1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
21 ***************************************************************************/
28 #include "mips_ejtag.h"
29 #include "mips32_dmaacc.h"
31 #include "mips64_pracc.h"
33 void mips_ejtag_set_instr(struct mips_ejtag
*ejtag_info
, uint32_t new_instr
)
35 assert(ejtag_info
->tap
!= NULL
);
36 struct jtag_tap
*tap
= ejtag_info
->tap
;
38 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
) {
40 struct scan_field field
;
41 field
.num_bits
= tap
->ir_length
;
45 buf_set_u32(t
, 0, field
.num_bits
, new_instr
);
47 field
.in_value
= NULL
;
49 jtag_add_ir_scan(tap
, &field
, TAP_IDLE
);
53 int mips_ejtag_get_idcode(struct mips_ejtag
*ejtag_info
)
55 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_IDCODE
);
57 ejtag_info
->idcode
= 0;
58 return mips_ejtag_drscan_32(ejtag_info
, &ejtag_info
->idcode
);
61 int mips_ejtag_get_impcode(struct mips_ejtag
*ejtag_info
)
63 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_IMPCODE
);
65 ejtag_info
->impcode
= 0;
66 return mips_ejtag_drscan_32(ejtag_info
, &ejtag_info
->impcode
);
69 void mips_ejtag_add_scan_96(struct mips_ejtag
*ejtag_info
, uint32_t ctrl
, uint32_t data
, uint8_t *in_scan_buf
)
71 assert(ejtag_info
->tap
!= NULL
);
72 struct jtag_tap
*tap
= ejtag_info
->tap
;
74 struct scan_field field
;
77 /* processor access "all" register 96 bit */
80 field
.out_value
= out_scan
;
81 buf_set_u32(out_scan
, 0, 32, ctrl
);
82 buf_set_u32(out_scan
+ 4, 0, 32, data
);
83 buf_set_u32(out_scan
+ 8, 0, 32, 0);
85 field
.in_value
= in_scan_buf
;
87 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
92 int mips_ejtag_drscan_64(struct mips_ejtag
*ejtag_info
, uint64_t *data
)
95 tap
= ejtag_info
->tap
;
99 struct scan_field field
;
100 uint8_t t
[8] = { 0 }, r
[8];
105 buf_set_u64(t
, 0, field
.num_bits
, *data
);
108 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
109 retval
= jtag_execute_queue();
110 if (retval
!= ERROR_OK
) {
111 LOG_ERROR("register read failed");
115 *data
= buf_get_u64(field
.in_value
, 0, 64);
122 void mips_ejtag_drscan_32_queued(struct mips_ejtag
*ejtag_info
, uint32_t data_out
, uint8_t *data_in
)
124 assert(ejtag_info
->tap
!= NULL
);
125 struct jtag_tap
*tap
= ejtag_info
->tap
;
127 struct scan_field field
;
130 uint8_t scan_out
[4] = { 0 };
131 field
.out_value
= scan_out
;
132 buf_set_u32(scan_out
, 0, field
.num_bits
, data_out
);
134 field
.in_value
= data_in
;
135 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
140 int mips_ejtag_drscan_32(struct mips_ejtag
*ejtag_info
, uint32_t *data
)
143 mips_ejtag_drscan_32_queued(ejtag_info
, *data
, scan_in
);
145 int retval
= jtag_execute_queue();
146 if (retval
!= ERROR_OK
) {
147 LOG_ERROR("register read failed");
151 *data
= buf_get_u32(scan_in
, 0, 32);
155 void mips_ejtag_drscan_32_out(struct mips_ejtag
*ejtag_info
, uint32_t data
)
157 mips_ejtag_drscan_32_queued(ejtag_info
, data
, NULL
);
160 int mips_ejtag_drscan_8(struct mips_ejtag
*ejtag_info
, uint8_t *data
)
162 assert(ejtag_info
->tap
!= NULL
);
163 struct jtag_tap
*tap
= ejtag_info
->tap
;
165 struct scan_field field
;
168 field
.out_value
= data
;
169 field
.in_value
= data
;
171 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
173 int retval
= jtag_execute_queue();
174 if (retval
!= ERROR_OK
) {
175 LOG_ERROR("register read failed");
181 void mips_ejtag_drscan_8_out(struct mips_ejtag
*ejtag_info
, uint8_t data
)
183 assert(ejtag_info
->tap
!= NULL
);
184 struct jtag_tap
*tap
= ejtag_info
->tap
;
186 struct scan_field field
;
189 field
.out_value
= &data
;
190 field
.in_value
= NULL
;
192 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
195 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
196 int mips_ejtag_config_step(struct mips_ejtag
*ejtag_info
, int enable_step
)
198 struct pracc_queue_info ctx
= {.ejtag_info
= ejtag_info
};
199 pracc_queue_init(&ctx
);
201 pracc_add(&ctx
, 0, MIPS32_MFC0(ctx
.isa
, 8, 23, 0)); /* move COP0 Debug to $8 */
202 pracc_add(&ctx
, 0, MIPS32_ORI(ctx
.isa
, 8, 8, 0x0100)); /* set SSt bit in debug reg */
204 pracc_add(&ctx
, 0, MIPS32_XORI(ctx
.isa
, 8, 8, 0x0100)); /* clear SSt bit in debug reg */
206 pracc_add(&ctx
, 0, MIPS32_MTC0(ctx
.isa
, 8, 23, 0)); /* move $8 to COP0 Debug */
207 pracc_add(&ctx
, 0, MIPS32_LUI(ctx
.isa
, 8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 bits of $8 */
208 pracc_add(&ctx
, 0, MIPS32_B(ctx
.isa
, NEG16((ctx
.code_count
+ 1) << ctx
.isa
))); /* jump to start */
209 pracc_add(&ctx
, 0, MIPS32_ORI(ctx
.isa
, 8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 bits of $8 */
211 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
, 1);
212 pracc_queue_free(&ctx
);
217 * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
218 * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
219 * For example bcm7401 and others. At leas on some
220 * CPUs, DebugMode wont start if this bit is not removed.
222 static int disable_dcr_mp(struct mips_ejtag
*ejtag_info
)
227 retval
= mips32_dmaacc_read_mem(ejtag_info
, EJTAG_DCR
, 4, 1, &dcr
);
228 if (retval
!= ERROR_OK
)
231 dcr
&= ~EJTAG_DCR_MP
;
232 retval
= mips32_dmaacc_write_mem(ejtag_info
, EJTAG_DCR
, 4, 1, &dcr
);
233 if (retval
!= ERROR_OK
)
237 LOG_ERROR("Failed to remove DCR MPbit!");
241 int mips_ejtag_enter_debug(struct mips_ejtag
*ejtag_info
)
244 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
246 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
) {
247 if (disable_dcr_mp(ejtag_info
) != ERROR_OK
)
251 /* set debug break bit */
252 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_JTAGBRK
;
253 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
255 /* break bit will be cleared by hardware */
256 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
257 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
258 LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32
"", ejtag_ctrl
);
259 if ((ejtag_ctrl
& EJTAG_CTRL_BRKST
) == 0)
264 LOG_ERROR("Failed to enter Debug Mode!");
268 int mips_ejtag_exit_debug(struct mips_ejtag
*ejtag_info
)
270 pa_list pracc_list
= {.instr
= MIPS32_DRET(ejtag_info
->isa
), .addr
= 0};
271 struct pracc_queue_info ctx
= {.max_code
= 1, .pracc_list
= &pracc_list
, .code_count
= 1, .store_count
= 0};
273 /* execute our dret instruction */
274 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
, 0); /* shift out instr, omit last check */
276 /* pic32mx workaround, false pending at low core clock */
277 jtag_add_sleep(1000);
281 /* mips_ejtag_init_mmr - assign Memory-Mapped Registers depending
284 static void mips_ejtag_init_mmr(struct mips_ejtag
*ejtag_info
)
286 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
) {
287 ejtag_info
->ejtag_ibs_addr
= EJTAG_V20_IBS
;
288 ejtag_info
->ejtag_iba0_addr
= EJTAG_V20_IBA0
;
289 ejtag_info
->ejtag_ibc_offs
= EJTAG_V20_IBC_OFFS
;
290 ejtag_info
->ejtag_ibm_offs
= EJTAG_V20_IBM_OFFS
;
292 ejtag_info
->ejtag_dbs_addr
= EJTAG_V20_DBS
;
293 ejtag_info
->ejtag_dba0_addr
= EJTAG_V20_DBA0
;
294 ejtag_info
->ejtag_dbc_offs
= EJTAG_V20_DBC_OFFS
;
295 ejtag_info
->ejtag_dbm_offs
= EJTAG_V20_DBM_OFFS
;
296 ejtag_info
->ejtag_dbv_offs
= EJTAG_V20_DBV_OFFS
;
298 ejtag_info
->ejtag_iba_step_size
= EJTAG_V20_IBAn_STEP
;
299 ejtag_info
->ejtag_dba_step_size
= EJTAG_V20_DBAn_STEP
;
301 ejtag_info
->ejtag_ibs_addr
= EJTAG_V25_IBS
;
302 ejtag_info
->ejtag_iba0_addr
= EJTAG_V25_IBA0
;
303 ejtag_info
->ejtag_ibm_offs
= EJTAG_V25_IBM_OFFS
;
304 ejtag_info
->ejtag_ibasid_offs
= EJTAG_V25_IBASID_OFFS
;
305 ejtag_info
->ejtag_ibc_offs
= EJTAG_V25_IBC_OFFS
;
307 ejtag_info
->ejtag_dbs_addr
= EJTAG_V25_DBS
;
308 ejtag_info
->ejtag_dba0_addr
= EJTAG_V25_DBA0
;
309 ejtag_info
->ejtag_dbm_offs
= EJTAG_V25_DBM_OFFS
;
310 ejtag_info
->ejtag_dbasid_offs
= EJTAG_V25_DBASID_OFFS
;
311 ejtag_info
->ejtag_dbc_offs
= EJTAG_V25_DBC_OFFS
;
312 ejtag_info
->ejtag_dbv_offs
= EJTAG_V25_DBV_OFFS
;
314 ejtag_info
->ejtag_iba_step_size
= EJTAG_V25_IBAn_STEP
;
315 ejtag_info
->ejtag_dba_step_size
= EJTAG_V25_DBAn_STEP
;
319 static void ejtag_v20_print_imp(struct mips_ejtag
*ejtag_info
)
321 LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
322 EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP
) ? " SDBBP_SPECIAL2" : " SDBBP",
323 EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT
) ? " EADDR>32bit" : " EADDR=32bit",
324 EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK
) ? " COMPLEX_BREAK" : "",
325 EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH
) ? " DCACHE_COH" : " DCACHE_NOT_COH",
326 EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH
) ? " ICACHE_COH" : " ICACHE_NOT_COH",
327 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB
) ? " noPB" : " PB",
328 EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB
) ? " noDB" : " DB",
329 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB
) ? " noIB" : " IB");
330 LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8
,
331 (uint8_t)((ejtag_info
->impcode
>> EJTAG_V20_IMP_BCHANNELS_SHIFT
) &
332 EJTAG_V20_IMP_BCHANNELS_MASK
));
335 static void ejtag_v26_print_imp(struct mips_ejtag
*ejtag_info
)
337 LOG_DEBUG("EJTAG v2.6: features:%s%s",
338 EJTAG_IMP_HAS(EJTAG_V26_IMP_R3K
) ? " R3k" : " R4k",
339 EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT
) ? " DINT" : "");
342 static void ejtag_main_print_imp(struct mips_ejtag
*ejtag_info
)
344 LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
345 EJTAG_IMP_HAS(EJTAG_IMP_ASID8
) ? " ASID_8" : "",
346 EJTAG_IMP_HAS(EJTAG_IMP_ASID6
) ? " ASID_6" : "",
347 EJTAG_IMP_HAS(EJTAG_IMP_MIPS16
) ? " MIPS16" : "",
348 EJTAG_IMP_HAS(EJTAG_IMP_NODMA
) ? " noDMA" : " DMA",
349 EJTAG_IMP_HAS(EJTAG_IMP_MIPS64
) ? " MIPS64" : " MIPS32");
351 switch (ejtag_info
->ejtag_version
) {
352 case EJTAG_VERSION_20
:
353 ejtag_v20_print_imp(ejtag_info
);
355 case EJTAG_VERSION_25
:
356 case EJTAG_VERSION_26
:
357 case EJTAG_VERSION_31
:
358 case EJTAG_VERSION_41
:
359 case EJTAG_VERSION_51
:
360 ejtag_v26_print_imp(ejtag_info
);
367 int mips_ejtag_init(struct mips_ejtag
*ejtag_info
)
369 int retval
= mips_ejtag_get_impcode(ejtag_info
);
370 if (retval
!= ERROR_OK
) {
371 LOG_ERROR("impcode read failed");
375 /* get ejtag version */
376 ejtag_info
->ejtag_version
= ((ejtag_info
->impcode
>> 29) & 0x07);
378 switch (ejtag_info
->ejtag_version
) {
379 case EJTAG_VERSION_20
:
380 LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
382 case EJTAG_VERSION_25
:
383 LOG_DEBUG("EJTAG: Version 2.5 Detected");
385 case EJTAG_VERSION_26
:
386 LOG_DEBUG("EJTAG: Version 2.6 Detected");
388 case EJTAG_VERSION_31
:
389 LOG_DEBUG("EJTAG: Version 3.1 Detected");
391 case EJTAG_VERSION_41
:
392 LOG_DEBUG("EJTAG: Version 4.1 Detected");
394 case EJTAG_VERSION_51
:
395 LOG_DEBUG("EJTAG: Version 5.1 Detected");
398 LOG_DEBUG("EJTAG: Unknown Version Detected");
401 ejtag_main_print_imp(ejtag_info
);
403 if ((ejtag_info
->impcode
& EJTAG_IMP_NODMA
) == 0) {
404 LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
405 "workaround current broken code.");
406 ejtag_info
->impcode
|= EJTAG_IMP_NODMA
;
409 ejtag_info
->ejtag_ctrl
= EJTAG_CTRL_PRACC
| EJTAG_CTRL_PROBEN
;
411 if (ejtag_info
->ejtag_version
!= EJTAG_VERSION_20
)
412 ejtag_info
->ejtag_ctrl
|= EJTAG_CTRL_ROCC
| EJTAG_CTRL_SETDEV
;
414 ejtag_info
->fast_access_save
= -1;
416 mips_ejtag_init_mmr(ejtag_info
);
421 int mips_ejtag_fastdata_scan(struct mips_ejtag
*ejtag_info
, int write_t
, uint32_t *data
)
423 assert(ejtag_info
->tap
!= NULL
);
424 struct jtag_tap
*tap
= ejtag_info
->tap
;
426 struct scan_field fields
[2];
428 /* fastdata 1-bit register */
429 fields
[0].num_bits
= 1;
432 fields
[0].out_value
= &spracc
;
433 fields
[0].in_value
= NULL
;
435 /* processor access data register 32 bit */
436 fields
[1].num_bits
= 32;
438 uint8_t t
[4] = {0, 0, 0, 0};
439 fields
[1].out_value
= t
;
442 fields
[1].in_value
= NULL
;
443 buf_set_u32(t
, 0, 32, *data
);
445 fields
[1].in_value
= (uint8_t *) data
;
447 jtag_add_dr_scan(tap
, 2, fields
, TAP_IDLE
);
449 if (!write_t
&& data
)
450 jtag_add_callback(mips_le_to_h_u32
,
451 (jtag_callback_data_t
) data
);
458 int mips64_ejtag_config_step(struct mips_ejtag
*ejtag_info
, bool enable_step
)
460 const uint32_t code_enable
[] = {
461 MIPS64_MTC0(1, 31, 0), /* move $1 to COP0 DeSave */
462 MIPS64_MFC0(1, 23, 0), /* move COP0 Debug to $1 */
463 MIPS64_ORI(1, 1, 0x0100), /* set SSt bit in debug reg */
464 MIPS64_MTC0(1, 23, 0), /* move $1 to COP0 Debug */
466 MIPS64_MFC0(1, 31, 0), /* move COP0 DeSave to $1 */
477 const uint32_t code_disable
[] = {
478 MIPS64_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
479 MIPS64_LUI(15, UPPER16(MIPS64_PRACC_STACK
)), /* $15 = MIPS64_PRACC_STACK */
480 MIPS64_ORI(15, 15, LOWER16(MIPS64_PRACC_STACK
)),
481 MIPS64_SD(1, 0, 15), /* sw $1,($15) */
482 MIPS64_SD(2, 0, 15), /* sw $2,($15) */
483 MIPS64_MFC0(1, 23, 0), /* move COP0 Debug to $1 */
484 MIPS64_LUI(2, 0xFFFF), /* $2 = 0xfffffeff */
485 MIPS64_ORI(2, 2, 0xFEFF),
487 MIPS64_MTC0(1, 23, 0), /* move $1 to COP0 Debug */
492 MIPS64_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
502 const uint32_t *code
= enable_step
? code_enable
: code_disable
;
503 unsigned code_len
= enable_step
? ARRAY_SIZE(code_enable
) :
504 ARRAY_SIZE(code_disable
);
506 return mips64_pracc_exec(ejtag_info
,
507 code_len
, code
, 0, NULL
, 0, NULL
);
510 int mips64_ejtag_exit_debug(struct mips_ejtag
*ejtag_info
)
512 const uint32_t code
[] = {
522 LOG_DEBUG("enter mips64_pracc_exec");
523 return mips64_pracc_exec(ejtag_info
,
524 ARRAY_SIZE(code
), code
, 0, NULL
, 0, NULL
);
527 int mips64_ejtag_fastdata_scan(struct mips_ejtag
*ejtag_info
, bool write_t
, uint64_t *data
)
529 struct jtag_tap
*tap
;
531 tap
= ejtag_info
->tap
;
534 struct scan_field fields
[2];
536 uint8_t t
[8] = {0, 0, 0, 0, 0, 0, 0, 0};
538 /* fastdata 1-bit register */
539 fields
[0].num_bits
= 1;
540 fields
[0].out_value
= &spracc
;
541 fields
[0].in_value
= NULL
;
543 /* processor access data register 64 bit */
544 fields
[1].num_bits
= 64;
545 fields
[1].out_value
= t
;
548 fields
[1].in_value
= NULL
;
549 buf_set_u64(t
, 0, 64, *data
);
551 fields
[1].in_value
= (uint8_t *) data
;
553 jtag_add_dr_scan(tap
, 2, fields
, TAP_IDLE
);
555 if (!write_t
&& data
)
556 jtag_add_callback(mips_le_to_h_u64
,
557 (jtag_callback_data_t
) data
);
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