bfd2cf56e7c29b1849a97377bbb92e2250386ba3
[openocd.git] / src / target / mips32.h
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2011 by Drasko DRASKOVIC *
8 * drasko.draskovic@gmail.com *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
22 ***************************************************************************/
23
24 #ifndef OPENOCD_TARGET_MIPS32_H
25 #define OPENOCD_TARGET_MIPS32_H
26
27 #include "target.h"
28 #include "mips32_pracc.h"
29
30 #define MIPS32_COMMON_MAGIC 0xB320B320
31
32 /**
33 * Memory segments (32bit kernel mode addresses)
34 * These are the traditional names used in the 32-bit universe.
35 */
36 #define KUSEG 0x00000000
37 #define KSEG0 0x80000000
38 #define KSEG1 0xa0000000
39 #define KSEG2 0xc0000000
40 #define KSEG3 0xe0000000
41
42 /** Returns the kernel segment base of a given address */
43 #define KSEGX(a) ((a) & 0xe0000000)
44
45 /** CP0 CONFIG regites fields */
46 #define MIPS32_CONFIG0_KU_SHIFT 25
47 #define MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT)
48
49 #define MIPS32_CONFIG0_K0_SHIFT 0
50 #define MIPS32_CONFIG0_K0_MASK (0x7 << MIPS32_CONFIG0_K0_SHIFT)
51
52 #define MIPS32_CONFIG0_K23_SHIFT 28
53 #define MIPS32_CONFIG0_K23_MASK (0x7 << MIPS32_CONFIG0_K23_SHIFT)
54
55 #define MIPS32_CONFIG0_AR_SHIFT 10
56 #define MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT)
57
58 #define MIPS32_CONFIG1_DL_SHIFT 10
59 #define MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT)
60
61 #define MIPS32_ARCH_REL1 0x0
62 #define MIPS32_ARCH_REL2 0x1
63
64 /* offsets into mips32 core register cache */
65 enum {
66 MIPS32_PC = 37,
67 MIPS32_FIR = 71,
68 MIPS32NUMCOREREGS
69 };
70
71 enum mips32_isa_mode {
72 MIPS32_ISA_MIPS32 = 0,
73 MIPS32_ISA_MIPS16E = 1,
74 };
75
76 struct mips32_comparator {
77 int used;
78 uint32_t bp_value;
79 uint32_t reg_address;
80 };
81
82 struct mips32_common {
83 uint32_t common_magic;
84 void *arch_info;
85 struct reg_cache *core_cache;
86 struct mips_ejtag ejtag_info;
87 uint32_t core_regs[MIPS32NUMCOREREGS];
88 enum mips32_isa_mode isa_mode;
89
90 /* working area for fastdata access */
91 struct working_area *fast_data_area;
92
93 int bp_scanned;
94 int num_inst_bpoints;
95 int num_data_bpoints;
96 int num_inst_bpoints_avail;
97 int num_data_bpoints_avail;
98 struct mips32_comparator *inst_break_list;
99 struct mips32_comparator *data_break_list;
100
101 /* register cache to processor synchronization */
102 int (*read_core_reg)(struct target *target, unsigned int num);
103 int (*write_core_reg)(struct target *target, unsigned int num);
104 };
105
106 static inline struct mips32_common *
107 target_to_mips32(struct target *target)
108 {
109 return target->arch_info;
110 }
111
112 struct mips32_core_reg {
113 uint32_t num;
114 struct target *target;
115 struct mips32_common *mips32_common;
116 };
117
118 struct mips32_algorithm {
119 int common_magic;
120 enum mips32_isa_mode isa_mode;
121 };
122
123 #define MIPS32_OP_ADDIU 0x21
124 #define MIPS32_OP_ANDI 0x0C
125 #define MIPS32_OP_BEQ 0x04
126 #define MIPS32_OP_BGTZ 0x07
127 #define MIPS32_OP_BNE 0x05
128 #define MIPS32_OP_ADDI 0x08
129 #define MIPS32_OP_AND 0x24
130 #define MIPS32_OP_CACHE 0x2F
131 #define MIPS32_OP_COP0 0x10
132 #define MIPS32_OP_J 0x02
133 #define MIPS32_OP_JR 0x08
134 #define MIPS32_OP_LUI 0x0F
135 #define MIPS32_OP_LW 0x23
136 #define MIPS32_OP_LBU 0x24
137 #define MIPS32_OP_LHU 0x25
138 #define MIPS32_OP_MFHI 0x10
139 #define MIPS32_OP_MTHI 0x11
140 #define MIPS32_OP_MFLO 0x12
141 #define MIPS32_OP_MTLO 0x13
142 #define MIPS32_OP_RDHWR 0x3B
143 #define MIPS32_OP_SB 0x28
144 #define MIPS32_OP_SH 0x29
145 #define MIPS32_OP_SW 0x2B
146 #define MIPS32_OP_ORI 0x0D
147 #define MIPS32_OP_XORI 0x0E
148 #define MIPS32_OP_XOR 0x26
149 #define MIPS32_OP_SLTU 0x2B
150 #define MIPS32_OP_SRL 0x03
151 #define MIPS32_OP_SYNCI 0x1F
152
153 #define MIPS32_OP_REGIMM 0x01
154 #define MIPS32_OP_SDBBP 0x3F
155 #define MIPS32_OP_SPECIAL 0x00
156 #define MIPS32_OP_SPECIAL2 0x07
157 #define MIPS32_OP_SPECIAL3 0x1F
158
159 #define MIPS32_COP0_MF 0x00
160 #define MIPS32_COP0_MT 0x04
161
162 #define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) \
163 (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct))
164 #define MIPS32_I_INST(opcode, rs, rt, immd) \
165 (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | (immd))
166 #define MIPS32_J_INST(opcode, addr) (((opcode) << 26) | (addr))
167
168 #define MIPS32_NOP 0
169 #define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
170 #define MIPS32_ADDU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDIU)
171 #define MIPS32_AND(reg, off, val) MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
172 #define MIPS32_ANDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ANDI, src, tar, val)
173 #define MIPS32_B(off) MIPS32_BEQ(0, 0, off)
174 #define MIPS32_BEQ(src, tar, off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
175 #define MIPS32_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)
176 #define MIPS32_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
177 #define MIPS32_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)
178 #define MIPS32_J(tar) MIPS32_J_INST(MIPS32_OP_J, tar)
179 #define MIPS32_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
180 #define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
181 #define MIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
182 #define MIPS32_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
183 #define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
184 #define MIPS32_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
185 #define MIPS32_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
186 #define MIPS32_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
187 #define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
188 #define MIPS32_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
189 #define MIPS32_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
190 #define MIPS32_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
191 #define MIPS32_XORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val)
192 #define MIPS32_RDHWR(tar, dst) MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)
193 #define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
194 #define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
195 #define MIPS32_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
196 #define MIPS32_XOR(reg, val1, val2) MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR)
197 #define MIPS32_SRL(reg, src, off) MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL)
198 #define MIPS32_SLTU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)
199 #define MIPS32_SYNCI(off, base) MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off)
200
201 #define MIPS32_SYNC 0xF
202 #define MIPS32_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */
203
204 /**
205 * Cache operations definitions
206 * Operation field is 5 bits long :
207 * 1) bits 1..0 hold cache type
208 * 2) bits 4..2 hold operation code
209 */
210 #define MIPS32_CACHE_D_HIT_WRITEBACK ((0x1 << 0) | (0x6 << 2))
211 #define MIPS32_CACHE_I_HIT_INVALIDATE ((0x0 << 0) | (0x4 << 2))
212
213 /* ejtag specific instructions */
214 #define MIPS32_DRET 0x4200001F
215 #define MIPS32_SDBBP 0x7000003F /* MIPS32_J_INST(MIPS32_OP_SPECIAL2, MIPS32_OP_SDBBP) */
216 #define MIPS16_SDBBP 0xE801
217
218 extern const struct command_registration mips32_command_handlers[];
219
220 int mips32_arch_state(struct target *target);
221
222 int mips32_init_arch_info(struct target *target,
223 struct mips32_common *mips32, struct jtag_tap *tap);
224
225 int mips32_restore_context(struct target *target);
226 int mips32_save_context(struct target *target);
227
228 struct reg_cache *mips32_build_reg_cache(struct target *target);
229
230 int mips32_run_algorithm(struct target *target,
231 int num_mem_params, struct mem_param *mem_params,
232 int num_reg_params, struct reg_param *reg_params,
233 uint32_t entry_point, uint32_t exit_point,
234 int timeout_ms, void *arch_info);
235
236 int mips32_configure_break_unit(struct target *target);
237
238 int mips32_enable_interrupts(struct target *target, int enable);
239
240 int mips32_examine(struct target *target);
241
242 int mips32_register_commands(struct command_context *cmd_ctx);
243
244 int mips32_get_gdb_reg_list(struct target *target,
245 struct reg **reg_list[], int *reg_list_size,
246 enum target_register_class reg_class);
247 int mips32_checksum_memory(struct target *target, uint32_t address,
248 uint32_t count, uint32_t *checksum);
249 int mips32_blank_check_memory(struct target *target,
250 uint32_t address, uint32_t count, uint32_t *blank);
251
252 #endif /* OPENOCD_TARGET_MIPS32_H */