src/target/mips32.h

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 #ifndef MIPS32_H
  24 #define MIPS32_H
  25
  26 #include "target.h"
  27 #include "mips32_pracc.h"
  28
  29 #define MIPS32_COMMON_MAGIC             0xB320B320
  30
  31 /* offsets into mips32 core register cache */
  32 enum
  33 {
  34         MIPS32_PC = 37,
  35         MIPS32NUMCOREREGS
  36 };
  37
  38 enum mips32_isa_mode
  39 {
  40         MIPS32_ISA_MIPS32 = 0,
  41         MIPS32_ISA_MIPS16E = 1,
  42 };
  43
  44 extern const char *mips_isa_strings[];
  45
  46 struct mips32_comparator
  47 {
  48         int used;
  49         uint32_t bp_value;
  50         uint32_t reg_address;
  51 };
  52
  53 struct mips32_common
  54 {
  55         uint32_t common_magic;
  56         void *arch_info;
  57         struct reg_cache *core_cache;
  58         struct mips_ejtag ejtag_info;
  59         uint32_t core_regs[MIPS32NUMCOREREGS];
  60         enum mips32_isa_mode isa_mode;
  61
  62         int bp_scanned;
  63         int num_inst_bpoints;
  64         int num_data_bpoints;
  65         int num_inst_bpoints_avail;
  66         int num_data_bpoints_avail;
  67         struct mips32_comparator *inst_break_list;
  68         struct mips32_comparator *data_break_list;
  69
  70         /* register cache to processor synchronization */
  71         int (*read_core_reg)(struct target *target, int num);
  72         int (*write_core_reg)(struct target *target, int num);
  73 };
  74
  75 static inline struct mips32_common *
  76 target_to_mips32(struct target *target)
  77 {
  78         return target->arch_info;
  79 }
  80
  81 struct mips32_core_reg
  82 {
  83         uint32_t num;
  84         struct target *target;
  85         struct mips32_common *mips32_common;
  86 };
  87
  88 #define MIPS32_OP_BEQ   0x04
  89 #define MIPS32_OP_BNE   0x05
  90 #define MIPS32_OP_ADDI  0x08
  91 #define MIPS32_OP_AND   0x24
  92 #define MIPS32_OP_COP0  0x10
  93 #define MIPS32_OP_JR    0x08
  94 #define MIPS32_OP_LUI   0x0F
  95 #define MIPS32_OP_LW    0x23
  96 #define MIPS32_OP_LBU   0x24
  97 #define MIPS32_OP_LHU   0x25
  98 #define MIPS32_OP_MFHI  0x10
  99 #define MIPS32_OP_MTHI  0x11
 100 #define MIPS32_OP_MFLO  0x12
 101 #define MIPS32_OP_MTLO  0x13
 102 #define MIPS32_OP_SB    0x28
 103 #define MIPS32_OP_SH    0x29
 104 #define MIPS32_OP_SW    0x2B
 105 #define MIPS32_OP_ORI   0x0D
 106
 107 #define MIPS32_COP0_MF  0x00
 108 #define MIPS32_COP0_MT  0x04
 109
 110 #define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct))
 111 #define MIPS32_I_INST(opcode, rs, rt, immd)     (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd))
 112 #define MIPS32_J_INST(opcode, addr)     (((opcode) << 26) |(addr))
 113
 114 #define MIPS32_NOP                                      0
 115 #define MIPS32_ADDI(tar, src, val)      MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
 116 #define MIPS32_AND(reg, off, val)       MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
 117 #define MIPS32_B(off)                           MIPS32_BEQ(0, 0, off)
 118 #define MIPS32_BEQ(src,tar,off)         MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
 119 #define MIPS32_BNE(src,tar,off)         MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
 120 #define MIPS32_JR(reg)                          MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
 121 #define MIPS32_MFC0(gpr, cpr, sel)      MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
 122 #define MIPS32_MTC0(gpr,cpr, sel)       MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
 123 #define MIPS32_LBU(reg, off, base)      MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
 124 #define MIPS32_LHU(reg, off, base)      MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
 125 #define MIPS32_LUI(reg, val)            MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
 126 #define MIPS32_LW(reg, off, base)       MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
 127 #define MIPS32_MFLO(reg)                        MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
 128 #define MIPS32_MFHI(reg)                        MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
 129 #define MIPS32_MTLO(reg)                        MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
 130 #define MIPS32_MTHI(reg)                        MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
 131 #define MIPS32_ORI(src, tar, val)       MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
 132 #define MIPS32_SB(reg, off, base)       MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
 133 #define MIPS32_SH(reg, off, base)       MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
 134 #define MIPS32_SW(reg, off, base)       MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
 135
 136 /* ejtag specific instructions */
 137 #define MIPS32_DRET                                     0x4200001F
 138 #define MIPS32_SDBBP                            0x7000003F
 139 #define MIPS16_SDBBP                            0xE801
 140
 141 int mips32_arch_state(struct target *target);
 142
 143 int mips32_init_arch_info(struct target *target,
 144                 struct mips32_common *mips32, struct jtag_tap *tap);
 145
 146 int mips32_restore_context(struct target *target);
 147 int mips32_save_context(struct target *target);
 148
 149 struct reg_cache *mips32_build_reg_cache(struct target *target);
 150
 151 int mips32_run_algorithm(struct target *target,
 152                 int num_mem_params, struct mem_param *mem_params,
 153                 int num_reg_params, struct reg_param *reg_params,
 154                 uint32_t entry_point, uint32_t exit_point,
 155                 int timeout_ms, void *arch_info);
 156
 157 int mips32_configure_break_unit(struct target *target);
 158
 159 int mips32_enable_interrupts(struct target *target, int enable);
 160
 161 int mips32_examine(struct target *target);
 162
 163 int mips32_register_commands(struct command_context *cmd_ctx);
 164
 165 int mips32_get_gdb_reg_list(struct target *target,
 166                 struct reg **reg_list[], int *reg_list_size);
 167
 168 #endif  /*MIPS32_H*/