- correct the register hi/lo read - wrong way round
[openocd.git] / src / target / mips32.h
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 #ifndef MIPS32_H
24 #define MIPS32_H
25
26 #include "target.h"
27 #include "register.h"
28 #include "mips_ejtag.h"
29 #include "mips32_pracc.h"
30
31 #define MIPS32_COMMON_MAGIC 0xB320B320
32
33 /* offsets into mips32 core register cache */
34 enum
35 {
36 MIPS32_PC = 37,
37 MIPS32NUMCOREREGS
38 };
39
40 typedef struct mips32_common_s
41 {
42 int common_magic;
43 void *arch_info;
44 reg_cache_t *core_cache;
45 mips_ejtag_t ejtag_info;
46 u32 core_regs[MIPS32NUMCOREREGS];
47
48 /* register cache to processor synchronization */
49 int (*read_core_reg)(struct target_s *target, int num);
50 int (*write_core_reg)(struct target_s *target, int num);
51 } mips32_common_t;
52
53 typedef struct mips32_core_reg_s
54 {
55 u32 num;
56 target_t *target;
57 mips32_common_t *mips32_common;
58 } mips32_core_reg_t;
59
60 #define MIPS32_OP_BEQ 0x04
61 #define MIPS32_OP_ADDI 0x08
62 #define MIPS32_OP_AND 0x24
63 #define MIPS32_OP_COP0 0x10
64 #define MIPS32_OP_LUI 0x0F
65 #define MIPS32_OP_LW 0x23
66 #define MIPS32_OP_LBU 0x24
67 #define MIPS32_OP_LHU 0x25
68 #define MIPS32_OP_MFHI 0x10
69 #define MIPS32_OP_MTHI 0x11
70 #define MIPS32_OP_MFLO 0x12
71 #define MIPS32_OP_MTLO 0x13
72 #define MIPS32_OP_SB 0x28
73 #define MIPS32_OP_SH 0x29
74 #define MIPS32_OP_SW 0x2B
75 #define MIPS32_OP_ORI 0x0D
76
77 #define MIPS32_COP0_MF 0x00
78 #define MIPS32_COP0_MT 0x04
79
80 #define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode)<<26) |((rs)<<21)|((rt)<<16)|((rd)<<11)| ((shamt)<<5) | (funct))
81 #define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode)<<26) |((rs)<<21)|((rt)<<16)|(immd))
82 #define MIPS32_J_INST(opcode, addr) (((opcode)<<26) |(addr))
83
84 #define MIPS32_NOP 0
85 #define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
86 #define MIPS32_AND(reg, off, val) MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
87 #define MIPS32_B(off) MIPS32_BEQ(0, 0, off)
88 #define MIPS32_BEQ(src,tar,off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
89 #define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
90 #define MIPS32_MTC0(gpr,cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
91 #define MIPS32_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
92 #define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
93 #define MIPS32_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
94 #define MIPS32_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
95 #define MIPS32_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
96 #define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
97 #define MIPS32_MTLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTLO)
98 #define MIPS32_MTHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTHI)
99 #define MIPS32_ORI(src, tar, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
100 #define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
101 #define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
102 #define MIPS32_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
103 #define MIPS32_DRET 0x4200001F
104
105 extern int mips32_arch_state(struct target_s *target);
106 extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_pos, const char *variant);
107 extern int mips32_restore_context(target_t *target);
108 extern int mips32_save_context(target_t *target);
109 extern reg_cache_t *mips32_build_reg_cache(target_t *target);
110 extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
111
112 extern int mips32_register_commands(struct command_context_s *cmd_ctx);
113 extern int mips32_invalidate_core_regs(target_t *target);
114 extern int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
115
116 #endif /*MIPS32_H*/