src/target/mips32.h

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
   8  *   drasko.draskovic@gmail.com                                            *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  ***************************************************************************/
  25
  26 #ifndef MIPS32_H
  27 #define MIPS32_H
  28
  29 #include "target.h"
  30 #include "mips32_pracc.h"
  31
  32 #define MIPS32_COMMON_MAGIC             0xB320B320
  33
  34 /* offsets into mips32 core register cache */
  35 enum
  36 {
  37         MIPS32_PC = 37,
  38         MIPS32NUMCOREREGS
  39 };
  40
  41 enum mips32_isa_mode
  42 {
  43         MIPS32_ISA_MIPS32 = 0,
  44         MIPS32_ISA_MIPS16E = 1,
  45 };
  46
  47 struct mips32_comparator
  48 {
  49         int used;
  50         uint32_t bp_value;
  51         uint32_t reg_address;
  52 };
  53
  54 struct mips32_common
  55 {
  56         uint32_t common_magic;
  57         void *arch_info;
  58         struct reg_cache *core_cache;
  59         struct mips_ejtag ejtag_info;
  60         uint32_t core_regs[MIPS32NUMCOREREGS];
  61         enum mips32_isa_mode isa_mode;
  62
  63         /* working area for fastdata access */
  64         struct working_area *fast_data_area;
  65
  66         int bp_scanned;
  67         int num_inst_bpoints;
  68         int num_data_bpoints;
  69         int num_inst_bpoints_avail;
  70         int num_data_bpoints_avail;
  71         struct mips32_comparator *inst_break_list;
  72         struct mips32_comparator *data_break_list;
  73
  74         /* register cache to processor synchronization */
  75         int (*read_core_reg)(struct target *target, int num);
  76         int (*write_core_reg)(struct target *target, int num);
  77 };
  78
  79 static inline struct mips32_common *
  80 target_to_mips32(struct target *target)
  81 {
  82         return target->arch_info;
  83 }
  84
  85 struct mips32_core_reg
  86 {
  87         uint32_t num;
  88         struct target *target;
  89         struct mips32_common *mips32_common;
  90 };
  91
  92 struct mips32_algorithm
  93 {
  94         int common_magic;
  95         enum mips32_isa_mode isa_mode;
  96 };
  97
  98 #define MIPS32_OP_BEQ   0x04
  99 #define MIPS32_OP_BNE   0x05
 100 #define MIPS32_OP_ADDI  0x08
 101 #define MIPS32_OP_AND   0x24
 102 #define MIPS32_OP_COP0  0x10
 103 #define MIPS32_OP_JR    0x08
 104 #define MIPS32_OP_LUI   0x0F
 105 #define MIPS32_OP_LW    0x23
 106 #define MIPS32_OP_LBU   0x24
 107 #define MIPS32_OP_LHU   0x25
 108 #define MIPS32_OP_MFHI  0x10
 109 #define MIPS32_OP_MTHI  0x11
 110 #define MIPS32_OP_MFLO  0x12
 111 #define MIPS32_OP_MTLO  0x13
 112 #define MIPS32_OP_SB    0x28
 113 #define MIPS32_OP_SH    0x29
 114 #define MIPS32_OP_SW    0x2B
 115 #define MIPS32_OP_ORI   0x0D
 116 #define MIPS32_OP_XOR   0x26
 117 #define MIPS32_OP_SRL   0x03
 118
 119 #define MIPS32_COP0_MF  0x00
 120 #define MIPS32_COP0_MT  0x04
 121
 122 #define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct))
 123 #define MIPS32_I_INST(opcode, rs, rt, immd)     (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd))
 124 #define MIPS32_J_INST(opcode, addr)     (((opcode) << 26) |(addr))
 125
 126 #define MIPS32_NOP                                      0
 127 #define MIPS32_ADDI(tar, src, val)      MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
 128 #define MIPS32_AND(reg, off, val)       MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
 129 #define MIPS32_B(off)                           MIPS32_BEQ(0, 0, off)
 130 #define MIPS32_BEQ(src,tar,off)         MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
 131 #define MIPS32_BNE(src,tar,off)         MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
 132 #define MIPS32_JR(reg)                          MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
 133 #define MIPS32_MFC0(gpr, cpr, sel)      MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
 134 #define MIPS32_MTC0(gpr,cpr, sel)       MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
 135 #define MIPS32_LBU(reg, off, base)      MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
 136 #define MIPS32_LHU(reg, off, base)      MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
 137 #define MIPS32_LUI(reg, val)            MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
 138 #define MIPS32_LW(reg, off, base)       MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
 139 #define MIPS32_MFLO(reg)                        MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
 140 #define MIPS32_MFHI(reg)                        MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
 141 #define MIPS32_MTLO(reg)                        MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
 142 #define MIPS32_MTHI(reg)                        MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
 143 #define MIPS32_ORI(tar, src, val)       MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
 144 #define MIPS32_SB(reg, off, base)       MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
 145 #define MIPS32_SH(reg, off, base)       MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
 146 #define MIPS32_SW(reg, off, base)       MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
 147 #define MIPS32_XOR(reg, val1, val2)     MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR)
 148 #define MIPS32_SRL(reg, src, off)       MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL)
 149
 150 /* ejtag specific instructions */
 151 #define MIPS32_DRET                                     0x4200001F
 152 #define MIPS32_SDBBP                            0x7000003F
 153 #define MIPS16_SDBBP                            0xE801
 154
 155 extern const struct command_registration mips32_command_handlers[];
 156
 157 int mips32_arch_state(struct target *target);
 158
 159 int mips32_init_arch_info(struct target *target,
 160                 struct mips32_common *mips32, struct jtag_tap *tap);
 161
 162 int mips32_restore_context(struct target *target);
 163 int mips32_save_context(struct target *target);
 164
 165 struct reg_cache *mips32_build_reg_cache(struct target *target);
 166
 167 int mips32_run_algorithm(struct target *target,
 168                 int num_mem_params, struct mem_param *mem_params,
 169                 int num_reg_params, struct reg_param *reg_params,
 170                 uint32_t entry_point, uint32_t exit_point,
 171                 int timeout_ms, void *arch_info);
 172
 173 int mips32_configure_break_unit(struct target *target);
 174
 175 int mips32_enable_interrupts(struct target *target, int enable);
 176
 177 int mips32_examine(struct target *target);
 178
 179 int mips32_register_commands(struct command_context *cmd_ctx);
 180
 181 int mips32_get_gdb_reg_list(struct target *target,
 182                 struct reg **reg_list[], int *reg_list_size);
 183 int mips32_checksum_memory(struct target *target, uint32_t address,
 184                 uint32_t count, uint32_t* checksum);
 185 int mips32_blank_check_memory(struct target *target,
 186                 uint32_t address, uint32_t count, uint32_t* blank);
 187
 188 #endif  /*MIPS32_H*/