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target: remove unused "bitfield" infrastructure
[openocd.git] / src / target / mips32.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "mips32.h"
30
31
32 char* mips32_core_reg_list[] =
33 {
34 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
35 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
36 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
37 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
38 "status", "lo", "hi", "badvaddr", "cause", "pc"
39 };
40
41 struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
42 {
43 {0, NULL, NULL},
44 {1, NULL, NULL},
45 {2, NULL, NULL},
46 {3, NULL, NULL},
47 {4, NULL, NULL},
48 {5, NULL, NULL},
49 {6, NULL, NULL},
50 {7, NULL, NULL},
51 {8, NULL, NULL},
52 {9, NULL, NULL},
53 {10, NULL, NULL},
54 {11, NULL, NULL},
55 {12, NULL, NULL},
56 {13, NULL, NULL},
57 {14, NULL, NULL},
58 {15, NULL, NULL},
59 {16, NULL, NULL},
60 {17, NULL, NULL},
61 {18, NULL, NULL},
62 {19, NULL, NULL},
63 {20, NULL, NULL},
64 {21, NULL, NULL},
65 {22, NULL, NULL},
66 {23, NULL, NULL},
67 {24, NULL, NULL},
68 {25, NULL, NULL},
69 {26, NULL, NULL},
70 {27, NULL, NULL},
71 {28, NULL, NULL},
72 {29, NULL, NULL},
73 {30, NULL, NULL},
74 {31, NULL, NULL},
75
76 {32, NULL, NULL},
77 {33, NULL, NULL},
78 {34, NULL, NULL},
79 {35, NULL, NULL},
80 {36, NULL, NULL},
81 {37, NULL, NULL},
82 };
83
84 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
85 * we also add 18 unknown registers to handle gdb requests */
86
87 #define MIPS32NUMFPREGS 34 + 18
88
89 uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
90
91 struct reg mips32_gdb_dummy_fp_reg =
92 {
93 .name = "GDB dummy floating-point register",
94 .value = mips32_gdb_dummy_fp_value,
95 .dirty = 0,
96 .valid = 1,
97 .size = 32,
98 .arch_info = NULL,
99 .arch_type = 0,
100 };
101
102 int mips32_core_reg_arch_type = -1;
103
104 int mips32_get_core_reg(struct reg *reg)
105 {
106 int retval;
107 struct mips32_core_reg *mips32_reg = reg->arch_info;
108 struct target *target = mips32_reg->target;
109 struct mips32_common *mips32_target = target->arch_info;
110
111 if (target->state != TARGET_HALTED)
112 {
113 return ERROR_TARGET_NOT_HALTED;
114 }
115
116 retval = mips32_target->read_core_reg(target, mips32_reg->num);
117
118 return retval;
119 }
120
121 int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
122 {
123 struct mips32_core_reg *mips32_reg = reg->arch_info;
124 struct target *target = mips32_reg->target;
125 uint32_t value = buf_get_u32(buf, 0, 32);
126
127 if (target->state != TARGET_HALTED)
128 {
129 return ERROR_TARGET_NOT_HALTED;
130 }
131
132 buf_set_u32(reg->value, 0, 32, value);
133 reg->dirty = 1;
134 reg->valid = 1;
135
136 return ERROR_OK;
137 }
138
139 int mips32_read_core_reg(struct target *target, int num)
140 {
141 uint32_t reg_value;
142 struct mips32_core_reg *mips_core_reg;
143
144 /* get pointers to arch-specific information */
145 struct mips32_common *mips32 = target->arch_info;
146
147 if ((num < 0) || (num >= MIPS32NUMCOREREGS))
148 return ERROR_INVALID_ARGUMENTS;
149
150 mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
151 reg_value = mips32->core_regs[num];
152 buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
153 mips32->core_cache->reg_list[num].valid = 1;
154 mips32->core_cache->reg_list[num].dirty = 0;
155
156 return ERROR_OK;
157 }
158
159 int mips32_write_core_reg(struct target *target, int num)
160 {
161 uint32_t reg_value;
162 struct mips32_core_reg *mips_core_reg;
163
164 /* get pointers to arch-specific information */
165 struct mips32_common *mips32 = target->arch_info;
166
167 if ((num < 0) || (num >= MIPS32NUMCOREREGS))
168 return ERROR_INVALID_ARGUMENTS;
169
170 reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
171 mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
172 mips32->core_regs[num] = reg_value;
173 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
174 mips32->core_cache->reg_list[num].valid = 1;
175 mips32->core_cache->reg_list[num].dirty = 0;
176
177 return ERROR_OK;
178 }
179
180 int mips32_invalidate_core_regs(struct target *target)
181 {
182 /* get pointers to arch-specific information */
183 struct mips32_common *mips32 = target->arch_info;
184 int i;
185
186 for (i = 0; i < mips32->core_cache->num_regs; i++)
187 {
188 mips32->core_cache->reg_list[i].valid = 0;
189 mips32->core_cache->reg_list[i].dirty = 0;
190 }
191
192 return ERROR_OK;
193 }
194
195 int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
196 {
197 /* get pointers to arch-specific information */
198 struct mips32_common *mips32 = target->arch_info;
199 int i;
200
201 /* include floating point registers */
202 *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
203 *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
204
205 for (i = 0; i < MIPS32NUMCOREREGS; i++)
206 {
207 (*reg_list)[i] = &mips32->core_cache->reg_list[i];
208 }
209
210 /* add dummy floating points regs */
211 for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
212 {
213 (*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
214 }
215
216 return ERROR_OK;
217 }
218
219 int mips32_save_context(struct target *target)
220 {
221 int i;
222
223 /* get pointers to arch-specific information */
224 struct mips32_common *mips32 = target->arch_info;
225 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
226
227 /* read core registers */
228 mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
229
230 for (i = 0; i < MIPS32NUMCOREREGS; i++)
231 {
232 if (!mips32->core_cache->reg_list[i].valid)
233 {
234 mips32->read_core_reg(target, i);
235 }
236 }
237
238 return ERROR_OK;
239 }
240
241 int mips32_restore_context(struct target *target)
242 {
243 int i;
244
245 /* get pointers to arch-specific information */
246 struct mips32_common *mips32 = target->arch_info;
247 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
248
249 for (i = 0; i < MIPS32NUMCOREREGS; i++)
250 {
251 if (mips32->core_cache->reg_list[i].dirty)
252 {
253 mips32->write_core_reg(target, i);
254 }
255 }
256
257 /* write core regs */
258 mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
259
260 return ERROR_OK;
261 }
262
263 int mips32_arch_state(struct target *target)
264 {
265 struct mips32_common *mips32 = target->arch_info;
266
267 if (mips32->common_magic != MIPS32_COMMON_MAGIC)
268 {
269 LOG_ERROR("BUG: called for a non-MIPS32 target");
270 exit(-1);
271 }
272
273 LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
274 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
275 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
276
277 return ERROR_OK;
278 }
279
280 struct reg_cache *mips32_build_reg_cache(struct target *target)
281 {
282 /* get pointers to arch-specific information */
283 struct mips32_common *mips32 = target->arch_info;
284
285 int num_regs = MIPS32NUMCOREREGS;
286 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
287 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
288 struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
289 struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
290 int i;
291
292 if (mips32_core_reg_arch_type == -1)
293 mips32_core_reg_arch_type = register_reg_arch_type(mips32_get_core_reg, mips32_set_core_reg);
294
295 register_init_dummy(&mips32_gdb_dummy_fp_reg);
296
297 /* Build the process context cache */
298 cache->name = "mips32 registers";
299 cache->next = NULL;
300 cache->reg_list = reg_list;
301 cache->num_regs = num_regs;
302 (*cache_p) = cache;
303 mips32->core_cache = cache;
304
305 for (i = 0; i < num_regs; i++)
306 {
307 arch_info[i] = mips32_core_reg_list_arch_info[i];
308 arch_info[i].target = target;
309 arch_info[i].mips32_common = mips32;
310 reg_list[i].name = mips32_core_reg_list[i];
311 reg_list[i].size = 32;
312 reg_list[i].value = calloc(1, 4);
313 reg_list[i].dirty = 0;
314 reg_list[i].valid = 0;
315 reg_list[i].arch_type = mips32_core_reg_arch_type;
316 reg_list[i].arch_info = &arch_info[i];
317 }
318
319 return cache;
320 }
321
322 int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
323 {
324 target->arch_info = mips32;
325 mips32->common_magic = MIPS32_COMMON_MAGIC;
326
327 /* has breakpoint/watchpint unit been scanned */
328 mips32->bp_scanned = 0;
329 mips32->data_break_list = NULL;
330
331 mips32->ejtag_info.tap = tap;
332 mips32->read_core_reg = mips32_read_core_reg;
333 mips32->write_core_reg = mips32_write_core_reg;
334
335 return ERROR_OK;
336 }
337
338 int mips32_register_commands(struct command_context *cmd_ctx)
339 {
340 return ERROR_OK;
341 }
342
343 int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
344 {
345 /*TODO*/
346 return ERROR_OK;
347 }
348
349 int mips32_examine(struct target *target)
350 {
351 struct mips32_common *mips32 = target->arch_info;
352
353 if (!target_was_examined(target))
354 {
355 target_set_examined(target);
356
357 /* we will configure later */
358 mips32->bp_scanned = 0;
359 mips32->num_inst_bpoints = 0;
360 mips32->num_data_bpoints = 0;
361 mips32->num_inst_bpoints_avail = 0;
362 mips32->num_data_bpoints_avail = 0;
363 }
364
365 return ERROR_OK;
366 }
367
368 int mips32_configure_break_unit(struct target *target)
369 {
370 /* get pointers to arch-specific information */
371 struct mips32_common *mips32 = target->arch_info;
372 int retval;
373 uint32_t dcr, bpinfo;
374 int i;
375
376 if (mips32->bp_scanned)
377 return ERROR_OK;
378
379 /* get info about breakpoint support */
380 if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
381 return retval;
382
383 if (dcr & (1 << 16))
384 {
385 /* get number of inst breakpoints */
386 if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
387 return retval;
388
389 mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
390 mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
391 mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator));
392 for (i = 0; i < mips32->num_inst_bpoints; i++)
393 {
394 mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
395 }
396
397 /* clear IBIS reg */
398 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
399 return retval;
400 }
401
402 if (dcr & (1 << 17))
403 {
404 /* get number of data breakpoints */
405 if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
406 return retval;
407
408 mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
409 mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
410 mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator));
411 for (i = 0; i < mips32->num_data_bpoints; i++)
412 {
413 mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
414 }
415
416 /* clear DBIS reg */
417 if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
418 return retval;
419 }
420
421 LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
422
423 mips32->bp_scanned = 1;
424
425 return ERROR_OK;
426 }
427
428 int mips32_enable_interrupts(struct target *target, int enable)
429 {
430 int retval;
431 int update = 0;
432 uint32_t dcr;
433
434 /* read debug control register */
435 if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
436 return retval;
437
438 if (enable)
439 {
440 if (!(dcr & (1 << 4)))
441 {
442 /* enable interrupts */
443 dcr |= (1 << 4);
444 update = 1;
445 }
446 }
447 else
448 {
449 if (dcr & (1 << 4))
450 {
451 /* disable interrupts */
452 dcr &= ~(1 << 4);
453 update = 1;
454 }
455 }
456
457 if (update)
458 {
459 if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
460 return retval;
461 }
462
463 return ERROR_OK;
464 }
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