1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
32 char* mips32_core_reg_list
[] =
34 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
35 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
36 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
37 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
38 "status", "lo", "hi", "badvaddr", "cause", "pc"
41 const char *mips_isa_strings
[] =
46 struct mips32_core_reg mips32_core_reg_list_arch_info
[MIPS32NUMCOREREGS
] =
89 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
90 * we also add 18 unknown registers to handle gdb requests */
92 #define MIPS32NUMFPREGS 34 + 18
94 uint8_t mips32_gdb_dummy_fp_value
[] = {0, 0, 0, 0};
96 struct reg mips32_gdb_dummy_fp_reg
=
98 .name
= "GDB dummy floating-point register",
99 .value
= mips32_gdb_dummy_fp_value
,
106 int mips32_get_core_reg(struct reg
*reg
)
109 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
110 struct target
*target
= mips32_reg
->target
;
111 struct mips32_common
*mips32_target
= target_to_mips32(target
);
113 if (target
->state
!= TARGET_HALTED
)
115 return ERROR_TARGET_NOT_HALTED
;
118 retval
= mips32_target
->read_core_reg(target
, mips32_reg
->num
);
123 int mips32_set_core_reg(struct reg
*reg
, uint8_t *buf
)
125 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
126 struct target
*target
= mips32_reg
->target
;
127 uint32_t value
= buf_get_u32(buf
, 0, 32);
129 if (target
->state
!= TARGET_HALTED
)
131 return ERROR_TARGET_NOT_HALTED
;
134 buf_set_u32(reg
->value
, 0, 32, value
);
141 int mips32_read_core_reg(struct target
*target
, int num
)
144 struct mips32_core_reg
*mips_core_reg
;
146 /* get pointers to arch-specific information */
147 struct mips32_common
*mips32
= target_to_mips32(target
);
149 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
150 return ERROR_INVALID_ARGUMENTS
;
152 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
153 reg_value
= mips32
->core_regs
[num
];
154 buf_set_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
155 mips32
->core_cache
->reg_list
[num
].valid
= 1;
156 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
161 int mips32_write_core_reg(struct target
*target
, int num
)
164 struct mips32_core_reg
*mips_core_reg
;
166 /* get pointers to arch-specific information */
167 struct mips32_common
*mips32
= target_to_mips32(target
);
169 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
170 return ERROR_INVALID_ARGUMENTS
;
172 reg_value
= buf_get_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32);
173 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
174 mips32
->core_regs
[num
] = reg_value
;
175 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", num
, reg_value
);
176 mips32
->core_cache
->reg_list
[num
].valid
= 1;
177 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
182 int mips32_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[], int *reg_list_size
)
184 /* get pointers to arch-specific information */
185 struct mips32_common
*mips32
= target_to_mips32(target
);
188 /* include floating point registers */
189 *reg_list_size
= MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
;
190 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
192 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
194 (*reg_list
)[i
] = &mips32
->core_cache
->reg_list
[i
];
197 /* add dummy floating points regs */
198 for (i
= MIPS32NUMCOREREGS
; i
< (MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
); i
++)
200 (*reg_list
)[i
] = &mips32_gdb_dummy_fp_reg
;
206 int mips32_save_context(struct target
*target
)
210 /* get pointers to arch-specific information */
211 struct mips32_common
*mips32
= target_to_mips32(target
);
212 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
214 /* read core registers */
215 mips32_pracc_read_regs(ejtag_info
, mips32
->core_regs
);
217 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
219 if (!mips32
->core_cache
->reg_list
[i
].valid
)
221 mips32
->read_core_reg(target
, i
);
228 int mips32_restore_context(struct target
*target
)
232 /* get pointers to arch-specific information */
233 struct mips32_common
*mips32
= target_to_mips32(target
);
234 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
236 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
238 if (mips32
->core_cache
->reg_list
[i
].dirty
)
240 mips32
->write_core_reg(target
, i
);
244 /* write core regs */
245 mips32_pracc_write_regs(ejtag_info
, mips32
->core_regs
);
250 int mips32_arch_state(struct target
*target
)
252 struct mips32_common
*mips32
= target_to_mips32(target
);
254 LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32
"",
255 mips_isa_strings
[mips32
->isa_mode
],
256 debug_reason_name(target
),
257 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
262 static const struct reg_arch_type mips32_reg_type
= {
263 .get
= mips32_get_core_reg
,
264 .set
= mips32_set_core_reg
,
267 struct reg_cache
*mips32_build_reg_cache(struct target
*target
)
269 /* get pointers to arch-specific information */
270 struct mips32_common
*mips32
= target_to_mips32(target
);
272 int num_regs
= MIPS32NUMCOREREGS
;
273 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
274 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
275 struct reg
*reg_list
= malloc(sizeof(struct reg
) * num_regs
);
276 struct mips32_core_reg
*arch_info
= malloc(sizeof(struct mips32_core_reg
) * num_regs
);
279 register_init_dummy(&mips32_gdb_dummy_fp_reg
);
281 /* Build the process context cache */
282 cache
->name
= "mips32 registers";
284 cache
->reg_list
= reg_list
;
285 cache
->num_regs
= num_regs
;
287 mips32
->core_cache
= cache
;
289 for (i
= 0; i
< num_regs
; i
++)
291 arch_info
[i
] = mips32_core_reg_list_arch_info
[i
];
292 arch_info
[i
].target
= target
;
293 arch_info
[i
].mips32_common
= mips32
;
294 reg_list
[i
].name
= mips32_core_reg_list
[i
];
295 reg_list
[i
].size
= 32;
296 reg_list
[i
].value
= calloc(1, 4);
297 reg_list
[i
].dirty
= 0;
298 reg_list
[i
].valid
= 0;
299 reg_list
[i
].type
= &mips32_reg_type
;
300 reg_list
[i
].arch_info
= &arch_info
[i
];
306 int mips32_init_arch_info(struct target
*target
, struct mips32_common
*mips32
, struct jtag_tap
*tap
)
308 target
->arch_info
= mips32
;
309 mips32
->common_magic
= MIPS32_COMMON_MAGIC
;
311 /* has breakpoint/watchpint unit been scanned */
312 mips32
->bp_scanned
= 0;
313 mips32
->data_break_list
= NULL
;
315 mips32
->ejtag_info
.tap
= tap
;
316 mips32
->read_core_reg
= mips32_read_core_reg
;
317 mips32
->write_core_reg
= mips32_write_core_reg
;
322 int mips32_run_algorithm(struct target
*target
, int num_mem_params
, struct mem_param
*mem_params
, int num_reg_params
, struct reg_param
*reg_params
, uint32_t entry_point
, uint32_t exit_point
, int timeout_ms
, void *arch_info
)
328 int mips32_examine(struct target
*target
)
330 struct mips32_common
*mips32
= target_to_mips32(target
);
332 if (!target_was_examined(target
))
334 target_set_examined(target
);
336 /* we will configure later */
337 mips32
->bp_scanned
= 0;
338 mips32
->num_inst_bpoints
= 0;
339 mips32
->num_data_bpoints
= 0;
340 mips32
->num_inst_bpoints_avail
= 0;
341 mips32
->num_data_bpoints_avail
= 0;
347 int mips32_configure_break_unit(struct target
*target
)
349 /* get pointers to arch-specific information */
350 struct mips32_common
*mips32
= target_to_mips32(target
);
352 uint32_t dcr
, bpinfo
;
355 if (mips32
->bp_scanned
)
358 /* get info about breakpoint support */
359 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
362 if (dcr
& EJTAG_DCR_IB
)
364 /* get number of inst breakpoints */
365 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &bpinfo
)) != ERROR_OK
)
368 mips32
->num_inst_bpoints
= (bpinfo
>> 24) & 0x0F;
369 mips32
->num_inst_bpoints_avail
= mips32
->num_inst_bpoints
;
370 mips32
->inst_break_list
= calloc(mips32
->num_inst_bpoints
, sizeof(struct mips32_comparator
));
371 for (i
= 0; i
< mips32
->num_inst_bpoints
; i
++)
373 mips32
->inst_break_list
[i
].reg_address
= EJTAG_IBA1
+ (0x100 * i
);
377 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
381 if (dcr
& EJTAG_DCR_DB
)
383 /* get number of data breakpoints */
384 if ((retval
= target_read_u32(target
, EJTAG_DBS
, &bpinfo
)) != ERROR_OK
)
387 mips32
->num_data_bpoints
= (bpinfo
>> 24) & 0x0F;
388 mips32
->num_data_bpoints_avail
= mips32
->num_data_bpoints
;
389 mips32
->data_break_list
= calloc(mips32
->num_data_bpoints
, sizeof(struct mips32_comparator
));
390 for (i
= 0; i
< mips32
->num_data_bpoints
; i
++)
392 mips32
->data_break_list
[i
].reg_address
= EJTAG_DBA1
+ (0x100 * i
);
396 if ((retval
= target_write_u32(target
, EJTAG_DBS
, 0)) != ERROR_OK
)
400 LOG_DEBUG("DCR 0x%" PRIx32
" numinst %i numdata %i", dcr
, mips32
->num_inst_bpoints
, mips32
->num_data_bpoints
);
402 mips32
->bp_scanned
= 1;
407 int mips32_enable_interrupts(struct target
*target
, int enable
)
413 /* read debug control register */
414 if ((retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
)) != ERROR_OK
)
419 if (!(dcr
& EJTAG_DCR_INTE
))
421 /* enable interrupts */
422 dcr
|= EJTAG_DCR_INTE
;
428 if (dcr
& EJTAG_DCR_INTE
)
430 /* disable interrupts */
431 dcr
&= ~EJTAG_DCR_INTE
;
438 if ((retval
= target_write_u32(target
, EJTAG_DCR
, dcr
)) != ERROR_OK
)
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