Code Review / openocd.git / blob
? search:


24cd7d954a973d2743da415c4e2f7b6ea09fb721
[openocd.git] / src / target / mips32.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "mips32.h"
30 #include "breakpoints.h"
31 #include "algorithm.h"
32 #include "register.h"
33
34 static char* mips32_core_reg_list[] =
35 {
36 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
37 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
38 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
39 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
40 "status", "lo", "hi", "badvaddr", "cause", "pc"
41 };
42
43 static const char *mips_isa_strings[] =
44 {
45 "MIPS32", "MIPS16e"
46 };
47
48 static struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
49 {
50 {0, NULL, NULL},
51 {1, NULL, NULL},
52 {2, NULL, NULL},
53 {3, NULL, NULL},
54 {4, NULL, NULL},
55 {5, NULL, NULL},
56 {6, NULL, NULL},
57 {7, NULL, NULL},
58 {8, NULL, NULL},
59 {9, NULL, NULL},
60 {10, NULL, NULL},
61 {11, NULL, NULL},
62 {12, NULL, NULL},
63 {13, NULL, NULL},
64 {14, NULL, NULL},
65 {15, NULL, NULL},
66 {16, NULL, NULL},
67 {17, NULL, NULL},
68 {18, NULL, NULL},
69 {19, NULL, NULL},
70 {20, NULL, NULL},
71 {21, NULL, NULL},
72 {22, NULL, NULL},
73 {23, NULL, NULL},
74 {24, NULL, NULL},
75 {25, NULL, NULL},
76 {26, NULL, NULL},
77 {27, NULL, NULL},
78 {28, NULL, NULL},
79 {29, NULL, NULL},
80 {30, NULL, NULL},
81 {31, NULL, NULL},
82
83 {32, NULL, NULL},
84 {33, NULL, NULL},
85 {34, NULL, NULL},
86 {35, NULL, NULL},
87 {36, NULL, NULL},
88 {37, NULL, NULL},
89 };
90
91 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
92 * we also add 18 unknown registers to handle gdb requests */
93
94 #define MIPS32NUMFPREGS 34 + 18
95
96 static uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
97
98 static struct reg mips32_gdb_dummy_fp_reg =
99 {
100 .name = "GDB dummy floating-point register",
101 .value = mips32_gdb_dummy_fp_value,
102 .dirty = 0,
103 .valid = 1,
104 .size = 32,
105 .arch_info = NULL,
106 };
107
108 static int mips32_get_core_reg(struct reg *reg)
109 {
110 int retval;
111 struct mips32_core_reg *mips32_reg = reg->arch_info;
112 struct target *target = mips32_reg->target;
113 struct mips32_common *mips32_target = target_to_mips32(target);
114
115 if (target->state != TARGET_HALTED)
116 {
117 return ERROR_TARGET_NOT_HALTED;
118 }
119
120 retval = mips32_target->read_core_reg(target, mips32_reg->num);
121
122 return retval;
123 }
124
125 static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
126 {
127 struct mips32_core_reg *mips32_reg = reg->arch_info;
128 struct target *target = mips32_reg->target;
129 uint32_t value = buf_get_u32(buf, 0, 32);
130
131 if (target->state != TARGET_HALTED)
132 {
133 return ERROR_TARGET_NOT_HALTED;
134 }
135
136 buf_set_u32(reg->value, 0, 32, value);
137 reg->dirty = 1;
138 reg->valid = 1;
139
140 return ERROR_OK;
141 }
142
143 static int mips32_read_core_reg(struct target *target, int num)
144 {
145 uint32_t reg_value;
146 struct mips32_core_reg *mips_core_reg;
147
148 /* get pointers to arch-specific information */
149 struct mips32_common *mips32 = target_to_mips32(target);
150
151 if ((num < 0) || (num >= MIPS32NUMCOREREGS))
152 return ERROR_INVALID_ARGUMENTS;
153
154 mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
155 reg_value = mips32->core_regs[num];
156 buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
157 mips32->core_cache->reg_list[num].valid = 1;
158 mips32->core_cache->reg_list[num].dirty = 0;
159
160 return ERROR_OK;
161 }
162
163 static int mips32_write_core_reg(struct target *target, int num)
164 {
165 uint32_t reg_value;
166 struct mips32_core_reg *mips_core_reg;
167
168 /* get pointers to arch-specific information */
169 struct mips32_common *mips32 = target_to_mips32(target);
170
171 if ((num < 0) || (num >= MIPS32NUMCOREREGS))
172 return ERROR_INVALID_ARGUMENTS;
173
174 reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
175 mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
176 mips32->core_regs[num] = reg_value;
177 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
178 mips32->core_cache->reg_list[num].valid = 1;
179 mips32->core_cache->reg_list[num].dirty = 0;
180
181 return ERROR_OK;
182 }
183
184 int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
185 {
186 /* get pointers to arch-specific information */
187 struct mips32_common *mips32 = target_to_mips32(target);
188 int i;
189
190 /* include floating point registers */
191 *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
192 *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
193
194 for (i = 0; i < MIPS32NUMCOREREGS; i++)
195 {
196 (*reg_list)[i] = &mips32->core_cache->reg_list[i];
197 }
198
199 /* add dummy floating points regs */
200 for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
201 {
202 (*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
203 }
204
205 return ERROR_OK;
206 }
207
208 int mips32_save_context(struct target *target)
209 {
210 int i;
211
212 /* get pointers to arch-specific information */
213 struct mips32_common *mips32 = target_to_mips32(target);
214 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
215
216 /* read core registers */
217 mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
218
219 for (i = 0; i < MIPS32NUMCOREREGS; i++)
220 {
221 if (!mips32->core_cache->reg_list[i].valid)
222 {
223 mips32->read_core_reg(target, i);
224 }
225 }
226
227 return ERROR_OK;
228 }
229
230 int mips32_restore_context(struct target *target)
231 {
232 int i;
233
234 /* get pointers to arch-specific information */
235 struct mips32_common *mips32 = target_to_mips32(target);
236 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
237
238 for (i = 0; i < MIPS32NUMCOREREGS; i++)
239 {
240 if (mips32->core_cache->reg_list[i].dirty)
241 {
242 mips32->write_core_reg(target, i);
243 }
244 }
245
246 /* write core regs */
247 mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
248
249 return ERROR_OK;
250 }
251
252 int mips32_arch_state(struct target *target)
253 {
254 struct mips32_common *mips32 = target_to_mips32(target);
255
256 LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
257 mips_isa_strings[mips32->isa_mode],
258 debug_reason_name(target),
259 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
260
261 return ERROR_OK;
262 }
263
264 static const struct reg_arch_type mips32_reg_type = {
265 .get = mips32_get_core_reg,
266 .set = mips32_set_core_reg,
267 };
268
269 struct reg_cache *mips32_build_reg_cache(struct target *target)
270 {
271 /* get pointers to arch-specific information */
272 struct mips32_common *mips32 = target_to_mips32(target);
273
274 int num_regs = MIPS32NUMCOREREGS;
275 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
276 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
277 struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
278 struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
279 int i;
280
281 register_init_dummy(&mips32_gdb_dummy_fp_reg);
282
283 /* Build the process context cache */
284 cache->name = "mips32 registers";
285 cache->next = NULL;
286 cache->reg_list = reg_list;
287 cache->num_regs = num_regs;
288 (*cache_p) = cache;
289 mips32->core_cache = cache;
290
291 for (i = 0; i < num_regs; i++)
292 {
293 arch_info[i] = mips32_core_reg_list_arch_info[i];
294 arch_info[i].target = target;
295 arch_info[i].mips32_common = mips32;
296 reg_list[i].name = mips32_core_reg_list[i];
297 reg_list[i].size = 32;
298 reg_list[i].value = calloc(1, 4);
299 reg_list[i].dirty = 0;
300 reg_list[i].valid = 0;
301 reg_list[i].type = &mips32_reg_type;
302 reg_list[i].arch_info = &arch_info[i];
303 }
304
305 return cache;
306 }
307
308 int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
309 {
310 target->arch_info = mips32;
311 mips32->common_magic = MIPS32_COMMON_MAGIC;
312
313 /* has breakpoint/watchpint unit been scanned */
314 mips32->bp_scanned = 0;
315 mips32->data_break_list = NULL;
316
317 mips32->ejtag_info.tap = tap;
318 mips32->read_core_reg = mips32_read_core_reg;
319 mips32->write_core_reg = mips32_write_core_reg;
320
321 return ERROR_OK;
322 }
323
324 /* run to exit point. return error if exit point was not reached. */
325 static int mips32_run_and_wait(struct target *target, uint32_t entry_point,
326 int timeout_ms, uint32_t exit_point, struct mips32_common *mips32)
327 {
328 uint32_t pc;
329 int retval;
330 /* This code relies on the target specific resume() and poll()->debug_entry()
331 * sequence to write register values to the processor and the read them back */
332 if ((retval = target_resume(target, 0, entry_point, 0, 1)) != ERROR_OK)
333 {
334 return retval;
335 }
336
337 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
338 /* If the target fails to halt due to the breakpoint, force a halt */
339 if (retval != ERROR_OK || target->state != TARGET_HALTED)
340 {
341 if ((retval = target_halt(target)) != ERROR_OK)
342 return retval;
343 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
344 {
345 return retval;
346 }
347 return ERROR_TARGET_TIMEOUT;
348 }
349
350 pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
351 if (exit_point && (pc != exit_point))
352 {
353 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
354 return ERROR_TARGET_TIMEOUT;
355 }
356
357 return ERROR_OK;
358 }
359
360 int mips32_run_algorithm(struct target *target, int num_mem_params,
361 struct mem_param *mem_params, int num_reg_params,
362 struct reg_param *reg_params, uint32_t entry_point,
363 uint32_t exit_point, int timeout_ms, void *arch_info)
364 {
365 struct mips32_common *mips32 = target_to_mips32(target);
366 struct mips32_algorithm *mips32_algorithm_info = arch_info;
367 enum mips32_isa_mode isa_mode = mips32->isa_mode;
368
369 uint32_t context[MIPS32NUMCOREREGS];
370 int i;
371 int retval = ERROR_OK;
372
373 LOG_DEBUG("Running algorithm");
374
375 /* NOTE: mips32_run_algorithm requires that each algorithm uses a software breakpoint
376 * at the exit point */
377
378 if (mips32->common_magic != MIPS32_COMMON_MAGIC)
379 {
380 LOG_ERROR("current target isn't a MIPS32 target");
381 return ERROR_TARGET_INVALID;
382 }
383
384 if (target->state != TARGET_HALTED)
385 {
386 LOG_WARNING("target not halted");
387 return ERROR_TARGET_NOT_HALTED;
388 }
389
390 /* refresh core register cache */
391 for (i = 0; i < MIPS32NUMCOREREGS; i++)
392 {
393 if (!mips32->core_cache->reg_list[i].valid)
394 mips32->read_core_reg(target, i);
395 context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
396 }
397
398 for (i = 0; i < num_mem_params; i++)
399 {
400 if ((retval = target_write_buffer(target, mem_params[i].address,
401 mem_params[i].size, mem_params[i].value)) != ERROR_OK)
402 {
403 return retval;
404 }
405 }
406
407 for (i = 0; i < num_reg_params; i++)
408 {
409 struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
410
411 if (!reg)
412 {
413 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
414 return ERROR_INVALID_ARGUMENTS;
415 }
416
417 if (reg->size != reg_params[i].size)
418 {
419 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
420 reg_params[i].reg_name);
421 return ERROR_INVALID_ARGUMENTS;
422 }
423
424 mips32_set_core_reg(reg, reg_params[i].value);
425 }
426
427 mips32->isa_mode = mips32_algorithm_info->isa_mode;
428
429 retval = mips32_run_and_wait(target, entry_point, timeout_ms, exit_point, mips32);
430
431 if (retval != ERROR_OK)
432 return retval;
433
434 for (i = 0; i < num_mem_params; i++)
435 {
436 if (mem_params[i].direction != PARAM_OUT)
437 {
438 if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size,
439 mem_params[i].value)) != ERROR_OK)
440 {
441 return retval;
442 }
443 }
444 }
445
446 for (i = 0; i < num_reg_params; i++)
447 {
448 if (reg_params[i].direction != PARAM_OUT)
449 {
450 struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
451 if (!reg)
452 {
453 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
454 return ERROR_INVALID_ARGUMENTS;
455 }
456
457 if (reg->size != reg_params[i].size)
458 {
459 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
460 reg_params[i].reg_name);
461 return ERROR_INVALID_ARGUMENTS;
462 }
463
464 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
465 }
466 }
467
468 /* restore everything we saved before */
469 for (i = 0; i < MIPS32NUMCOREREGS; i++)
470 {
471 uint32_t regvalue;
472 regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
473 if (regvalue != context[i])
474 {
475 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
476 mips32->core_cache->reg_list[i].name, context[i]);
477 buf_set_u32(mips32->core_cache->reg_list[i].value,
478 0, 32, context[i]);
479 mips32->core_cache->reg_list[i].valid = 1;
480 mips32->core_cache->reg_list[i].dirty = 1;
481 }
482 }
483
484 mips32->isa_mode = isa_mode;
485
486 return ERROR_OK;
487 }
488
489 int mips32_examine(struct target *target)
490 {
491 struct mips32_common *mips32 = target_to_mips32(target);
492
493 if (!target_was_examined(target))
494 {
495 target_set_examined(target);
496
497 /* we will configure later */
498 mips32->bp_scanned = 0;
499 mips32->num_inst_bpoints = 0;
500 mips32->num_data_bpoints = 0;
501 mips32->num_inst_bpoints_avail = 0;
502 mips32->num_data_bpoints_avail = 0;
503 }
504
505 return ERROR_OK;
506 }
507
508 int mips32_configure_break_unit(struct target *target)
509 {
510 /* get pointers to arch-specific information */
511 struct mips32_common *mips32 = target_to_mips32(target);
512 int retval;
513 uint32_t dcr, bpinfo;
514 int i;
515
516 if (mips32->bp_scanned)
517 return ERROR_OK;
518
519 /* get info about breakpoint support */
520 if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
521 return retval;
522
523 if (dcr & EJTAG_DCR_IB)
524 {
525 /* get number of inst breakpoints */
526 if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
527 return retval;
528
529 mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
530 mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
531 mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator));
532 for (i = 0; i < mips32->num_inst_bpoints; i++)
533 {
534 mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
535 }
536
537 /* clear IBIS reg */
538 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
539 return retval;
540 }
541
542 if (dcr & EJTAG_DCR_DB)
543 {
544 /* get number of data breakpoints */
545 if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
546 return retval;
547
548 mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
549 mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
550 mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator));
551 for (i = 0; i < mips32->num_data_bpoints; i++)
552 {
553 mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
554 }
555
556 /* clear DBIS reg */
557 if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
558 return retval;
559 }
560
561 LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
562 mips32->num_data_bpoints);
563
564 mips32->bp_scanned = 1;
565
566 return ERROR_OK;
567 }
568
569 int mips32_enable_interrupts(struct target *target, int enable)
570 {
571 int retval;
572 int update = 0;
573 uint32_t dcr;
574
575 /* read debug control register */
576 if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
577 return retval;
578
579 if (enable)
580 {
581 if (!(dcr & EJTAG_DCR_INTE))
582 {
583 /* enable interrupts */
584 dcr |= EJTAG_DCR_INTE;
585 update = 1;
586 }
587 }
588 else
589 {
590 if (dcr & EJTAG_DCR_INTE)
591 {
592 /* disable interrupts */
593 dcr &= ~EJTAG_DCR_INTE;
594 update = 1;
595 }
596 }
597
598 if (update)
599 {
600 if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
601 return retval;
602 }
603
604 return ERROR_OK;
605 }
606
607 int mips32_checksum_memory(struct target *target, uint32_t address,
608 uint32_t count, uint32_t* checksum)
609 {
610 struct working_area *crc_algorithm;
611 struct reg_param reg_params[2];
612 struct mips32_algorithm mips32_info;
613 int retval;
614 uint32_t i;
615
616 static const uint32_t mips_crc_code[] =
617 {
618 0x248C0000, /* addiu $t4, $a0, 0 */
619 0x24AA0000, /* addiu $t2, $a1, 0 */
620 0x2404FFFF, /* addiu $a0, $zero, 0xffffffff */
621 0x10000010, /* beq $zero, $zero, ncomp */
622 0x240B0000, /* addiu $t3, $zero, 0 */
623 /* nbyte: */
624 0x81850000, /* lb $a1, ($t4) */
625 0x218C0001, /* addi $t4, $t4, 1 */
626 0x00052E00, /* sll $a1, $a1, 24 */
627 0x3C0204C1, /* lui $v0, 0x04c1 */
628 0x00852026, /* xor $a0, $a0, $a1 */
629 0x34471DB7, /* ori $a3, $v0, 0x1db7 */
630 0x00003021, /* addu $a2, $zero, $zero */
631 /* loop: */
632 0x00044040, /* sll $t0, $a0, 1 */
633 0x24C60001, /* addiu $a2, $a2, 1 */
634 0x28840000, /* slti $a0, $a0, 0 */
635 0x01074826, /* xor $t1, $t0, $a3 */
636 0x0124400B, /* movn $t0, $t1, $a0 */
637 0x28C30008, /* slti $v1, $a2, 8 */
638 0x1460FFF9, /* bne $v1, $zero, loop */
639 0x01002021, /* addu $a0, $t0, $zero */
640 /* ncomp: */
641 0x154BFFF0, /* bne $t2, $t3, nbyte */
642 0x256B0001, /* addiu $t3, $t3, 1 */
643 0x7000003F, /* sdbbp */
644 };
645
646 /* make sure we have a working area */
647 if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK)
648 {
649 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
650 }
651
652 /* convert flash writing code into a buffer in target endianness */
653 for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++)
654 target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), mips_crc_code[i]);
655
656 mips32_info.common_magic = MIPS32_COMMON_MAGIC;
657 mips32_info.isa_mode = MIPS32_ISA_MIPS32;
658
659 init_reg_param(&reg_params[0], "a0", 32, PARAM_IN_OUT);
660 buf_set_u32(reg_params[0].value, 0, 32, address);
661
662 init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
663 buf_set_u32(reg_params[1].value, 0, 32, count);
664
665 int timeout = 20000 * (1 + (count / (1024 * 1024)));
666
667 if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
668 crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), timeout,
669 &mips32_info)) != ERROR_OK)
670 {
671 destroy_reg_param(&reg_params[0]);
672 destroy_reg_param(&reg_params[1]);
673 target_free_working_area(target, crc_algorithm);
674 return 0;
675 }
676
677 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
678
679 destroy_reg_param(&reg_params[0]);
680 destroy_reg_param(&reg_params[1]);
681
682 target_free_working_area(target, crc_algorithm);
683
684 return ERROR_OK;
685 }
686
687 /** Checks whether a memory region is zeroed. */
688 int mips32_blank_check_memory(struct target *target,
689 uint32_t address, uint32_t count, uint32_t* blank)
690 {
691 struct working_area *erase_check_algorithm;
692 struct reg_param reg_params[3];
693 struct mips32_algorithm mips32_info;
694 int retval;
695 uint32_t i;
696
697 static const uint32_t erase_check_code[] =
698 {
699 /* nbyte: */
700 0x80880000, /* lb $t0, ($a0) */
701 0x00C83024, /* and $a2, $a2, $t0 */
702 0x24A5FFFF, /* addiu $a1, $a1, -1 */
703 0x14A0FFFC, /* bne $a1, $zero, nbyte */
704 0x24840001, /* addiu $a0, $a0, 1 */
705 0x7000003F /* sdbbp */
706 };
707
708 /* make sure we have a working area */
709 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
710 {
711 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
712 }
713
714 /* convert flash writing code into a buffer in target endianness */
715 for (i = 0; i < ARRAY_SIZE(erase_check_code); i++)
716 {
717 target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t),
718 erase_check_code[i]);
719 }
720
721 mips32_info.common_magic = MIPS32_COMMON_MAGIC;
722 mips32_info.isa_mode = MIPS32_ISA_MIPS32;
723
724 init_reg_param(&reg_params[0], "a0", 32, PARAM_OUT);
725 buf_set_u32(reg_params[0].value, 0, 32, address);
726
727 init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
728 buf_set_u32(reg_params[1].value, 0, 32, count);
729
730 init_reg_param(&reg_params[2], "a2", 32, PARAM_IN_OUT);
731 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
732
733 if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
734 erase_check_algorithm->address,
735 erase_check_algorithm->address + (sizeof(erase_check_code)-2),
736 10000, &mips32_info)) != ERROR_OK)
737 {
738 destroy_reg_param(&reg_params[0]);
739 destroy_reg_param(&reg_params[1]);
740 destroy_reg_param(&reg_params[2]);
741 target_free_working_area(target, erase_check_algorithm);
742 return 0;
743 }
744
745 *blank = buf_get_u32(reg_params[2].value, 0, 32);
746
747 destroy_reg_param(&reg_params[0]);
748 destroy_reg_param(&reg_params[1]);
749 destroy_reg_param(&reg_params[2]);
750
751 target_free_working_area(target, erase_check_algorithm);
752
753 return ERROR_OK;
754 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)