src/target/lakemont.c

   1 /*
   2  * Copyright(c) 2013-2016 Intel Corporation.
   3  *
   4  * Adrian Burns (adrian.burns@intel.com)
   5  * Thomas Faust (thomas.faust@intel.com)
   6  * Ivan De Cesaris (ivan.de.cesaris@intel.com)
   7  * Julien Carreno (julien.carreno@intel.com)
   8  * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
   9  * Jessica Gomez (jessica.gomez.hernandez@intel.com)
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  24  *
  25  * Contact Information:
  26  * Intel Corporation
  27  */
  28
  29 /*
  30  * @file
  31  * This implements the probemode operations for Lakemont 1 (LMT1).
  32  */
  33
  34 #ifdef HAVE_CONFIG_H
  35 #include "config.h"
  36 #endif
  37
  38 #include <helper/log.h>
  39
  40 #include "target.h"
  41 #include "target_type.h"
  42 #include "lakemont.h"
  43 #include "register.h"
  44 #include "breakpoints.h"
  45 #include "x86_32_common.h"
  46
  47 static int irscan(struct target *t, uint8_t *out,
  48                         uint8_t *in, uint8_t ir_len);
  49 static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len);
  50 static int save_context(struct target *target);
  51 static int restore_context(struct target *target);
  52 static uint32_t get_tapstatus(struct target *t);
  53 static int enter_probemode(struct target *t);
  54 static int exit_probemode(struct target *t);
  55 static int halt_prep(struct target *t);
  56 static int do_halt(struct target *t);
  57 static int do_resume(struct target *t);
  58 static int read_all_core_hw_regs(struct target *t);
  59 static int write_all_core_hw_regs(struct target *t);
  60 static int read_hw_reg(struct target *t,
  61                         int reg, uint32_t *regval, uint8_t cache);
  62 static int write_hw_reg(struct target *t,
  63                         int reg, uint32_t regval, uint8_t cache);
  64 static struct reg_cache *lakemont_build_reg_cache
  65                         (struct target *target);
  66 static int submit_reg_pir(struct target *t, int num);
  67 static int submit_instruction_pir(struct target *t, int num);
  68 static int submit_pir(struct target *t, uint64_t op);
  69 static int lakemont_get_core_reg(struct reg *reg);
  70 static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf);
  71
  72 static struct scan_blk scan;
  73
  74 /* registers and opcodes for register access, pm_idx is used to identify the
  75  * registers that are modified for lakemont probemode specific operations
  76  */
  77 static const struct {
  78         uint8_t id;
  79         const char *name;
  80         uint64_t op;
  81         uint8_t pm_idx;
  82         unsigned bits;
  83         enum reg_type type;
  84         const char *group;
  85         const char *feature;
  86 } regs[] = {
  87         /* general purpose registers */
  88         { EAX, "eax", 0x000000D01D660000, 0, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
  89         { ECX, "ecx", 0x000000501D660000, 1, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
  90         { EDX, "edx", 0x000000901D660000, 2, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
  91         { EBX, "ebx", 0x000000101D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
  92         { ESP, "esp", 0x000000E01D660000, NOT_PMREG, 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.i386.core" },
  93         { EBP, "ebp", 0x000000601D660000, NOT_PMREG, 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.i386.core" },
  94         { ESI, "esi", 0x000000A01D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
  95         { EDI, "edi", 0x000000201D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
  96
  97         /* instruction pointer & flags */
  98         { EIP, "eip", 0x000000C01D660000, 3, 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.i386.core" },
  99         { EFLAGS, "eflags", 0x000000401D660000, 4, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 100
 101         /* segment registers */
 102         { CS, "cs", 0x000000281D660000, 5, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 103         { SS, "ss", 0x000000C81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 104         { DS, "ds", 0x000000481D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 105         { ES, "es", 0x000000A81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 106         { FS, "fs", 0x000000881D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 107         { GS, "gs", 0x000000081D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 108
 109         /* floating point unit registers - not accessible via JTAG - here to satisfy GDB */
 110         { ST0, "st0", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 111         { ST1, "st1", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 112         { ST2, "st2", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 113         { ST3, "st3", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 114         { ST4, "st4", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 115         { ST5, "st5", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 116         { ST6, "st6", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 117         { ST7, "st7", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 118         { FCTRL, "fctrl", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 119         { FSTAT, "fstat", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 120         { FTAG, "ftag", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 121         { FISEG, "fiseg", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 122         { FIOFF, "fioff", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 123         { FOSEG, "foseg", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 124         { FOOFF, "fooff", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 125         { FOP, "fop", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
 126
 127         /* control registers */
 128         { CR0, "cr0", 0x000000001D660000, 6, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 129         { CR2, "cr2", 0x000000BC1D660000, 7, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 130         { CR3, "cr3", 0x000000801D660000, 8, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 131         { CR4, "cr4", 0x0000002C1D660000, 9, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 132
 133         /* debug registers */
 134         { DR0, "dr0", 0x0000007C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 135         { DR1, "dr1", 0x000000FC1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 136         { DR2, "dr2", 0x000000021D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 137         { DR3, "dr3", 0x000000821D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 138         { DR6, "dr6", 0x000000301D660000, 10, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 139         { DR7, "dr7", 0x000000B01D660000, 11, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 140
 141         /* descriptor tables */
 142         { IDTB, "idtbase", 0x000000581D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 143         { IDTL, "idtlimit", 0x000000D81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 144         { IDTAR, "idtar", 0x000000981D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 145         { GDTB, "gdtbase", 0x000000B81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 146         { GDTL, "gdtlimit", 0x000000781D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 147         { GDTAR, "gdtar", 0x000000381D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 148         { TR, "tr", 0x000000701D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 149         { LDTR, "ldtr", 0x000000F01D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 150         { LDTB, "ldbase", 0x000000041D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 151         { LDTL, "ldlimit", 0x000000841D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 152         { LDTAR, "ldtar", 0x000000F81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 153
 154         /* segment registers */
 155         { CSB, "csbase", 0x000000F41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 156         { CSL, "cslimit", 0x0000000C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 157         { CSAR, "csar", 0x000000741D660000, 12, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 158         { DSB, "dsbase", 0x000000941D660000, 13, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 159         { DSL, "dslimit", 0x000000541D660000, 14, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 160         { DSAR, "dsar", 0x000000141D660000, 15, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 161         { ESB, "esbase", 0x0000004C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 162         { ESL, "eslimit", 0x000000CC1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 163         { ESAR, "esar", 0x0000008C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 164         { FSB, "fsbase", 0x000000641D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 165         { FSL, "fslimit", 0x000000E41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 166         { FSAR, "fsar", 0x000000A41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 167         { GSB, "gsbase", 0x000000C41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 168         { GSL, "gslimit", 0x000000241D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 169         { GSAR, "gsar", 0x000000441D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 170         { SSB, "ssbase", 0x000000341D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 171         { SSL, "sslimit", 0x000000B41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 172         { SSAR, "ssar", 0x000000D41D660000, 16, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 173         { TSSB, "tssbase", 0x000000E81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 174         { TSSL, "tsslimit", 0x000000181D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 175         { TSSAR, "tssar", 0x000000681D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 176         /* probemode control register */
 177         { PMCR, "pmcr", 0x000000421D660000, 17, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
 178 };
 179
 180 static const struct {
 181         uint8_t id;
 182         const char *name;
 183         uint64_t op;
 184 } instructions[] = {
 185         /* memory read/write */
 186         { MEMRDB32, "MEMRDB32", 0x0909090909090851 },
 187         { MEMRDB16, "MEMRDB16", 0x09090909090851E6 },
 188         { MEMRDH32, "MEMRDH32", 0x090909090908D166 },
 189         { MEMRDH16, "MEMRDH16", 0x090909090908D1E6 },
 190         { MEMRDW32, "MEMRDW32", 0x09090909090908D1 },
 191         { MEMRDW16, "MEMRDW16", 0x0909090908D1E666 },
 192         { MEMWRB32, "MEMWRB32", 0x0909090909090811 },
 193         { MEMWRB16, "MEMWRB16", 0x09090909090811E6 },
 194         { MEMWRH32, "MEMWRH32", 0x0909090909089166 },
 195         { MEMWRH16, "MEMWRH16", 0x09090909090891E6 },
 196         { MEMWRW32, "MEMWRW32", 0x0909090909090891 },
 197         { MEMWRW16, "MEMWRW16", 0x090909090891E666 },
 198         /* IO read/write */
 199         { IORDB32, "IORDB32", 0x0909090909090937 },
 200         { IORDB16, "IORDB16", 0x09090909090937E6 },
 201         { IORDH32, "IORDH32", 0x090909090909B766 },
 202         { IORDH16, "IORDH16", 0x090909090909B7E6 },
 203         { IORDW32, "IORDW32", 0x09090909090909B7 },
 204         { IORDW16, "IORDW16", 0x0909090909B7E666 },
 205         { IOWRB32, "IOWRB32", 0x0909090909090977 },
 206         { IOWRB16, "IOWRB16", 0x09090909090977E6 },
 207         { IOWRH32, "IOWRH32", 0x090909090909F766 },
 208         { IOWRH16, "IOWRH16", 0x090909090909F7E6 },
 209         { IOWRW32, "IOWRW32", 0x09090909090909F7 },
 210         { IOWRW16, "IOWRW16", 0x0909090909F7E666 },
 211         /* lakemont1 core shadow ram access opcodes */
 212         { SRAMACCESS, "SRAMACCESS", 0x0000000E9D660000 },
 213         { SRAM2PDR, "SRAM2PDR", 0x4CF0000000000000 },
 214         { PDR2SRAM, "PDR2SRAM", 0x0CF0000000000000 },
 215         { WBINVD, "WBINVD", 0x09090909090990F0 },
 216 };
 217
 218 bool check_not_halted(const struct target *t)
 219 {
 220         bool halted = t->state == TARGET_HALTED;
 221         if (!halted)
 222                 LOG_ERROR("target running, halt it first");
 223         return !halted;
 224 }
 225
 226 static int irscan(struct target *t, uint8_t *out,
 227                         uint8_t *in, uint8_t ir_len)
 228 {
 229         int retval = ERROR_OK;
 230         struct x86_32_common *x86_32 = target_to_x86_32(t);
 231         if (NULL == t->tap) {
 232                 retval = ERROR_FAIL;
 233                 LOG_ERROR("%s invalid target tap", __func__);
 234                 return retval;
 235         }
 236         if (ir_len != t->tap->ir_length) {
 237                 retval = ERROR_FAIL;
 238                 if (t->tap->enabled)
 239                         LOG_ERROR("%s tap enabled but tap irlen=%d",
 240                                         __func__, t->tap->ir_length);
 241                 else
 242                         LOG_ERROR("%s tap not enabled and irlen=%d",
 243                                         __func__, t->tap->ir_length);
 244                 return retval;
 245         }
 246         struct scan_field *fields = &scan.field;
 247         fields->num_bits = ir_len;
 248         fields->out_value = out;
 249         fields->in_value = in;
 250         jtag_add_ir_scan(x86_32->curr_tap, fields, TAP_IDLE);
 251         if (x86_32->flush) {
 252                 retval = jtag_execute_queue();
 253                 if (retval != ERROR_OK)
 254                         LOG_ERROR("%s failed to execute queue", __func__);
 255         }
 256         return retval;
 257 }
 258
 259 static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len)
 260 {
 261         int retval = ERROR_OK;
 262         uint64_t data = 0;
 263         struct x86_32_common *x86_32 = target_to_x86_32(t);
 264         if (NULL == t->tap) {
 265                 retval = ERROR_FAIL;
 266                 LOG_ERROR("%s invalid target tap", __func__);
 267                 return retval;
 268         }
 269         if (len > MAX_SCAN_SIZE || 0 == len) {
 270                 retval = ERROR_FAIL;
 271                 LOG_ERROR("%s data len is %d bits, max is %d bits",
 272                                 __func__, len, MAX_SCAN_SIZE);
 273                 return retval;
 274         }
 275         struct scan_field *fields = &scan.field;
 276         fields->out_value = out;
 277         fields->in_value = in;
 278         fields->num_bits = len;
 279         jtag_add_dr_scan(x86_32->curr_tap, 1, fields, TAP_IDLE);
 280         if (x86_32->flush) {
 281                 retval = jtag_execute_queue();
 282                 if (retval != ERROR_OK) {
 283                         LOG_ERROR("%s drscan failed to execute queue", __func__);
 284                         return retval;
 285                 }
 286         }
 287         if (in != NULL) {
 288                 if (len >= 8) {
 289                         for (int n = (len / 8) - 1 ; n >= 0; n--)
 290                                 data = (data << 8) + *(in+n);
 291                 } else
 292                         LOG_DEBUG("dr in 0x%02" PRIx8, *in);
 293         } else {
 294                 LOG_ERROR("%s no drscan data", __func__);
 295                 retval = ERROR_FAIL;
 296         }
 297         return retval;
 298 }
 299
 300 static int save_context(struct target *t)
 301 {
 302         int err;
 303         /* read core registers from lakemont sram */
 304         err = read_all_core_hw_regs(t);
 305         if (err != ERROR_OK) {
 306                 LOG_ERROR("%s error reading regs", __func__);
 307                 return err;
 308         }
 309         return ERROR_OK;
 310 }
 311
 312 static int restore_context(struct target *t)
 313 {
 314         int err = ERROR_OK;
 315         uint32_t i;
 316         struct x86_32_common *x86_32 = target_to_x86_32(t);
 317
 318         /* write core regs into the core PM SRAM from the reg_cache */
 319         err = write_all_core_hw_regs(t);
 320         if (err != ERROR_OK) {
 321                 LOG_ERROR("%s error writing regs", __func__);
 322                 return err;
 323         }
 324
 325         for (i = 0; i < (x86_32->cache->num_regs); i++) {
 326                 x86_32->cache->reg_list[i].dirty = 0;
 327                 x86_32->cache->reg_list[i].valid = 0;
 328         }
 329         return err;
 330 }
 331
 332 /*
 333  * we keep reg_cache in sync with hardware at halt/resume time, we avoid
 334  * writing to real hardware here bacause pm_regs reflects the hardware
 335  * while we are halted then reg_cache syncs with hw on resume
 336  * TODO - in order for "reg eip force" to work it assume get/set reads
 337  * and writes from hardware, may be other reasons also because generally
 338  * other openocd targets read/write from hardware in get/set - watch this!
 339  */
 340 static int lakemont_get_core_reg(struct reg *reg)
 341 {
 342         int retval = ERROR_OK;
 343         struct lakemont_core_reg *lakemont_reg = reg->arch_info;
 344         struct target *t = lakemont_reg->target;
 345         if (check_not_halted(t))
 346                 return ERROR_TARGET_NOT_HALTED;
 347         LOG_DEBUG("reg=%s, value=0x%08" PRIx32, reg->name,
 348                         buf_get_u32(reg->value, 0, 32));
 349         return retval;
 350 }
 351
 352 static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf)
 353 {
 354         struct lakemont_core_reg *lakemont_reg = reg->arch_info;
 355         struct target *t = lakemont_reg->target;
 356         uint32_t value = buf_get_u32(buf, 0, 32);
 357         LOG_DEBUG("reg=%s, newval=0x%08" PRIx32, reg->name, value);
 358         if (check_not_halted(t))
 359                 return ERROR_TARGET_NOT_HALTED;
 360         buf_set_u32(reg->value, 0, 32, value);
 361         reg->dirty = 1;
 362         reg->valid = 1;
 363         return ERROR_OK;
 364 }
 365
 366 static const struct reg_arch_type lakemont_reg_type = {
 367         /* these get called if reg_cache doesnt have a "valid" value
 368          * of an individual reg eg "reg eip" but not for "reg" block
 369          */
 370         .get = lakemont_get_core_reg,
 371         .set = lakemont_set_core_reg,
 372 };
 373
 374 struct reg_cache *lakemont_build_reg_cache(struct target *t)
 375 {
 376         struct x86_32_common *x86_32 = target_to_x86_32(t);
 377         int num_regs = ARRAY_SIZE(regs);
 378         struct reg_cache **cache_p = register_get_last_cache_p(&t->reg_cache);
 379         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 380         struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
 381         struct lakemont_core_reg *arch_info = malloc(sizeof(struct lakemont_core_reg) * num_regs);
 382         struct reg_feature *feature;
 383         int i;
 384
 385         if (cache == NULL || reg_list == NULL || arch_info == NULL) {
 386                 free(cache);
 387                 free(reg_list);
 388                 free(arch_info);
 389                 LOG_ERROR("%s out of memory", __func__);
 390                 return NULL;
 391         }
 392
 393         /* Build the process context cache */
 394         cache->name = "lakemont registers";
 395         cache->next = NULL;
 396         cache->reg_list = reg_list;
 397         cache->num_regs = num_regs;
 398         (*cache_p) = cache;
 399         x86_32->cache = cache;
 400
 401         for (i = 0; i < num_regs; i++) {
 402                 arch_info[i].target = t;
 403                 arch_info[i].x86_32_common = x86_32;
 404                 arch_info[i].op = regs[i].op;
 405                 arch_info[i].pm_idx = regs[i].pm_idx;
 406                 reg_list[i].name = regs[i].name;
 407                 reg_list[i].size = 32;
 408                 reg_list[i].value = calloc(1, 4);
 409                 reg_list[i].dirty = 0;
 410                 reg_list[i].valid = 0;
 411                 reg_list[i].type = &lakemont_reg_type;
 412                 reg_list[i].arch_info = &arch_info[i];
 413
 414                 reg_list[i].group = regs[i].group;
 415                 reg_list[i].number = i;
 416                 reg_list[i].exist = true;
 417                 reg_list[i].caller_save = true; /* gdb defaults to true */
 418
 419                 feature = calloc(1, sizeof(struct reg_feature));
 420                 if (feature) {
 421                         feature->name = regs[i].feature;
 422                         reg_list[i].feature = feature;
 423                 } else
 424                         LOG_ERROR("%s unable to allocate feature list", __func__);
 425
 426                 reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
 427                 if (reg_list[i].reg_data_type)
 428                         reg_list[i].reg_data_type->type = regs[i].type;
 429                 else
 430                         LOG_ERROR("%s unable to allocate reg type list", __func__);
 431         }
 432         return cache;
 433 }
 434
 435 static uint32_t get_tapstatus(struct target *t)
 436 {
 437         scan.out[0] = TAPSTATUS;
 438         if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
 439                 return 0;
 440         if (drscan(t, NULL, scan.out, TS_SIZE) != ERROR_OK)
 441                 return 0;
 442         return buf_get_u32(scan.out, 0, 32);
 443 }
 444
 445 static int enter_probemode(struct target *t)
 446 {
 447         uint32_t tapstatus = 0;
 448         tapstatus = get_tapstatus(t);
 449         LOG_DEBUG("TS before PM enter = 0x%08" PRIx32, tapstatus);
 450         if (tapstatus & TS_PM_BIT) {
 451                 LOG_DEBUG("core already in probemode");
 452                 return ERROR_OK;
 453         }
 454         scan.out[0] = PROBEMODE;
 455         if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
 456                 return ERROR_FAIL;
 457         scan.out[0] = 1;
 458         if (drscan(t, scan.out, scan.in, 1) != ERROR_OK)
 459                 return ERROR_FAIL;
 460         tapstatus = get_tapstatus(t);
 461         LOG_DEBUG("TS after PM enter = 0x%08" PRIx32, tapstatus);
 462         if ((tapstatus & TS_PM_BIT) && (!(tapstatus & TS_EN_PM_BIT)))
 463                 return ERROR_OK;
 464         else {
 465                 LOG_ERROR("%s PM enter error, tapstatus = 0x%08" PRIx32
 466                                 , __func__, tapstatus);
 467                 return ERROR_FAIL;
 468         }
 469 }
 470
 471 static int exit_probemode(struct target *t)
 472 {
 473         uint32_t tapstatus = get_tapstatus(t);
 474         LOG_DEBUG("TS before PM exit = 0x%08" PRIx32, tapstatus);
 475
 476         if (!(tapstatus & TS_PM_BIT)) {
 477                 LOG_USER("core not in PM");
 478                 return ERROR_OK;
 479         }
 480         scan.out[0] = PROBEMODE;
 481         if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
 482                 return ERROR_FAIL;
 483         scan.out[0] = 0;
 484         if (drscan(t, scan.out, scan.in, 1) != ERROR_OK)
 485                 return ERROR_FAIL;
 486         return ERROR_OK;
 487 }
 488
 489 /* do whats needed to properly enter probemode for debug on lakemont */
 490 static int halt_prep(struct target *t)
 491 {
 492         struct x86_32_common *x86_32 = target_to_x86_32(t);
 493         if (write_hw_reg(t, DSB, PM_DSB, 0) != ERROR_OK)
 494                 return ERROR_FAIL;
 495         LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSB].name, PM_DSB);
 496         if (write_hw_reg(t, DSL, PM_DSL, 0) != ERROR_OK)
 497                 return ERROR_FAIL;
 498         LOG_DEBUG("write %s 0x%08" PRIx32, regs[DSL].name, PM_DSL);
 499         if (write_hw_reg(t, DSAR, PM_DSAR, 0) != ERROR_OK)
 500                 return ERROR_FAIL;
 501         LOG_DEBUG("write DSAR 0x%08" PRIx32, PM_DSAR);
 502         if (write_hw_reg(t, CSB, PM_DSB, 0) != ERROR_OK)
 503                 return ERROR_FAIL;
 504         LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSB].name, PM_DSB);
 505         if (write_hw_reg(t, CSL, PM_DSL, 0) != ERROR_OK)
 506                 return ERROR_FAIL;
 507         LOG_DEBUG("write %s 0x%08" PRIx32, regs[CSL].name, PM_DSL);
 508         if (write_hw_reg(t, DR7, PM_DR7, 0) != ERROR_OK)
 509                 return ERROR_FAIL;
 510         LOG_DEBUG("write DR7 0x%08" PRIx32, PM_DR7);
 511
 512         uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
 513         uint32_t csar = buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32);
 514         uint32_t ssar = buf_get_u32(x86_32->cache->reg_list[SSAR].value, 0, 32);
 515         uint32_t cr0 = buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32);
 516
 517         /* clear VM86 and IF bits if they are set */
 518         LOG_DEBUG("EFLAGS = 0x%08" PRIx32 ", VM86 = %d, IF = %d", eflags,
 519                         eflags & EFLAGS_VM86 ? 1 : 0,
 520                         eflags & EFLAGS_IF ? 1 : 0);
 521         if ((eflags & EFLAGS_VM86) || (eflags & EFLAGS_IF)) {
 522                 x86_32->pm_regs[I(EFLAGS)] = eflags & ~(EFLAGS_VM86 | EFLAGS_IF);
 523                 if (write_hw_reg(t, EFLAGS, x86_32->pm_regs[I(EFLAGS)], 0) != ERROR_OK)
 524                         return ERROR_FAIL;
 525                 LOG_DEBUG("EFLAGS now = 0x%08" PRIx32 ", VM86 = %d, IF = %d",
 526                                 x86_32->pm_regs[I(EFLAGS)],
 527                                 x86_32->pm_regs[I(EFLAGS)] & EFLAGS_VM86 ? 1 : 0,
 528                                 x86_32->pm_regs[I(EFLAGS)] & EFLAGS_IF ? 1 : 0);
 529         }
 530
 531         /* set CPL to 0 for memory access */
 532         if (csar & CSAR_DPL) {
 533                 x86_32->pm_regs[I(CSAR)] = csar & ~CSAR_DPL;
 534                 if (write_hw_reg(t, CSAR, x86_32->pm_regs[I(CSAR)], 0) != ERROR_OK)
 535                         return ERROR_FAIL;
 536                 LOG_DEBUG("write CSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(CSAR)]);
 537         }
 538         if (ssar & SSAR_DPL) {
 539                 x86_32->pm_regs[I(SSAR)] = ssar & ~SSAR_DPL;
 540                 if (write_hw_reg(t, SSAR, x86_32->pm_regs[I(SSAR)], 0) != ERROR_OK)
 541                         return ERROR_FAIL;
 542                 LOG_DEBUG("write SSAR_CPL to 0 0x%08" PRIx32, x86_32->pm_regs[I(SSAR)]);
 543         }
 544
 545         /* if cache's are enabled, disable and flush, depending on the core version */
 546         if (!(x86_32->core_type == LMT3_5) && !(cr0 & CR0_CD)) {
 547                 LOG_DEBUG("caching enabled CR0 = 0x%08" PRIx32, cr0);
 548                 if (cr0 & CR0_PG) {
 549                         x86_32->pm_regs[I(CR0)] = cr0 & ~CR0_PG;
 550                         if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
 551                                 return ERROR_FAIL;
 552                         LOG_DEBUG("cleared paging CR0_PG = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
 553                         /* submit wbinvd to flush cache */
 554                         if (submit_reg_pir(t, WBINVD) != ERROR_OK)
 555                                 return ERROR_FAIL;
 556                         x86_32->pm_regs[I(CR0)] =
 557                                 x86_32->pm_regs[I(CR0)] | (CR0_CD | CR0_NW | CR0_PG);
 558                         if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
 559                                 return ERROR_FAIL;
 560                         LOG_DEBUG("set CD, NW and PG, CR0 = 0x%08" PRIx32, x86_32->pm_regs[I(CR0)]);
 561                 }
 562         }
 563         return ERROR_OK;
 564 }
 565
 566 static int do_halt(struct target *t)
 567 {
 568         /* needs proper handling later if doing a halt errors out */
 569         t->state = TARGET_DEBUG_RUNNING;
 570         if (enter_probemode(t) != ERROR_OK)
 571                 return ERROR_FAIL;
 572
 573         return lakemont_update_after_probemode_entry(t);
 574 }
 575
 576 /* we need to expose the update to be able to complete the reset at SoC level */
 577 int lakemont_update_after_probemode_entry(struct target *t)
 578 {
 579         if (save_context(t) != ERROR_OK)
 580                 return ERROR_FAIL;
 581         if (halt_prep(t) != ERROR_OK)
 582                 return ERROR_FAIL;
 583         t->state = TARGET_HALTED;
 584
 585         return target_call_event_callbacks(t, TARGET_EVENT_HALTED);
 586 }
 587
 588 static int do_resume(struct target *t)
 589 {
 590         /* needs proper handling later */
 591         t->state = TARGET_DEBUG_RUNNING;
 592         if (restore_context(t) != ERROR_OK)
 593                 return ERROR_FAIL;
 594         if (exit_probemode(t) != ERROR_OK)
 595                 return ERROR_FAIL;
 596         t->state = TARGET_RUNNING;
 597
 598         t->debug_reason = DBG_REASON_NOTHALTED;
 599         LOG_USER("target running");
 600
 601         return target_call_event_callbacks(t, TARGET_EVENT_RESUMED);
 602 }
 603
 604 static int read_all_core_hw_regs(struct target *t)
 605 {
 606         int err;
 607         uint32_t regval;
 608         unsigned i;
 609         struct x86_32_common *x86_32 = target_to_x86_32(t);
 610         for (i = 0; i < (x86_32->cache->num_regs); i++) {
 611                 if (NOT_AVAIL_REG == regs[i].pm_idx)
 612                         continue;
 613                 err = read_hw_reg(t, regs[i].id, &regval, 1);
 614                 if (err != ERROR_OK) {
 615                         LOG_ERROR("%s error saving reg %s",
 616                                         __func__, x86_32->cache->reg_list[i].name);
 617                         return err;
 618                 }
 619         }
 620         LOG_DEBUG("read_all_core_hw_regs read %u registers ok", i);
 621         return ERROR_OK;
 622 }
 623
 624 static int write_all_core_hw_regs(struct target *t)
 625 {
 626         int err;
 627         unsigned i;
 628         struct x86_32_common *x86_32 = target_to_x86_32(t);
 629         for (i = 0; i < (x86_32->cache->num_regs); i++) {
 630                 if (NOT_AVAIL_REG == regs[i].pm_idx)
 631                         continue;
 632                 err = write_hw_reg(t, i, 0, 1);
 633                 if (err != ERROR_OK) {
 634                         LOG_ERROR("%s error restoring reg %s",
 635                                         __func__, x86_32->cache->reg_list[i].name);
 636                         return err;
 637                 }
 638         }
 639         LOG_DEBUG("write_all_core_hw_regs wrote %u registers ok", i);
 640         return ERROR_OK;
 641 }
 642
 643 /* read reg from lakemont core shadow ram, update reg cache if needed */
 644 static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cache)
 645 {
 646         struct x86_32_common *x86_32 = target_to_x86_32(t);
 647         struct lakemont_core_reg *arch_info;
 648         arch_info = x86_32->cache->reg_list[reg].arch_info;
 649         x86_32->flush = 0; /* dont flush scans till we have a batch */
 650         if (submit_reg_pir(t, reg) != ERROR_OK)
 651                 return ERROR_FAIL;
 652         if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
 653                 return ERROR_FAIL;
 654         if (submit_instruction_pir(t, SRAM2PDR) != ERROR_OK)
 655                 return ERROR_FAIL;
 656         x86_32->flush = 1;
 657         scan.out[0] = RDWRPDR;
 658         if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
 659                 return ERROR_FAIL;
 660         if (drscan(t, NULL, scan.out, PDR_SIZE) != ERROR_OK)
 661                 return ERROR_FAIL;
 662
 663         jtag_add_sleep(DELAY_SUBMITPIR);
 664         *regval = buf_get_u32(scan.out, 0, 32);
 665         if (cache) {
 666                 buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval);
 667                 x86_32->cache->reg_list[reg].valid = 1;
 668                 x86_32->cache->reg_list[reg].dirty = 0;
 669         }
 670         LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
 671                         x86_32->cache->reg_list[reg].name,
 672                         arch_info->op,
 673                         *regval);
 674         return ERROR_OK;
 675 }
 676
 677 /* write lakemont core shadow ram reg, update reg cache if needed */
 678 static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cache)
 679 {
 680         struct x86_32_common *x86_32 = target_to_x86_32(t);
 681         struct lakemont_core_reg *arch_info;
 682         arch_info = x86_32->cache->reg_list[reg].arch_info;
 683
 684         uint8_t reg_buf[4];
 685         if (cache)
 686                 regval = buf_get_u32(x86_32->cache->reg_list[reg].value, 0, 32);
 687         buf_set_u32(reg_buf, 0, 32, regval);
 688         LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
 689                         x86_32->cache->reg_list[reg].name,
 690                         arch_info->op,
 691                         regval);
 692
 693         x86_32->flush = 0; /* dont flush scans till we have a batch */
 694         if (submit_reg_pir(t, reg) != ERROR_OK)
 695                 return ERROR_FAIL;
 696         if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
 697                 return ERROR_FAIL;
 698         scan.out[0] = RDWRPDR;
 699         if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
 700                 return ERROR_FAIL;
 701         if (drscan(t, reg_buf, scan.out, PDR_SIZE) != ERROR_OK)
 702                 return ERROR_FAIL;
 703         x86_32->flush = 1;
 704         if (submit_instruction_pir(t, PDR2SRAM) != ERROR_OK)
 705                 return ERROR_FAIL;
 706
 707         /* we are writing from the cache so ensure we reset flags */
 708         if (cache) {
 709                 x86_32->cache->reg_list[reg].dirty = 0;
 710                 x86_32->cache->reg_list[reg].valid = 0;
 711         }
 712         return ERROR_OK;
 713 }
 714
 715 static bool is_paging_enabled(struct target *t)
 716 {
 717         struct x86_32_common *x86_32 = target_to_x86_32(t);
 718         if (x86_32->pm_regs[I(CR0)] & CR0_PG)
 719                 return true;
 720         else
 721                 return false;
 722 }
 723
 724 static uint8_t get_num_user_regs(struct target *t)
 725 {
 726         struct x86_32_common *x86_32 = target_to_x86_32(t);
 727         return x86_32->cache->num_regs;
 728 }
 729 /* value of the CR0.PG (paging enabled) bit influences memory reads/writes */
 730 static int disable_paging(struct target *t)
 731 {
 732         struct x86_32_common *x86_32 = target_to_x86_32(t);
 733         x86_32->pm_regs[I(CR0)] = x86_32->pm_regs[I(CR0)] & ~CR0_PG;
 734         int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);
 735         if (err != ERROR_OK) {
 736                 LOG_ERROR("%s error disabling paging", __func__);
 737                 return err;
 738         }
 739         return err;
 740 }
 741
 742 static int enable_paging(struct target *t)
 743 {
 744         struct x86_32_common *x86_32 = target_to_x86_32(t);
 745         x86_32->pm_regs[I(CR0)] = (x86_32->pm_regs[I(CR0)] | CR0_PG);
 746         int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);
 747         if (err != ERROR_OK) {
 748                 LOG_ERROR("%s error enabling paging", __func__);
 749                 return err;
 750         }
 751         return err;
 752 }
 753
 754 static bool sw_bpts_supported(struct target *t)
 755 {
 756         uint32_t tapstatus = get_tapstatus(t);
 757         if (tapstatus & TS_SBP_BIT)
 758                 return true;
 759         else
 760                 return false;
 761 }
 762
 763 static int transaction_status(struct target *t)
 764 {
 765         uint32_t tapstatus = get_tapstatus(t);
 766         if ((TS_EN_PM_BIT | TS_PRDY_BIT) & tapstatus) {
 767                 LOG_ERROR("%s transaction error tapstatus = 0x%08" PRIx32
 768                                 , __func__, tapstatus);
 769                 return ERROR_FAIL;
 770         } else {
 771                 return ERROR_OK;
 772         }
 773 }
 774
 775 static int submit_instruction(struct target *t, int num)
 776 {
 777         int err = submit_instruction_pir(t, num);
 778         if (err != ERROR_OK) {
 779                 LOG_ERROR("%s error submitting pir", __func__);
 780                 return err;
 781         }
 782         return err;
 783 }
 784
 785 static int submit_reg_pir(struct target *t, int num)
 786 {
 787         LOG_DEBUG("reg %s op=0x%016" PRIx64, regs[num].name, regs[num].op);
 788         int err = submit_pir(t, regs[num].op);
 789         if (err != ERROR_OK) {
 790                 LOG_ERROR("%s error submitting pir", __func__);
 791                 return err;
 792         }
 793         return err;
 794 }
 795
 796 static int submit_instruction_pir(struct target *t, int num)
 797 {
 798         LOG_DEBUG("%s op=0x%016" PRIx64, instructions[num].name,
 799                         instructions[num].op);
 800         int err = submit_pir(t, instructions[num].op);
 801         if (err != ERROR_OK) {
 802                 LOG_ERROR("%s error submitting pir", __func__);
 803                 return err;
 804         }
 805         return err;
 806 }
 807
 808 /*
 809  * PIR (Probe Mode Instruction Register), SUBMITPIR is an "IR only" TAP
 810  * command; there is no corresponding data register
 811  */
 812 static int submit_pir(struct target *t, uint64_t op)
 813 {
 814         struct x86_32_common *x86_32 = target_to_x86_32(t);
 815
 816         uint8_t op_buf[8];
 817         buf_set_u64(op_buf, 0, 64, op);
 818         int flush = x86_32->flush;
 819         x86_32->flush = 0;
 820         scan.out[0] = WRPIR;
 821         if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
 822                 return ERROR_FAIL;
 823         if (drscan(t, op_buf, scan.out, PIR_SIZE) != ERROR_OK)
 824                 return ERROR_FAIL;
 825         scan.out[0] = SUBMITPIR;
 826         x86_32->flush = flush;
 827         if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
 828                 return ERROR_FAIL;
 829         jtag_add_sleep(DELAY_SUBMITPIR);
 830         return ERROR_OK;
 831 }
 832
 833 int lakemont_init_target(struct command_context *cmd_ctx, struct target *t)
 834 {
 835         lakemont_build_reg_cache(t);
 836         t->state = TARGET_RUNNING;
 837         t->debug_reason = DBG_REASON_NOTHALTED;
 838         return ERROR_OK;
 839 }
 840
 841 int lakemont_init_arch_info(struct target *t, struct x86_32_common *x86_32)
 842 {
 843         x86_32->submit_instruction = submit_instruction;
 844         x86_32->transaction_status = transaction_status;
 845         x86_32->read_hw_reg = read_hw_reg;
 846         x86_32->write_hw_reg = write_hw_reg;
 847         x86_32->sw_bpts_supported = sw_bpts_supported;
 848         x86_32->get_num_user_regs = get_num_user_regs;
 849         x86_32->is_paging_enabled = is_paging_enabled;
 850         x86_32->disable_paging = disable_paging;
 851         x86_32->enable_paging = enable_paging;
 852         return ERROR_OK;
 853 }
 854
 855 int lakemont_poll(struct target *t)
 856 {
 857         /* LMT1 PMCR register currently allows code breakpoints, data breakpoints,
 858          * single stepping and shutdowns to be redirected to PM but does not allow
 859          * redirecting into PM as a result of SMM enter and SMM exit
 860          */
 861         uint32_t ts = get_tapstatus(t);
 862
 863         if (ts == 0xFFFFFFFF && t->state != TARGET_DEBUG_RUNNING) {
 864                 /* something is wrong here */
 865                 LOG_ERROR("tapstatus invalid - scan_chain serialization or locked JTAG access issues");
 866                 /* TODO: Give a hint that unlocking is wrong or maybe a
 867                  * 'jtag arp_init' helps
 868                  */
 869                 t->state = TARGET_DEBUG_RUNNING;
 870                 return ERROR_OK;
 871         }
 872
 873         if (t->state == TARGET_HALTED && (!(ts & TS_PM_BIT))) {
 874                 LOG_INFO("target running for unknown reason");
 875                 t->state = TARGET_RUNNING;
 876         }
 877
 878         if (t->state == TARGET_RUNNING &&
 879                 t->state != TARGET_DEBUG_RUNNING) {
 880
 881                 if ((ts & TS_PM_BIT) && (ts & TS_PMCR_BIT)) {
 882
 883                         LOG_DEBUG("redirect to PM, tapstatus=0x%08" PRIx32, get_tapstatus(t));
 884
 885                         t->state = TARGET_DEBUG_RUNNING;
 886                         if (save_context(t) != ERROR_OK)
 887                                 return ERROR_FAIL;
 888                         if (halt_prep(t) != ERROR_OK)
 889                                 return ERROR_FAIL;
 890                         t->state = TARGET_HALTED;
 891                         t->debug_reason = DBG_REASON_UNDEFINED;
 892
 893                         struct x86_32_common *x86_32 = target_to_x86_32(t);
 894                         uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
 895                         uint32_t dr6 = buf_get_u32(x86_32->cache->reg_list[DR6].value, 0, 32);
 896                         uint32_t hwbreakpoint = (uint32_t)-1;
 897
 898                         if (dr6 & DR6_BRKDETECT_0)
 899                                 hwbreakpoint = 0;
 900                         if (dr6 & DR6_BRKDETECT_1)
 901                                 hwbreakpoint = 1;
 902                         if (dr6 & DR6_BRKDETECT_2)
 903                                 hwbreakpoint = 2;
 904                         if (dr6 & DR6_BRKDETECT_3)
 905                                 hwbreakpoint = 3;
 906
 907                         if (hwbreakpoint != (uint32_t)-1) {
 908                                 uint32_t dr7 = buf_get_u32(x86_32->cache->reg_list[DR7].value, 0, 32);
 909                                 uint32_t type = dr7 & (0x03 << (DR7_RW_SHIFT + hwbreakpoint*DR7_RW_LEN_SIZE));
 910                                 if (type == DR7_BP_EXECUTE) {
 911                                         LOG_USER("hit hardware breakpoint (hwreg=%" PRIu32 ") at 0x%08" PRIx32, hwbreakpoint, eip);
 912                                 } else {
 913                                         uint32_t address = 0;
 914                                         switch (hwbreakpoint) {
 915                                         default:
 916                                         case 0:
 917                                                 address = buf_get_u32(x86_32->cache->reg_list[DR0].value, 0, 32);
 918                                         break;
 919                                         case 1:
 920                                                 address = buf_get_u32(x86_32->cache->reg_list[DR1].value, 0, 32);
 921                                         break;
 922                                         case 2:
 923                                                 address = buf_get_u32(x86_32->cache->reg_list[DR2].value, 0, 32);
 924                                         break;
 925                                         case 3:
 926                                                 address = buf_get_u32(x86_32->cache->reg_list[DR3].value, 0, 32);
 927                                         break;
 928                                         }
 929                                         LOG_USER("hit '%s' watchpoint for 0x%08" PRIx32 " (hwreg=%" PRIu32 ") at 0x%08" PRIx32,
 930                                                                 type == DR7_BP_WRITE ? "write" : "access", address,
 931                                                                 hwbreakpoint, eip);
 932                                 }
 933                                 t->debug_reason = DBG_REASON_BREAKPOINT;
 934                         } else {
 935                                 /* Check if the target hit a software breakpoint.
 936                                  * ! Watch out: EIP is currently pointing after the breakpoint opcode
 937                                  */
 938                                 struct breakpoint *bp = NULL;
 939                                 bp = breakpoint_find(t, eip-1);
 940                                 if (bp != NULL) {
 941                                         t->debug_reason = DBG_REASON_BREAKPOINT;
 942                                         if (bp->type == BKPT_SOFT) {
 943                                                 /* The EIP is now pointing the the next byte after the
 944                                                  * breakpoint instruction. This needs to be corrected.
 945                                                  */
 946                                                 buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
 947                                                 x86_32->cache->reg_list[EIP].dirty = 1;
 948                                                 x86_32->cache->reg_list[EIP].valid = 1;
 949                                                 LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1);
 950                                         } else {
 951                                                 /* it's not a hardware breakpoint (checked already in DR6 state)
 952                                                  * and it's also not a software breakpoint ...
 953                                                  */
 954                                                 LOG_USER("hit unknown breakpoint at 0x%08" PRIx32, eip);
 955                                         }
 956                                 } else {
 957
 958                                         /* There is also the case that we hit an breakpoint instruction,
 959                                          * which was not set by us. This needs to be handled be the
 960                                          * application that introduced the breakpoint.
 961                                          */
 962
 963                                         LOG_USER("unknown break reason at 0x%08" PRIx32, eip);
 964                                 }
 965                         }
 966
 967                         return target_call_event_callbacks(t, TARGET_EVENT_HALTED);
 968                 }
 969         }
 970         return ERROR_OK;
 971 }
 972
 973 int lakemont_arch_state(struct target *t)
 974 {
 975         struct x86_32_common *x86_32 = target_to_x86_32(t);
 976
 977         LOG_USER("target halted due to %s at 0x%08" PRIx32 " in %s mode",
 978                         debug_reason_name(t),
 979                         buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32),
 980                         (buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32) & CR0_PE) ? "protected" : "real");
 981
 982         return ERROR_OK;
 983 }
 984
 985 int lakemont_halt(struct target *t)
 986 {
 987         if (t->state == TARGET_RUNNING) {
 988                 t->debug_reason = DBG_REASON_DBGRQ;
 989                 if (do_halt(t) != ERROR_OK)
 990                         return ERROR_FAIL;
 991                 return ERROR_OK;
 992         } else {
 993                 LOG_ERROR("%s target not running", __func__);
 994                 return ERROR_FAIL;
 995         }
 996 }
 997
 998 int lakemont_resume(struct target *t, int current, uint32_t address,
 999                         int handle_breakpoints, int debug_execution)
1000 {
1001         struct breakpoint *bp = NULL;
1002         struct x86_32_common *x86_32 = target_to_x86_32(t);
1003
1004         if (check_not_halted(t))
1005                 return ERROR_TARGET_NOT_HALTED;
1006         /* TODO lakemont_enable_breakpoints(t); */
1007         if (t->state == TARGET_HALTED) {
1008
1009                 /* running away for a software breakpoint needs some special handling */
1010                 uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
1011                 bp = breakpoint_find(t, eip);
1012                 if (bp != NULL /*&& bp->type == BKPT_SOFT*/) {
1013                         /* the step will step over the breakpoint */
1014                         if (lakemont_step(t, 0, 0, 1) != ERROR_OK) {
1015                                 LOG_ERROR("%s stepping over a software breakpoint at 0x%08" PRIx32 " "
1016                                                 "failed to resume the target", __func__, eip);
1017                                 return ERROR_FAIL;
1018                         }
1019                 }
1020
1021                 /* if breakpoints are enabled, we need to redirect these into probe mode */
1022                 struct breakpoint *activeswbp = t->breakpoints;
1023                 while (activeswbp != NULL && activeswbp->set == 0)
1024                         activeswbp = activeswbp->next;
1025                 struct watchpoint *activehwbp = t->watchpoints;
1026                 while (activehwbp != NULL && activehwbp->set == 0)
1027                         activehwbp = activehwbp->next;
1028                 if (activeswbp != NULL || activehwbp != NULL)
1029                         buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
1030                 if (do_resume(t) != ERROR_OK)
1031                         return ERROR_FAIL;
1032         } else {
1033                 LOG_USER("target not halted");
1034                 return ERROR_FAIL;
1035         }
1036         return ERROR_OK;
1037 }
1038
1039 int lakemont_step(struct target *t, int current,
1040                         uint32_t address, int handle_breakpoints)
1041 {
1042         struct x86_32_common *x86_32 = target_to_x86_32(t);
1043         uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
1044         uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
1045         uint32_t pmcr = buf_get_u32(x86_32->cache->reg_list[PMCR].value, 0, 32);
1046         struct breakpoint *bp = NULL;
1047         int retval = ERROR_OK;
1048         uint32_t tapstatus = 0;
1049
1050         if (check_not_halted(t))
1051                 return ERROR_TARGET_NOT_HALTED;
1052         bp = breakpoint_find(t, eip);
1053         if (retval == ERROR_OK && bp != NULL/*&& bp->type == BKPT_SOFT*/) {
1054                 /* TODO: This should only be done for software breakpoints.
1055                  * Stepping from hardware breakpoints should be possible with the resume flag
1056                  * Needs testing.
1057                  */
1058                 retval = x86_32_common_remove_breakpoint(t, bp);
1059         }
1060
1061         /* Set EFLAGS[TF] and PMCR[IR], exit pm and wait for PRDY# */
1062         LOG_DEBUG("modifying PMCR = 0x%08" PRIx32 " and EFLAGS = 0x%08" PRIx32, pmcr, eflags);
1063         eflags = eflags | (EFLAGS_TF | EFLAGS_RF);
1064         buf_set_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32, eflags);
1065         buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
1066         LOG_DEBUG("EFLAGS [TF] [RF] bits set=0x%08" PRIx32 ", PMCR=0x%08" PRIx32 ", EIP=0x%08" PRIx32,
1067                         eflags, pmcr, eip);
1068
1069         tapstatus = get_tapstatus(t);
1070
1071         t->debug_reason = DBG_REASON_SINGLESTEP;
1072         t->state = TARGET_DEBUG_RUNNING;
1073         if (restore_context(t) != ERROR_OK)
1074                 return ERROR_FAIL;
1075         if (exit_probemode(t) != ERROR_OK)
1076                 return ERROR_FAIL;
1077
1078         target_call_event_callbacks(t, TARGET_EVENT_RESUMED);
1079
1080         tapstatus = get_tapstatus(t);
1081         if (tapstatus & (TS_PM_BIT | TS_EN_PM_BIT | TS_PRDY_BIT | TS_PMCR_BIT)) {
1082                 /* target has stopped */
1083                 if (save_context(t) != ERROR_OK)
1084                         return ERROR_FAIL;
1085                 if (halt_prep(t) != ERROR_OK)
1086                         return ERROR_FAIL;
1087                 t->state = TARGET_HALTED;
1088
1089                 LOG_USER("step done from EIP 0x%08" PRIx32 " to 0x%08" PRIx32, eip,
1090                                 buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32));
1091                 target_call_event_callbacks(t, TARGET_EVENT_HALTED);
1092         } else {
1093                 /* target didn't stop
1094                  * I hope the poll() will catch it, but the deleted breakpoint is gone
1095                  */
1096                 LOG_ERROR("%s target didn't stop after executing a single step", __func__);
1097                 t->state = TARGET_RUNNING;
1098                 return ERROR_FAIL;
1099         }
1100
1101         /* try to re-apply the breakpoint, even of step failed
1102          * TODO: When a bp was set, we should try to stop the target - fix the return above
1103          */
1104         if (bp != NULL/*&& bp->type == BKPT_SOFT*/) {
1105                 /* TODO: This should only be done for software breakpoints.
1106                  * Stepping from hardware breakpoints should be possible with the resume flag
1107                  * Needs testing.
1108                  */
1109                 retval = x86_32_common_add_breakpoint(t, bp);
1110         }
1111
1112         return retval;
1113 }
1114
1115 /* TODO - implement resetbreak fully through CLTAP registers */
1116 int lakemont_reset_assert(struct target *t)
1117 {
1118         LOG_DEBUG("-");
1119         return ERROR_OK;
1120 }
1121
1122 int lakemont_reset_deassert(struct target *t)
1123 {
1124         LOG_DEBUG("-");
1125         return ERROR_OK;
1126 }