Nicolas Pitre fixed regression.
[openocd.git] / src / target / feroceon.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Marvell Semiconductors, Inc. *
3 * Written by Nicolas Pitre <nico@marvell.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 /*
22 * Marvell Feroceon (88F5182, 88F5281) support.
23 *
24 * The Feroceon core mimics the ARM926 ICE interface with the following
25 * differences:
26 *
27 * - the MOE (method of entry) reporting is not implemented
28 *
29 * - breakpoint/watchpoint comparator #1 is seemingly not implemented
30 *
31 * - due to a different pipeline implementation, some injected debug
32 * instruction sequences have to be somewhat different
33 *
34 * Other issues:
35 *
36 * - asserting DBGRQ doesn't work if target is looping on the undef vector
37 *
38 * - the EICE version signature in the COMMS_CTL reg is next to the flow bits
39 * not at the top, and rather meaningless due to existing discrepencies
40 *
41 * - the DCC channel is half duplex (only one FIFO for both directions) with
42 * seemingly no proper flow control.
43 */
44
45 #ifdef HAVE_CONFIG_H
46 #include "config.h"
47 #endif
48
49 #include "arm926ejs.h"
50 #include "jtag.h"
51 #include "log.h"
52 #include "arm_simulator.h"
53
54 #include <stdlib.h>
55 #include <string.h>
56
57 int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s *target);
58 int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
59 int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
60 int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
61 int feroceon_quit();
62
63 target_type_t feroceon_target =
64 {
65 .name = "feroceon",
66
67 .poll = arm7_9_poll,
68 .arch_state = arm926ejs_arch_state,
69
70 .target_request_data = arm7_9_target_request_data,
71
72 .halt = arm7_9_halt,
73 .resume = arm7_9_resume,
74 .step = arm7_9_step,
75
76 .assert_reset = arm7_9_assert_reset,
77 .deassert_reset = arm7_9_deassert_reset,
78 .soft_reset_halt = arm926ejs_soft_reset_halt,
79
80 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
81
82 .read_memory = arm7_9_read_memory,
83 .write_memory = arm926ejs_write_memory,
84 .bulk_write_memory = feroceon_bulk_write_memory,
85 .checksum_memory = arm7_9_checksum_memory,
86
87 .run_algorithm = armv4_5_run_algorithm,
88
89 .add_breakpoint = arm7_9_add_breakpoint,
90 .remove_breakpoint = arm7_9_remove_breakpoint,
91 .add_watchpoint = arm7_9_add_watchpoint,
92 .remove_watchpoint = arm7_9_remove_watchpoint,
93
94 .register_commands = arm926ejs_register_commands,
95 .target_command = feroceon_target_command,
96 .init_target = feroceon_init_target,
97 .examine = feroceon_examine,
98 .quit = feroceon_quit
99 };
100
101
102 void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc)
103 {
104 armv4_5_common_t *armv4_5 = target->arch_info;
105 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
106 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
107
108 /*
109 * save r0 before using it and put system in ARM state
110 * to allow common handling of ARM and THUMB debugging
111 */
112
113 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
114 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
115 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
116 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
117 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
118 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
119 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
120 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
121 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
122
123 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
124 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
125 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
126 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
127 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
128 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
129 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
130
131 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(15), 0, NULL, 0);
132 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
133 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
134 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
135 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
136
137 jtag_execute_queue();
138
139 /*
140 * fix program counter:
141 * MOV R0, PC was the 10th instruction (+18)
142 * reading PC in Thumb state gives address of instruction + 4
143 */
144 *pc -= 22;
145 }
146
147 void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
148 {
149 int i;
150 armv4_5_common_t *armv4_5 = target->arch_info;
151 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
152 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
153
154 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
155 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
156 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
157
158 for (i = 0; i <= 15; i++)
159 if (mask & (1 << i))
160 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
161
162 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
163 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
164 }
165
166 void feroceon_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
167 {
168 int i;
169 armv4_5_common_t *armv4_5 = target->arch_info;
170 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
171 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
172 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
173 u32 *buf_u32 = buffer;
174 u16 *buf_u16 = buffer;
175 u8 *buf_u8 = buffer;
176
177 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
178 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
179 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
180
181 for (i = 0; i <= 15; i++)
182 {
183 if (mask & (1 << i)) {
184 switch (size)
185 {
186 case 4:
187 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
188 break;
189 case 2:
190 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
191 break;
192 case 1:
193 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
194 break;
195 }
196 }
197 }
198
199 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
200 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
201 }
202
203 void feroceon_read_xpsr(target_t *target, u32 *xpsr, int spsr)
204 {
205 armv4_5_common_t *armv4_5 = target->arch_info;
206 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
207 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
208
209 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
210 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
211 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
212 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
213 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
214 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
215 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
216
217 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, 1, 0, 0), 0, NULL, 0);
218 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
219 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
220 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
221
222 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
223 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
224 }
225
226 void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr)
227 {
228 armv4_5_common_t *armv4_5 = target->arch_info;
229 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
230 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
231
232 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
233
234 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
235 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
236 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
237 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
238 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
239 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
240 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
241
242 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
243 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
244 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
245 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
246 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
247 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
248 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
249
250 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
251 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
252 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
253 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
254 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
255 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
256 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
257
258 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
259 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
260 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
261 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
262 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
263 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
264 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
265 }
266
267 void feroceon_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
268 {
269 armv4_5_common_t *armv4_5 = target->arch_info;
270 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
271 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
272
273 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
274
275 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
276 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
277 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
278 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
279 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
280 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
281 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
282 }
283
284 void feroceon_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
285 {
286 int i;
287 armv4_5_common_t *armv4_5 = target->arch_info;
288 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
289 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
290
291 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
292 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
293 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
294
295 for (i = 0; i <= 15; i++)
296 if (mask & (1 << i))
297 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
298
299 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
300 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
301 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
302 }
303
304 void feroceon_branch_resume(target_t *target)
305 {
306 armv4_5_common_t *armv4_5 = target->arch_info;
307 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
308 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
309
310 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
311 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
312 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
313 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffff9, 0), 0, NULL, 0);
314 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
315
316 /* need BYPASS before RESTART */
317 jtag_add_end_state(TAP_RTI);
318 arm_jtag_set_instr(jtag_info, 0xf, NULL);
319 }
320
321 void feroceon_branch_resume_thumb(target_t *target)
322 {
323 LOG_DEBUG("-");
324
325 armv4_5_common_t *armv4_5 = target->arch_info;
326 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
327 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
328 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
329 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
330
331 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
332 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
333 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
334 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc & ~3, NULL, 0);
335 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
336 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
337 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
338
339 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
340 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
341 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
342 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
343
344 arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); /* add r0,r15,#1 */
345 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
346 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
347 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
348
349 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 1), 0, NULL, 0);
350 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
351 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
352 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, r0, NULL, 0);
353 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
354 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
355
356 pc = (pc & 2) >> 1;
357 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7e9 + pc), 0, NULL, 0);
358 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 1);
359
360 /* need BYPASS before RESTART */
361 jtag_add_end_state(TAP_RTI);
362 arm_jtag_set_instr(jtag_info, 0xf, NULL);
363 }
364
365 int feroceon_read_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
366 {
367 armv4_5_common_t *armv4_5 = target->arch_info;
368 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
369 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
370 int err;
371
372 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
373 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
374 err = arm7_9_execute_sys_speed(target);
375 if (err != ERROR_OK)
376 return err;
377
378 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, 1, 0, 0), 0, NULL, 0);
379 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
380 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
381 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, value, 0);
382 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
383 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
384 return jtag_execute_queue();
385 }
386
387 int feroceon_write_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
388 {
389 armv4_5_common_t *armv4_5 = target->arch_info;
390 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
391 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
392
393 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
394 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
395 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
396 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, value, NULL, 0);
397 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
398 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
399 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
400
401 arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
402 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
403 return arm7_9_execute_sys_speed(target);
404 }
405
406 void feroceon_enable_single_step(target_t *target)
407 {
408 armv4_5_common_t *armv4_5 = target->arch_info;
409 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
410 u32 next_pc;
411
412 /* calculate PC of next instruction */
413 if (arm_simulate_step(target, &next_pc) != ERROR_OK)
414 {
415 u32 current_pc, current_opcode;
416 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
417 target_read_u32(target, current_pc, &current_opcode);
418 LOG_ERROR("BUG: couldn't calculate PC of next instruction, "
419 "current opcode is 0x%8.8x", current_opcode);
420 next_pc = current_pc;
421 }
422 arm7_9_restore_context(target);
423
424 /* set a breakpoint there */
425 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc);
426 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0);
427 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
428 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
429 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
430 }
431
432 void feroceon_disable_single_step(target_t *target)
433 {
434 armv4_5_common_t *armv4_5 = target->arch_info;
435 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
436
437 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
438 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
439 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
440 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
441 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
442 }
443
444 int feroceon_examine_debug_reason(target_t *target)
445 {
446 /* the MOE is not implemented */
447 if (target->debug_reason != DBG_REASON_SINGLESTEP)
448 {
449 target->debug_reason = DBG_REASON_DBGRQ;
450 }
451
452 return ERROR_OK;
453 }
454
455 int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
456 {
457 armv4_5_common_t *armv4_5 = target->arch_info;
458 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
459 enum armv4_5_state core_state = armv4_5->core_state;
460 u32 x, flip, shift, save[7];
461 int i;
462
463 /*
464 * We can't use the dcc flow control bits, so let's transfer data
465 * with 31 bits and flip the MSB each time a new data word is sent.
466 */
467 static u32 dcc_code[] =
468 {
469 0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */
470 0xe3a0301e, /* 1: mov r3, #30 */
471 0xe3a04002, /* mov r4, #2 */
472 0xee111e10, /* 2: mrc p14, 0, r1, c1, c0, 0 */
473 0xe1310005, /* teq r1, r5 */
474 0x0afffffc, /* beq 1b */
475 0xe1a05001, /* mov r5, r1 */
476 0xe1a01081, /* mov r1, r1, lsl #1 */
477 0xee112e10, /* 3: mrc p14, 0, r2, c1, c0, 0 */
478 0xe1320005, /* teq r2, r5 */
479 0x0afffffc, /* beq 3b */
480 0xe1a05002, /* mov r5, r2 */
481 0xe3c22102, /* bic r2, r2, #0x80000000 */
482 0xe1811332, /* orr r1, r1, r2, lsr r3 */
483 0xe2533001, /* subs r3, r3, #1 */
484 0xe4801004, /* str r1, [r0], #4 */
485 0xe1a01412, /* mov r1, r2, lsl r4 */
486 0xe2844001, /* add r4, r4, #1 */
487 0x4affffed, /* bmi 1b */
488 0xeafffff3, /* b 3b */
489 };
490
491 int dcc_size = sizeof(dcc_code);
492
493 if (!arm7_9->dcc_downloads)
494 return target->type->write_memory(target, address, 4, count, buffer);
495
496 /* regrab previously allocated working_area, or allocate a new one */
497 if (!arm7_9->dcc_working_area)
498 {
499 u8 dcc_code_buf[dcc_size];
500
501 /* make sure we have a working area */
502 if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK)
503 {
504 LOG_INFO("no working area available, falling back to memory writes");
505 return target->type->write_memory(target, address, 4, count, buffer);
506 }
507
508 /* copy target instructions to target endianness */
509 for (i = 0; i < dcc_size/4; i++)
510 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
511
512 /* write DCC code to working area */
513 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf);
514 }
515
516 /* backup clobbered processor state */
517 for (i = 0; i <= 5; i++)
518 save[i] = buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32);
519 save[i] = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
520
521 /* set up target address in r0 */
522 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
523 armv4_5->core_cache->reg_list[0].valid = 1;
524 armv4_5->core_cache->reg_list[0].dirty = 1;
525 armv4_5->core_state = ARMV4_5_STATE_ARM;
526
527 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
528 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
529
530 /* send data over */
531 x = 0;
532 flip = 0;
533 shift = 1;
534 for (i = 0; i < count; i++)
535 {
536 u32 y = target_buffer_get_u32(target, buffer);
537 u32 z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000);
538 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
539 x = y << (32 - shift);
540 if (++shift >= 32 || i + 1 >= count)
541 {
542 z = (x >> 1) | (flip ^= 0x80000000);
543 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
544 x = 0;
545 shift = 1;
546 }
547 buffer += 4;
548 }
549
550 target_halt(target);
551 while (target->state != TARGET_HALTED)
552 target_poll(target);
553
554 /* restore target state */
555 for (i = 0; i <= 5; i++)
556 {
557 buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, save[i]);
558 armv4_5->core_cache->reg_list[i].valid = 1;
559 armv4_5->core_cache->reg_list[i].dirty = 1;
560 }
561 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, save[i]);
562 armv4_5->core_cache->reg_list[15].valid = 1;
563 armv4_5->core_cache->reg_list[15].dirty = 1;
564 armv4_5->core_state = core_state;
565
566 return ERROR_OK;
567 }
568
569 int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
570 {
571 arm9tdmi_init_target(cmd_ctx, target);
572 return ERROR_OK;
573 }
574
575 int feroceon_quit()
576 {
577 return ERROR_OK;
578 }
579
580 int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
581 {
582 int chain_pos;
583 char *variant = NULL;
584 armv4_5_common_t *armv4_5;
585 arm7_9_common_t *arm7_9;
586 arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
587 memset(arm926ejs, 0, sizeof(*arm926ejs));
588
589 if (argc < 4)
590 {
591 LOG_ERROR("'target arm926ejs' requires at least one additional argument");
592 exit(-1);
593 }
594
595 chain_pos = strtoul(args[3], NULL, 0);
596
597 if (argc >= 5)
598 variant = args[4];
599
600 LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
601
602 arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
603
604 armv4_5 = target->arch_info;
605 arm7_9 = armv4_5->arch_info;
606
607 /* override some insn sequence functions */
608 arm7_9->change_to_arm = feroceon_change_to_arm;
609 arm7_9->read_core_regs = feroceon_read_core_regs;
610 arm7_9->read_core_regs_target_buffer = feroceon_read_core_regs_target_buffer;
611 arm7_9->read_xpsr = feroceon_read_xpsr;
612 arm7_9->write_xpsr = feroceon_write_xpsr;
613 arm7_9->write_xpsr_im8 = feroceon_write_xpsr_im8;
614 arm7_9->write_core_regs = feroceon_write_core_regs;
615 arm7_9->branch_resume = feroceon_branch_resume;
616 arm7_9->branch_resume_thumb = feroceon_branch_resume_thumb;
617
618 /* must be implemented with only one comparator */
619 arm7_9->enable_single_step = feroceon_enable_single_step;
620 arm7_9->disable_single_step = feroceon_disable_single_step;
621
622 /* MOE is not implemented */
623 arm7_9->examine_debug_reason = feroceon_examine_debug_reason;
624
625 /* the standard ARM926 methods don't always work (don't ask...) */
626 arm926ejs->read_cp15 = feroceon_read_cp15;
627 arm926ejs->write_cp15 = feroceon_write_cp15;
628
629 /* asserting DBGRQ won't win over the undef exception */
630 arm7_9->use_dbgrq = 0;
631
632 /* only one working comparator */
633 arm7_9->wp_available = 1;
634 arm7_9->wp1_used = -1;
635
636 return ERROR_OK;
637 }
638
639
640 int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s *target)
641 {
642 armv4_5_common_t *armv4_5;
643 arm7_9_common_t *arm7_9;
644 int retval;
645
646 retval = arm9tdmi_examine(cmd_ctx, target);
647 if (retval!=ERROR_OK)
648 return retval;
649
650 armv4_5 = target->arch_info;
651 arm7_9 = armv4_5->arch_info;
652
653 /* the COMMS_CTRL bits are all contiguous */
654 if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6)
655 LOG_ERROR("unexpected Feroceon EICE version signature");
656
657 arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
658 arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
659 arm7_9->has_monitor_mode = 1;
660
661 /* vector catch reg is not initialized on reset */
662 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0);
663
664 /* clear monitor mode, enable comparators */
665 embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
666 jtag_execute_queue();
667 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
668 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
669 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
670
671 return ERROR_OK;
672 }