1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007 by Vincent Palatin *
6 * vincent.palatin_openocd@m4x.org *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
34 /* ETM registers (V1.3 protocol) */
39 ETM_TRIG_EVENT
= 0x02,
42 ETM_SYS_CONFIG
= 0x05,
43 ETM_TRACE_RESOURCE_CTRL
= 0x06,
44 ETM_TRACE_EN_CTRL2
= 0x07,
45 ETM_TRACE_EN_EVENT
= 0x08,
46 ETM_TRACE_EN_CTRL1
= 0x09,
47 ETM_FIFOFULL_REGION
= 0x0a,
48 ETM_FIFOFULL_LEVEL
= 0x0b,
49 ETM_VIEWDATA_EVENT
= 0x0c,
50 ETM_VIEWDATA_CTRL1
= 0x0d,
51 ETM_VIEWDATA_CTRL2
= 0x0e,
52 ETM_VIEWDATA_CTRL3
= 0x0f,
53 ETM_ADDR_COMPARATOR_VALUE
= 0x10,
54 ETM_ADDR_ACCESS_TYPE
= 0x20,
55 ETM_DATA_COMPARATOR_VALUE
= 0x30,
56 ETM_DATA_COMPARATOR_MASK
= 0x40,
57 ETM_COUNTER_INITAL_VALUE
= 0x50,
58 ETM_COUNTER_ENABLE
= 0x54,
59 ETM_COUNTER_RELOAD_VALUE
= 0x58,
60 ETM_COUNTER_VALUE
= 0x5c,
61 ETM_SEQUENCER_CTRL
= 0x60,
62 ETM_SEQUENCER_STATE
= 0x67,
63 ETM_EXTERNAL_OUTPUT
= 0x68,
64 ETM_CONTEXTID_COMPARATOR_VALUE
= 0x6c,
65 ETM_CONTEXTID_COMPARATOR_MASK
= 0x6f,
68 typedef struct etm_reg_s
71 arm_jtag_t
*jtag_info
;
79 ETM_PORT_16BIT
= 0x20,
80 ETM_PORT_WIDTH_MASK
= 0x70,
82 ETM_PORT_NORMAL
= 0x00000,
83 ETM_PORT_MUXED
= 0x10000,
84 ETM_PORT_DEMUXED
= 0x20000,
85 ETM_PORT_MODE_MASK
= 0x30000,
87 ETM_PORT_FULL_CLOCK
= 0x0000,
88 ETM_PORT_HALF_CLOCK
= 0x1000,
89 ETM_PORT_CLOCK_MASK
= 0x1000,
95 ETMV1_TRACE_NONE
= 0x00,
96 ETMV1_TRACE_DATA
= 0x01,
97 ETMV1_TRACE_ADDR
= 0x02,
98 ETMV1_TRACE_MASK
= 0x03,
100 ETMV1_CONTEXTID_NONE
= 0x00,
101 ETMV1_CONTEXTID_8
= 0x10,
102 ETMV1_CONTEXTID_16
= 0x20,
103 ETMV1_CONTEXTID_32
= 0x30,
104 ETMV1_CONTEXTID_MASK
= 0x30,
106 ETMV1_CYCLE_ACCURATE
= 0x100
109 /* forward-declare ETM context */
110 struct etm_context_s
;
112 typedef struct etm_capture_driver_s
115 int (*register_commands
)(struct command_context_s
*cmd_ctx
);
116 int (*init
)(struct etm_context_s
*etm_ctx
);
117 trace_status_t (*status
)(struct etm_context_s
*etm_ctx
);
118 int (*read_trace
)(struct etm_context_s
*etm_ctx
);
119 int (*start_capture
)(struct etm_context_s
*etm_ctx
);
120 int (*stop_capture
)(struct etm_context_s
*etm_ctx
);
121 } etm_capture_driver_t
;
123 typedef struct etmv1_trace_data_s
125 u8 pipestat
; /* pipeline cycle this packet belongs to */
126 u16 packet
; /* packet data (4, 8 or 16 bit) */
127 int tracesync
; /* 1 if tracesync was set on this packet */
128 } etmv1_trace_data_t
;
130 /* describe a trace context
131 * if support for ETMv2 or ETMv3 is to be implemented,
132 * this will have to be split into version independent elements
133 * and a version specific part
135 typedef struct etm_context_s
137 reg_cache_t
*reg_cache
; /* ETM register cache */
138 etm_capture_driver_t
*capture_driver
; /* driver used to access ETM data */
139 void *capture_driver_priv
; /* capture driver private data */
140 trace_status_t capture_status
; /* current state of capture run */
141 etmv1_trace_data_t
*trace_data
; /* trace data */
142 u32 trace_depth
; /* number of trace cycles to be analyzed, 0 if no trace data available */
143 etm_portmode_t portmode
; /* normal, multiplexed or demultiplexed */
144 etmv1_tracemode_t tracemode
; /* type of information the trace contains (data, addres, contextID, ...) */
145 armv4_5_state_t core_state
; /* current core state (ARM, Thumb, Jazelle) */
146 image_t image
; /* source for target opcodes */
147 u32 pipe_index
; /* current trace cycle */
148 u32 data_index
; /* cycle holding next data packet */
149 u32 current_pc
; /* current program counter */
150 u32 pc_ok
; /* full PC has been acquired */
151 u32 last_branch
; /* last branch address output */
152 u32 last_ptr
; /* address of the last data access */
153 u32 context_id
; /* context ID of the code being traced */
156 /* PIPESTAT values */
169 /* branch reason values */
172 BR_NORMAL
= 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */
173 BR_ENABLE
= 0x1, /* Trace has been enabled */
174 BR_RESTART
= 0x2, /* Trace restarted after a FIFO overflow */
175 BR_NODEBUG
= 0x3, /* ARM has exited for debug state */
176 BR_PERIOD
= 0x4, /* Peridioc synchronization point (ETM>=v1.2)*/
177 BR_RSVD5
= 0x5, /* reserved */
178 BR_RSVD6
= 0x6, /* reserved */
179 BR_RSVD7
= 0x7, /* reserved */
180 } etmv1_branch_reason_t
;
182 extern char *etmv1v1_branch_reason_strings
[];
184 extern reg_cache_t
* etm_build_reg_cache(target_t
*target
, arm_jtag_t
*jtag_info
, etm_context_t
*etm_ctx
);
185 extern int etm_read_reg(reg_t
*reg
);
186 extern int etm_write_reg(reg_t
*reg
, u32 value
);
187 extern int etm_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
);
188 extern int etm_store_reg(reg_t
*reg
);
189 extern int etm_set_reg(reg_t
*reg
, u32 value
);
190 extern int etm_set_reg_w_exec(reg_t
*reg
, u8
*buf
);
192 int etm_register_commands(struct command_context_s
*cmd_ctx
);
193 int etm_register_user_commands(struct command_context_s
*cmd_ctx
);
194 extern etm_context_t
* etm_create_context(etm_portmode_t portmode
, char *capture_driver_name
);
196 #define ERROR_ETM_INVALID_DRIVER (-1300)
197 #define ERROR_ETM_PORTMODE_NOT_SUPPORTED (-1301)
198 #define ERROR_ETM_CAPTURE_INIT_FAILED (-1302)
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