1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
30 #include "arm7_9_common.h"
31 #include "arm_disassembler.h"
32 #include "arm_simulator.h"
37 #include "binarybuffer.h"
45 /* ETM register access functionality
49 bitfield_desc_t etm_comms_ctrl_bitfield_desc
[] =
57 int etm_reg_arch_info
[] =
59 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
60 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
61 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
62 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
63 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
64 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
65 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
66 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
67 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
68 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
69 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
70 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
71 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
72 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
75 int etm_reg_arch_size_info
[] =
77 32, 32, 17, 8, 3, 9, 32, 16,
78 17, 26, 25, 8, 17, 32, 32, 17,
79 32, 32, 32, 32, 32, 32, 32, 32,
80 32, 32, 32, 32, 32, 32, 32, 32,
81 7, 7, 7, 7, 7, 7, 7, 7,
82 7, 7, 7, 7, 7, 7, 7, 7,
83 32, 32, 32, 32, 32, 32, 32, 32,
84 32, 32, 32, 32, 32, 32, 32, 32,
85 32, 32, 32, 32, 32, 32, 32, 32,
86 32, 32, 32, 32, 32, 32, 32, 32,
87 16, 16, 16, 16, 18, 18, 18, 18,
88 17, 17, 17, 17, 16, 16, 16, 16,
89 17, 17, 17, 17, 17, 17, 2,
90 17, 17, 17, 17, 32, 32, 32, 32
93 char* etm_reg_list
[] =
101 "ETM_TRACE_RESOURCE_CTRL",
102 "ETM_TRACE_EN_CTRL2",
103 "ETM_TRACE_EN_EVENT",
104 "ETM_TRACE_EN_CTRL1",
105 "ETM_FIFOFULL_REGION",
106 "ETM_FIFOFULL_LEVEL",
107 "ETM_VIEWDATA_EVENT",
108 "ETM_VIEWDATA_CTRL1",
109 "ETM_VIEWDATA_CTRL2",
110 "ETM_VIEWDATA_CTRL3",
111 "ETM_ADDR_COMPARATOR_VALUE1",
112 "ETM_ADDR_COMPARATOR_VALUE2",
113 "ETM_ADDR_COMPARATOR_VALUE3",
114 "ETM_ADDR_COMPARATOR_VALUE4",
115 "ETM_ADDR_COMPARATOR_VALUE5",
116 "ETM_ADDR_COMPARATOR_VALUE6",
117 "ETM_ADDR_COMPARATOR_VALUE7",
118 "ETM_ADDR_COMPARATOR_VALUE8",
119 "ETM_ADDR_COMPARATOR_VALUE9",
120 "ETM_ADDR_COMPARATOR_VALUE10",
121 "ETM_ADDR_COMPARATOR_VALUE11",
122 "ETM_ADDR_COMPARATOR_VALUE12",
123 "ETM_ADDR_COMPARATOR_VALUE13",
124 "ETM_ADDR_COMPARATOR_VALUE14",
125 "ETM_ADDR_COMPARATOR_VALUE15",
126 "ETM_ADDR_COMPARATOR_VALUE16",
127 "ETM_ADDR_ACCESS_TYPE1",
128 "ETM_ADDR_ACCESS_TYPE2",
129 "ETM_ADDR_ACCESS_TYPE3",
130 "ETM_ADDR_ACCESS_TYPE4",
131 "ETM_ADDR_ACCESS_TYPE5",
132 "ETM_ADDR_ACCESS_TYPE6",
133 "ETM_ADDR_ACCESS_TYPE7",
134 "ETM_ADDR_ACCESS_TYPE8",
135 "ETM_ADDR_ACCESS_TYPE9",
136 "ETM_ADDR_ACCESS_TYPE10",
137 "ETM_ADDR_ACCESS_TYPE11",
138 "ETM_ADDR_ACCESS_TYPE12",
139 "ETM_ADDR_ACCESS_TYPE13",
140 "ETM_ADDR_ACCESS_TYPE14",
141 "ETM_ADDR_ACCESS_TYPE15",
142 "ETM_ADDR_ACCESS_TYPE16",
143 "ETM_DATA_COMPARATOR_VALUE1",
144 "ETM_DATA_COMPARATOR_VALUE2",
145 "ETM_DATA_COMPARATOR_VALUE3",
146 "ETM_DATA_COMPARATOR_VALUE4",
147 "ETM_DATA_COMPARATOR_VALUE5",
148 "ETM_DATA_COMPARATOR_VALUE6",
149 "ETM_DATA_COMPARATOR_VALUE7",
150 "ETM_DATA_COMPARATOR_VALUE8",
151 "ETM_DATA_COMPARATOR_VALUE9",
152 "ETM_DATA_COMPARATOR_VALUE10",
153 "ETM_DATA_COMPARATOR_VALUE11",
154 "ETM_DATA_COMPARATOR_VALUE12",
155 "ETM_DATA_COMPARATOR_VALUE13",
156 "ETM_DATA_COMPARATOR_VALUE14",
157 "ETM_DATA_COMPARATOR_VALUE15",
158 "ETM_DATA_COMPARATOR_VALUE16",
159 "ETM_DATA_COMPARATOR_MASK1",
160 "ETM_DATA_COMPARATOR_MASK2",
161 "ETM_DATA_COMPARATOR_MASK3",
162 "ETM_DATA_COMPARATOR_MASK4",
163 "ETM_DATA_COMPARATOR_MASK5",
164 "ETM_DATA_COMPARATOR_MASK6",
165 "ETM_DATA_COMPARATOR_MASK7",
166 "ETM_DATA_COMPARATOR_MASK8",
167 "ETM_DATA_COMPARATOR_MASK9",
168 "ETM_DATA_COMPARATOR_MASK10",
169 "ETM_DATA_COMPARATOR_MASK11",
170 "ETM_DATA_COMPARATOR_MASK12",
171 "ETM_DATA_COMPARATOR_MASK13",
172 "ETM_DATA_COMPARATOR_MASK14",
173 "ETM_DATA_COMPARATOR_MASK15",
174 "ETM_DATA_COMPARATOR_MASK16",
175 "ETM_COUNTER_INITAL_VALUE1",
176 "ETM_COUNTER_INITAL_VALUE2",
177 "ETM_COUNTER_INITAL_VALUE3",
178 "ETM_COUNTER_INITAL_VALUE4",
179 "ETM_COUNTER_ENABLE1",
180 "ETM_COUNTER_ENABLE2",
181 "ETM_COUNTER_ENABLE3",
182 "ETM_COUNTER_ENABLE4",
183 "ETM_COUNTER_RELOAD_VALUE1",
184 "ETM_COUNTER_RELOAD_VALUE2",
185 "ETM_COUNTER_RELOAD_VALUE3",
186 "ETM_COUNTER_RELOAD_VALUE4",
187 "ETM_COUNTER_VALUE1",
188 "ETM_COUNTER_VALUE2",
189 "ETM_COUNTER_VALUE3",
190 "ETM_COUNTER_VALUE4",
191 "ETM_SEQUENCER_CTRL1",
192 "ETM_SEQUENCER_CTRL2",
193 "ETM_SEQUENCER_CTRL3",
194 "ETM_SEQUENCER_CTRL4",
195 "ETM_SEQUENCER_CTRL5",
196 "ETM_SEQUENCER_CTRL6",
197 "ETM_SEQUENCER_STATE",
198 "ETM_EXTERNAL_OUTPUT1",
199 "ETM_EXTERNAL_OUTPUT2",
200 "ETM_EXTERNAL_OUTPUT3",
201 "ETM_EXTERNAL_OUTPUT4",
202 "ETM_CONTEXTID_COMPARATOR_VALUE1",
203 "ETM_CONTEXTID_COMPARATOR_VALUE2",
204 "ETM_CONTEXTID_COMPARATOR_VALUE3",
205 "ETM_CONTEXTID_COMPARATOR_MASK"
208 int etm_reg_arch_type
= -1;
210 int etm_get_reg(reg_t
*reg
);
211 int etm_set_reg(reg_t
*reg
, u32 value
);
212 int etm_set_reg_w_exec(reg_t
*reg
, u8
*buf
);
214 int etm_write_reg(reg_t
*reg
, u32 value
);
215 int etm_read_reg(reg_t
*reg
);
217 command_t
*etm_cmd
= NULL
;
219 reg_cache_t
* etm_build_reg_cache(target_t
*target
, arm_jtag_t
*jtag_info
, etm_context_t
*etm_ctx
)
221 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
222 reg_t
*reg_list
= NULL
;
223 etm_reg_t
*arch_info
= NULL
;
224 int num_regs
= sizeof(etm_reg_arch_info
)/sizeof(int);
228 /* register a register arch-type for etm registers only once */
229 if (etm_reg_arch_type
== -1)
230 etm_reg_arch_type
= register_reg_arch_type(etm_get_reg
, etm_set_reg_w_exec
);
232 /* the actual registers are kept in two arrays */
233 reg_list
= calloc(num_regs
, sizeof(reg_t
));
234 arch_info
= calloc(num_regs
, sizeof(etm_reg_t
));
236 /* fill in values for the reg cache */
237 reg_cache
->name
= "etm registers";
238 reg_cache
->next
= NULL
;
239 reg_cache
->reg_list
= reg_list
;
240 reg_cache
->num_regs
= num_regs
;
242 /* set up registers */
243 for (i
= 0; i
< num_regs
; i
++)
245 reg_list
[i
].name
= etm_reg_list
[i
];
246 reg_list
[i
].size
= 32;
247 reg_list
[i
].dirty
= 0;
248 reg_list
[i
].valid
= 0;
249 reg_list
[i
].bitfield_desc
= NULL
;
250 reg_list
[i
].num_bitfields
= 0;
251 reg_list
[i
].value
= calloc(1, 4);
252 reg_list
[i
].arch_info
= &arch_info
[i
];
253 reg_list
[i
].arch_type
= etm_reg_arch_type
;
254 reg_list
[i
].size
= etm_reg_arch_size_info
[i
];
255 arch_info
[i
].addr
= etm_reg_arch_info
[i
];
256 arch_info
[i
].jtag_info
= jtag_info
;
259 /* initialize some ETM control register settings */
260 etm_get_reg(®_list
[ETM_CTRL
]);
261 etm_ctrl_value
= buf_get_u32(reg_list
[ETM_CTRL
].value
, 0, reg_list
[ETM_CTRL
].size
);
263 /* clear the ETM powerdown bit (0) */
264 etm_ctrl_value
&= ~0x1;
266 /* configure port width (6:4), mode (17:16) and clocking (13) */
267 etm_ctrl_value
= (etm_ctrl_value
&
268 ~ETM_PORT_WIDTH_MASK
& ~ETM_PORT_MODE_MASK
& ~ETM_PORT_CLOCK_MASK
)
271 buf_set_u32(reg_list
[ETM_CTRL
].value
, 0, reg_list
[ETM_CTRL
].size
, etm_ctrl_value
);
272 etm_store_reg(®_list
[ETM_CTRL
]);
274 /* the ETM might have an ETB connected */
275 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0)
277 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
281 ERROR("etb selected as etm capture driver, but no ETB configured");
285 reg_cache
->next
= etb_build_reg_cache(etb
);
287 etb
->reg_cache
= reg_cache
->next
;
290 if (etm_ctx
->capture_driver
->init(etm_ctx
) != ERROR_OK
)
292 ERROR("ETM capture driver initialization failed");
299 int etm_get_reg(reg_t
*reg
)
301 if (etm_read_reg(reg
) != ERROR_OK
)
303 ERROR("BUG: error scheduling etm register read");
307 if (jtag_execute_queue() != ERROR_OK
)
309 ERROR("register read failed");
315 int etm_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
317 etm_reg_t
*etm_reg
= reg
->arch_info
;
318 u8 reg_addr
= etm_reg
->addr
& 0x7f;
319 scan_field_t fields
[3];
321 DEBUG("%i", etm_reg
->addr
);
323 jtag_add_end_state(TAP_RTI
);
324 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
325 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
327 fields
[0].device
= etm_reg
->jtag_info
->chain_pos
;
328 fields
[0].num_bits
= 32;
329 fields
[0].out_value
= reg
->value
;
330 fields
[0].out_mask
= NULL
;
331 fields
[0].in_value
= NULL
;
332 fields
[0].in_check_value
= NULL
;
333 fields
[0].in_check_mask
= NULL
;
334 fields
[0].in_handler
= NULL
;
335 fields
[0].in_handler_priv
= NULL
;
337 fields
[1].device
= etm_reg
->jtag_info
->chain_pos
;
338 fields
[1].num_bits
= 7;
339 fields
[1].out_value
= malloc(1);
340 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
341 fields
[1].out_mask
= NULL
;
342 fields
[1].in_value
= NULL
;
343 fields
[1].in_check_value
= NULL
;
344 fields
[1].in_check_mask
= NULL
;
345 fields
[1].in_handler
= NULL
;
346 fields
[1].in_handler_priv
= NULL
;
348 fields
[2].device
= etm_reg
->jtag_info
->chain_pos
;
349 fields
[2].num_bits
= 1;
350 fields
[2].out_value
= malloc(1);
351 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
352 fields
[2].out_mask
= NULL
;
353 fields
[2].in_value
= NULL
;
354 fields
[2].in_check_value
= NULL
;
355 fields
[2].in_check_mask
= NULL
;
356 fields
[2].in_handler
= NULL
;
357 fields
[2].in_handler_priv
= NULL
;
359 jtag_add_dr_scan(3, fields
, -1, NULL
);
361 fields
[0].in_value
= reg
->value
;
362 fields
[0].in_check_value
= check_value
;
363 fields
[0].in_check_mask
= check_mask
;
365 jtag_add_dr_scan(3, fields
, -1, NULL
);
367 free(fields
[1].out_value
);
368 free(fields
[2].out_value
);
373 int etm_read_reg(reg_t
*reg
)
375 return etm_read_reg_w_check(reg
, NULL
, NULL
);
378 int etm_set_reg(reg_t
*reg
, u32 value
)
380 if (etm_write_reg(reg
, value
) != ERROR_OK
)
382 ERROR("BUG: error scheduling etm register write");
386 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
393 int etm_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
395 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
397 if (jtag_execute_queue() != ERROR_OK
)
399 ERROR("register write failed");
405 int etm_write_reg(reg_t
*reg
, u32 value
)
407 etm_reg_t
*etm_reg
= reg
->arch_info
;
408 u8 reg_addr
= etm_reg
->addr
& 0x7f;
409 scan_field_t fields
[3];
411 DEBUG("%i: 0x%8.8x", etm_reg
->addr
, value
);
413 jtag_add_end_state(TAP_RTI
);
414 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
415 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
417 fields
[0].device
= etm_reg
->jtag_info
->chain_pos
;
418 fields
[0].num_bits
= 32;
419 fields
[0].out_value
= malloc(4);
420 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
421 fields
[0].out_mask
= NULL
;
422 fields
[0].in_value
= NULL
;
423 fields
[0].in_check_value
= NULL
;
424 fields
[0].in_check_mask
= NULL
;
425 fields
[0].in_handler
= NULL
;
426 fields
[0].in_handler_priv
= NULL
;
428 fields
[1].device
= etm_reg
->jtag_info
->chain_pos
;
429 fields
[1].num_bits
= 7;
430 fields
[1].out_value
= malloc(1);
431 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
432 fields
[1].out_mask
= NULL
;
433 fields
[1].in_value
= NULL
;
434 fields
[1].in_check_value
= NULL
;
435 fields
[1].in_check_mask
= NULL
;
436 fields
[1].in_handler
= NULL
;
437 fields
[1].in_handler_priv
= NULL
;
439 fields
[2].device
= etm_reg
->jtag_info
->chain_pos
;
440 fields
[2].num_bits
= 1;
441 fields
[2].out_value
= malloc(1);
442 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
443 fields
[2].out_mask
= NULL
;
444 fields
[2].in_value
= NULL
;
445 fields
[2].in_check_value
= NULL
;
446 fields
[2].in_check_mask
= NULL
;
447 fields
[2].in_handler
= NULL
;
448 fields
[2].in_handler_priv
= NULL
;
450 jtag_add_dr_scan(3, fields
, -1, NULL
);
452 free(fields
[0].out_value
);
453 free(fields
[1].out_value
);
454 free(fields
[2].out_value
);
459 int etm_store_reg(reg_t
*reg
)
461 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
464 /* ETM trace analysis functionality
467 extern etm_capture_driver_t etb_capture_driver
;
468 extern etm_capture_driver_t etm_dummy_capture_driver
;
469 #if BUILD_OOCD_TRACE == 1
470 extern etm_capture_driver_t oocd_trace_capture_driver
;
473 etm_capture_driver_t
*etm_capture_drivers
[] =
476 &etm_dummy_capture_driver
,
477 #if BUILD_OOCD_TRACE == 1
478 &oocd_trace_capture_driver
,
483 char *etmv1v1_branch_reason_strings
[] =
487 "trace restarted after overflow",
489 "periodic synchronization",
495 int etm_read_instruction(etm_context_t
*ctx
, arm_instruction_t
*instruction
)
504 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
506 /* search for the section the current instruction belongs to */
507 for (i
= 0; i
< ctx
->image
->num_sections
; i
++)
509 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
510 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
> ctx
->current_pc
))
519 /* current instruction couldn't be found in the image */
520 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
523 if (ctx
->core_state
== ARMV4_5_STATE_ARM
)
526 if ((retval
= image_read_section(ctx
->image
, section
,
527 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
528 4, buf
, &size_read
)) != ERROR_OK
)
530 ERROR("error while reading instruction: %i", retval
);
531 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
533 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
534 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
536 else if (ctx
->core_state
== ARMV4_5_STATE_THUMB
)
539 if ((retval
= image_read_section(ctx
->image
, section
,
540 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
541 2, buf
, &size_read
)) != ERROR_OK
)
543 ERROR("error while reading instruction: %i", retval
);
544 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
546 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
547 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
549 else if (ctx
->core_state
== ARMV4_5_STATE_JAZELLE
)
551 ERROR("BUG: tracing of jazelle code not supported");
556 ERROR("BUG: unknown core state encountered");
563 int etmv1_next_packet(etm_context_t
*ctx
, u8
*packet
, int apo
)
565 while (ctx
->data_index
< ctx
->trace_depth
)
567 /* if the caller specified an address packet offset, skip until the
568 * we reach the n-th cycle marked with tracesync */
571 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
582 /* no tracedata output during a TD cycle
583 * or in a trigger cycle */
584 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
585 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
))
592 if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
)
594 if (ctx
->data_half
== 0)
596 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
601 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
606 else if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
608 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
613 /* on a 4-bit port, a packet will be output during two consecutive cycles */
614 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
617 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
618 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
619 ctx
->data_index
+= 2;
628 int etmv1_branch_address(etm_context_t
*ctx
)
636 /* quit analysis if less than two cycles are left in the trace
637 * because we can't extract the APO */
638 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
641 /* a BE could be output during an APO cycle, skip the current
642 * and continue with the new one */
643 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
645 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
648 /* address packet offset encoded in the next two cycles' pipestat bits */
649 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
650 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
652 /* count number of tracesync cycles between current pipe_index and data_index
653 * i.e. the number of tracesyncs that data_index already passed by
654 * to subtract them from the APO */
655 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++)
657 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
661 /* extract up to four 7-bit packets */
663 if ((retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0)) != 0)
665 ctx
->last_branch
&= ~(0x7f << shift
);
666 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
668 } while ((packet
& 0x80) && (shift
< 28));
670 /* one last packet holding 4 bits of the address, plus the branch reason code */
671 if ((shift
== 28) && (packet
& 0x80))
673 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
675 ctx
->last_branch
&= 0x0fffffff;
676 ctx
->last_branch
|= (packet
& 0x0f) << 28;
677 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
682 ctx
->last_branch_reason
= 0;
690 /* if a full address was output, we might have branched into Jazelle state */
691 if ((shift
== 32) && (packet
& 0x80))
693 ctx
->core_state
= ARMV4_5_STATE_JAZELLE
;
697 /* if we didn't branch into Jazelle state, the current processor state is
698 * encoded in bit 0 of the branch target address */
699 if (ctx
->last_branch
& 0x1)
701 ctx
->core_state
= ARMV4_5_STATE_THUMB
;
702 ctx
->last_branch
&= ~0x1;
706 ctx
->core_state
= ARMV4_5_STATE_ARM
;
707 ctx
->last_branch
&= ~0x3;
714 int etmv1_data(etm_context_t
*ctx
, int size
, u32
*data
)
720 for (j
= 0; j
< size
; j
++)
722 if ((retval
= etmv1_next_packet(ctx
, &buf
[j
], 0)) != 0)
727 ERROR("TODO: add support for 64-bit values");
729 *data
= target_buffer_get_u32(ctx
->target
, buf
);
731 *data
= target_buffer_get_u16(ctx
->target
, buf
);
738 int etmv1_analyze_trace(etm_context_t
*ctx
, struct command_context_s
*cmd_ctx
)
741 arm_instruction_t instruction
;
743 /* read the trace data if it wasn't read already */
744 if (ctx
->trace_depth
== 0)
745 ctx
->capture_driver
->read_trace(ctx
);
747 /* start at the beginning of the captured trace */
752 /* neither the PC nor the data pointer are valid */
756 while (ctx
->pipe_index
< ctx
->trace_depth
)
758 u8 pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
759 u32 next_pc
= ctx
->current_pc
;
760 u32 old_data_index
= ctx
->data_index
;
761 u32 old_data_half
= ctx
->data_half
;
762 u32 old_index
= ctx
->pipe_index
;
765 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
767 command_print(cmd_ctx
, "--- trigger ---");
770 /* if we don't have a valid pc skip until we reach an indirect branch */
771 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
))
773 if (pipestat
== STAT_IE
)
774 ctx
->last_instruction
= ctx
->pipe_index
;
779 /* any indirect branch could have interrupted instruction flow
780 * - the branch reason code could indicate a trace discontinuity
781 * - a branch to the exception vectors indicates an exception
783 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
))
785 /* backup current data index, to be able to consume the branch address
786 * before examining data address and values
788 old_data_index
= ctx
->data_index
;
789 old_data_half
= ctx
->data_half
;
791 if ((retval
= etmv1_branch_address(ctx
)) != 0)
793 /* negative return value from etmv1_branch_address means we ran out of packets,
794 * quit analysing the trace */
798 /* a positive return values means the current branch was abandoned,
799 * and a new branch was encountered in cycle ctx->pipe_index + retval;
801 WARNING("abandoned branch encountered, correctnes of analysis uncertain");
802 ctx
->pipe_index
+= retval
;
806 /* skip over APO cycles */
807 ctx
->pipe_index
+= 2;
809 switch (ctx
->last_branch_reason
)
811 case 0x0: /* normal PC change */
812 next_pc
= ctx
->last_branch
;
813 ctx
->last_instruction
= old_index
;
815 case 0x1: /* tracing enabled */
816 command_print(cmd_ctx
, "--- tracing enabled at 0x%8.8x ---", ctx
->last_branch
);
817 ctx
->current_pc
= ctx
->last_branch
;
819 ctx
->last_instruction
= old_index
;
822 case 0x2: /* trace restarted after FIFO overflow */
823 command_print(cmd_ctx
, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx
->last_branch
);
824 ctx
->current_pc
= ctx
->last_branch
;
826 ctx
->last_instruction
= old_index
;
829 case 0x3: /* exit from debug state */
830 command_print(cmd_ctx
, "--- exit from debug state at 0x%8.8x ---", ctx
->last_branch
);
831 ctx
->current_pc
= ctx
->last_branch
;
833 ctx
->last_instruction
= old_index
;
836 case 0x4: /* periodic synchronization point */
837 next_pc
= ctx
->last_branch
;
838 ctx
->last_instruction
= old_index
;
840 default: /* reserved */
841 ERROR("BUG: branch reason code 0x%x is reserved", ctx
->last_branch_reason
);
846 /* if we got here the branch was a normal PC change
847 * (or a periodic synchronization point, which means the same for that matter)
848 * if we didn't accquire a complete PC continue with the next cycle
853 /* indirect branch to the exception vector means an exception occured */
854 if (((ctx
->last_branch
>= 0x0) && (ctx
->last_branch
<= 0x20))
855 || ((ctx
->last_branch
>= 0xffff0000) && (ctx
->last_branch
<= 0xffff0020)))
857 ctx
->last_instruction
= old_index
;
859 if ((ctx
->last_branch
& 0xff) == 0x10)
861 command_print(cmd_ctx
, "data abort");
865 command_print(cmd_ctx
, "exception vector 0x%2.2x", ctx
->last_branch
);
866 ctx
->current_pc
= ctx
->last_branch
;
873 /* an instruction was executed (or not, depending on the condition flags)
874 * retrieve it from the image for displaying */
875 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
876 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
877 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4))))
879 if ((retval
= etm_read_instruction(ctx
, &instruction
)) != ERROR_OK
)
881 /* can't continue tracing with no image available */
882 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
886 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
888 /* TODO: handle incomplete images */
892 cycles
= old_index
- ctx
->last_instruction
;
893 ctx
->last_instruction
= old_index
;
896 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
))
898 u32 new_data_index
= ctx
->data_index
;
899 u32 new_data_half
= ctx
->data_half
;
901 /* in case of a branch with data, the branch target address was consumed before
902 * we temporarily go back to the saved data index */
903 if (pipestat
== STAT_BD
)
905 ctx
->data_index
= old_data_index
;
906 ctx
->data_half
= old_data_half
;
909 if (ctx
->tracemode
& ETMV1_TRACE_ADDR
)
915 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
917 ctx
->last_ptr
&= ~(0x7f << shift
);
918 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
920 } while ((packet
& 0x80) && (shift
< 32));
927 command_print(cmd_ctx
, "address: 0x%8.8x", ctx
->last_ptr
);
931 if (ctx
->tracemode
& ETMV1_TRACE_DATA
)
933 if ((instruction
.type
== ARM_LDM
) || (instruction
.type
== ARM_STM
))
936 for (i
= 0; i
< 16; i
++)
938 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
941 if (etmv1_data(ctx
, 4, &data
) != 0)
943 command_print(cmd_ctx
, "data: 0x%8.8x", data
);
947 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_STRH
))
950 if (etmv1_data(ctx
, arm_access_size(&instruction
), &data
) != 0)
952 command_print(cmd_ctx
, "data: 0x%8.8x", data
);
956 /* restore data index after consuming BD address and data */
957 if (pipestat
== STAT_BD
)
959 ctx
->data_index
= new_data_index
;
960 ctx
->data_half
= new_data_half
;
965 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
967 if (((instruction
.type
== ARM_B
) ||
968 (instruction
.type
== ARM_BL
) ||
969 (instruction
.type
== ARM_BLX
)) &&
970 (instruction
.info
.b_bl_bx_blx
.target_address
!= -1))
972 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
976 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
979 else if (pipestat
== STAT_IN
)
981 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
984 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
))
986 char cycles_text
[32] = "";
988 /* if the trace was captured with cycle accurate tracing enabled,
989 * output the number of cycles since the last executed instruction
991 if (ctx
->tracemode
& ETMV1_CYCLE_ACCURATE
)
993 snprintf(cycles_text
, 32, " (%i %s)",
995 (cycles
== 1) ? "cycle" : "cycles");
998 command_print(cmd_ctx
, "%s%s%s",
1000 (pipestat
== STAT_IN
) ? " (not executed)" : "",
1003 ctx
->current_pc
= next_pc
;
1005 /* packets for an instruction don't start on or before the preceding
1006 * functional pipestat (i.e. other than WT or TD)
1008 if (ctx
->data_index
<= ctx
->pipe_index
)
1010 ctx
->data_index
= ctx
->pipe_index
+ 1;
1015 ctx
->pipe_index
+= 1;
1021 int handle_etm_tracemode_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1024 armv4_5_common_t
*armv4_5
;
1025 arm7_9_common_t
*arm7_9
;
1026 etmv1_tracemode_t tracemode
;
1028 target
= get_current_target(cmd_ctx
);
1030 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1032 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1036 if (!arm7_9
->etm_ctx
)
1038 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1042 tracemode
= arm7_9
->etm_ctx
->tracemode
;
1046 if (strcmp(args
[0], "none") == 0)
1048 tracemode
= ETMV1_TRACE_NONE
;
1050 else if (strcmp(args
[0], "data") == 0)
1052 tracemode
= ETMV1_TRACE_DATA
;
1054 else if (strcmp(args
[0], "address") == 0)
1056 tracemode
= ETMV1_TRACE_ADDR
;
1058 else if (strcmp(args
[0], "all") == 0)
1060 tracemode
= ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
;
1064 command_print(cmd_ctx
, "invalid option '%s'", args
[0]);
1068 switch (strtol(args
[1], NULL
, 0))
1071 tracemode
|= ETMV1_CONTEXTID_NONE
;
1074 tracemode
|= ETMV1_CONTEXTID_8
;
1077 tracemode
|= ETMV1_CONTEXTID_16
;
1080 tracemode
|= ETMV1_CONTEXTID_32
;
1083 command_print(cmd_ctx
, "invalid option '%s'", args
[1]);
1087 if (strcmp(args
[2], "enable") == 0)
1089 tracemode
|= ETMV1_CYCLE_ACCURATE
;
1091 else if (strcmp(args
[2], "disable") == 0)
1097 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1101 if (strcmp(args
[3], "enable") == 0)
1103 tracemode
|= ETMV1_BRANCH_OUTPUT
;
1105 else if (strcmp(args
[3], "disable") == 0)
1111 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1117 command_print(cmd_ctx
, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
1121 command_print(cmd_ctx
, "current tracemode configuration:");
1123 switch (tracemode
& ETMV1_TRACE_MASK
)
1125 case ETMV1_TRACE_NONE
:
1126 command_print(cmd_ctx
, "data tracing: none");
1128 case ETMV1_TRACE_DATA
:
1129 command_print(cmd_ctx
, "data tracing: data only");
1131 case ETMV1_TRACE_ADDR
:
1132 command_print(cmd_ctx
, "data tracing: address only");
1134 case ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
:
1135 command_print(cmd_ctx
, "data tracing: address and data");
1139 switch (tracemode
& ETMV1_CONTEXTID_MASK
)
1141 case ETMV1_CONTEXTID_NONE
:
1142 command_print(cmd_ctx
, "contextid tracing: none");
1144 case ETMV1_CONTEXTID_8
:
1145 command_print(cmd_ctx
, "contextid tracing: 8 bit");
1147 case ETMV1_CONTEXTID_16
:
1148 command_print(cmd_ctx
, "contextid tracing: 16 bit");
1150 case ETMV1_CONTEXTID_32
:
1151 command_print(cmd_ctx
, "contextid tracing: 32 bit");
1155 if (tracemode
& ETMV1_CYCLE_ACCURATE
)
1157 command_print(cmd_ctx
, "cycle-accurate tracing enabled");
1161 command_print(cmd_ctx
, "cycle-accurate tracing disabled");
1164 if (tracemode
& ETMV1_BRANCH_OUTPUT
)
1166 command_print(cmd_ctx
, "full branch address output enabled");
1170 command_print(cmd_ctx
, "full branch address output disabled");
1173 /* only update ETM_CTRL register if tracemode changed */
1174 if (arm7_9
->etm_ctx
->tracemode
!= tracemode
)
1176 reg_t
*etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1178 etm_get_reg(etm_ctrl_reg
);
1180 buf_set_u32(etm_ctrl_reg
->value
, 2, 2, tracemode
& ETMV1_TRACE_MASK
);
1181 buf_set_u32(etm_ctrl_reg
->value
, 14, 2, (tracemode
& ETMV1_CONTEXTID_MASK
) >> 4);
1182 buf_set_u32(etm_ctrl_reg
->value
, 12, 1, (tracemode
& ETMV1_CYCLE_ACCURATE
) >> 8);
1183 buf_set_u32(etm_ctrl_reg
->value
, 8, 1, (tracemode
& ETMV1_BRANCH_OUTPUT
) >> 9);
1184 etm_store_reg(etm_ctrl_reg
);
1186 arm7_9
->etm_ctx
->tracemode
= tracemode
;
1188 /* invalidate old trace data */
1189 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1190 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1192 free(arm7_9
->etm_ctx
->trace_data
);
1194 arm7_9
->etm_ctx
->trace_depth
= 0;
1200 int handle_etm_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1203 armv4_5_common_t
*armv4_5
;
1204 arm7_9_common_t
*arm7_9
;
1205 etm_portmode_t portmode
= 0x0;
1206 etm_context_t
*etm_ctx
= malloc(sizeof(etm_context_t
));
1211 ERROR("incomplete 'etm config <target> <port_width> <port_mode> <clocking> <capture_driver>' command");
1215 target
= get_target_by_num(strtoul(args
[0], NULL
, 0));
1219 ERROR("target number '%s' not defined", args
[0]);
1223 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1225 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1229 switch (strtoul(args
[1], NULL
, 0))
1232 portmode
|= ETM_PORT_4BIT
;
1235 portmode
|= ETM_PORT_8BIT
;
1238 portmode
|= ETM_PORT_16BIT
;
1241 command_print(cmd_ctx
, "unsupported ETM port width '%s', must be 4, 8 or 16", args
[1]);
1245 if (strcmp("normal", args
[2]) == 0)
1247 portmode
|= ETM_PORT_NORMAL
;
1249 else if (strcmp("multiplexed", args
[2]) == 0)
1251 portmode
|= ETM_PORT_MUXED
;
1253 else if (strcmp("demultiplexed", args
[2]) == 0)
1255 portmode
|= ETM_PORT_DEMUXED
;
1259 command_print(cmd_ctx
, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args
[2]);
1263 if (strcmp("half", args
[3]) == 0)
1265 portmode
|= ETM_PORT_HALF_CLOCK
;
1267 else if (strcmp("full", args
[3]) == 0)
1269 portmode
|= ETM_PORT_FULL_CLOCK
;
1273 command_print(cmd_ctx
, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args
[3]);
1277 for (i
=0; etm_capture_drivers
[i
]; i
++)
1279 if (strcmp(args
[4], etm_capture_drivers
[i
]->name
) == 0)
1281 if (etm_capture_drivers
[i
]->register_commands(cmd_ctx
) != ERROR_OK
)
1287 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1293 if (!etm_capture_drivers
[i
])
1295 /* no supported capture driver found, don't register an ETM */
1297 ERROR("trace capture driver '%s' not found", args
[4]);
1301 etm_ctx
->target
= target
;
1302 etm_ctx
->trigger_percent
= 50;
1303 etm_ctx
->trace_data
= NULL
;
1304 etm_ctx
->trace_depth
= 0;
1305 etm_ctx
->portmode
= portmode
;
1306 etm_ctx
->tracemode
= 0x0;
1307 etm_ctx
->core_state
= ARMV4_5_STATE_ARM
;
1308 etm_ctx
->image
= NULL
;
1309 etm_ctx
->pipe_index
= 0;
1310 etm_ctx
->data_index
= 0;
1311 etm_ctx
->current_pc
= 0x0;
1313 etm_ctx
->last_branch
= 0x0;
1314 etm_ctx
->last_branch_reason
= 0x0;
1315 etm_ctx
->last_ptr
= 0x0;
1316 etm_ctx
->ptr_ok
= 0x0;
1317 etm_ctx
->context_id
= 0x0;
1318 etm_ctx
->last_instruction
= 0;
1320 arm7_9
->etm_ctx
= etm_ctx
;
1322 etm_register_user_commands(cmd_ctx
);
1327 int handle_etm_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1330 armv4_5_common_t
*armv4_5
;
1331 arm7_9_common_t
*arm7_9
;
1332 reg_t
*etm_config_reg
;
1333 reg_t
*etm_sys_config_reg
;
1337 target
= get_current_target(cmd_ctx
);
1339 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1341 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1345 if (!arm7_9
->etm_ctx
)
1347 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1351 etm_config_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CONFIG
];
1352 etm_sys_config_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_SYS_CONFIG
];
1354 etm_get_reg(etm_config_reg
);
1355 command_print(cmd_ctx
, "pairs of address comparators: %i", buf_get_u32(etm_config_reg
->value
, 0, 4));
1356 command_print(cmd_ctx
, "pairs of data comparators: %i", buf_get_u32(etm_config_reg
->value
, 4, 4));
1357 command_print(cmd_ctx
, "memory map decoders: %i", buf_get_u32(etm_config_reg
->value
, 8, 4));
1358 command_print(cmd_ctx
, "number of counters: %i", buf_get_u32(etm_config_reg
->value
, 12, 4));
1359 command_print(cmd_ctx
, "sequencer %spresent",
1360 (buf_get_u32(etm_config_reg
->value
, 16, 1) == 1) ? "" : "not ");
1361 command_print(cmd_ctx
, "number of ext. inputs: %i", buf_get_u32(etm_config_reg
->value
, 17, 3));
1362 command_print(cmd_ctx
, "number of ext. outputs: %i", buf_get_u32(etm_config_reg
->value
, 20, 3));
1363 command_print(cmd_ctx
, "FIFO full %spresent",
1364 (buf_get_u32(etm_config_reg
->value
, 23, 1) == 1) ? "" : "not ");
1365 command_print(cmd_ctx
, "protocol version: %i", buf_get_u32(etm_config_reg
->value
, 28, 3));
1367 etm_get_reg(etm_sys_config_reg
);
1369 switch (buf_get_u32(etm_sys_config_reg
->value
, 0, 3))
1381 command_print(cmd_ctx
, "max. port size: %i", max_port_size
);
1383 command_print(cmd_ctx
, "half-rate clocking %ssupported",
1384 (buf_get_u32(etm_sys_config_reg
->value
, 3, 1) == 1) ? "" : "not ");
1385 command_print(cmd_ctx
, "full-rate clocking %ssupported",
1386 (buf_get_u32(etm_sys_config_reg
->value
, 4, 1) == 1) ? "" : "not ");
1387 command_print(cmd_ctx
, "normal trace format %ssupported",
1388 (buf_get_u32(etm_sys_config_reg
->value
, 5, 1) == 1) ? "" : "not ");
1389 command_print(cmd_ctx
, "multiplex trace format %ssupported",
1390 (buf_get_u32(etm_sys_config_reg
->value
, 6, 1) == 1) ? "" : "not ");
1391 command_print(cmd_ctx
, "demultiplex trace format %ssupported",
1392 (buf_get_u32(etm_sys_config_reg
->value
, 7, 1) == 1) ? "" : "not ");
1393 command_print(cmd_ctx
, "FIFO full %ssupported",
1394 (buf_get_u32(etm_sys_config_reg
->value
, 8, 1) == 1) ? "" : "not ");
1399 int handle_etm_status_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1402 armv4_5_common_t
*armv4_5
;
1403 arm7_9_common_t
*arm7_9
;
1404 trace_status_t trace_status
;
1406 target
= get_current_target(cmd_ctx
);
1408 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1410 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1414 if (!arm7_9
->etm_ctx
)
1416 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1420 trace_status
= arm7_9
->etm_ctx
->capture_driver
->status(arm7_9
->etm_ctx
);
1422 if (trace_status
== TRACE_IDLE
)
1424 command_print(cmd_ctx
, "tracing is idle");
1428 static char *completed
= " completed";
1429 static char *running
= " is running";
1430 static char *overflowed
= ", trace overflowed";
1431 static char *triggered
= ", trace triggered";
1433 command_print(cmd_ctx
, "trace collection%s%s%s",
1434 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1435 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1436 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1438 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1440 command_print(cmd_ctx
, "%i frames of trace data read", arm7_9
->etm_ctx
->trace_depth
);
1447 int handle_etm_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1450 armv4_5_common_t
*armv4_5
;
1451 arm7_9_common_t
*arm7_9
;
1452 etm_context_t
*etm_ctx
;
1456 command_print(cmd_ctx
, "usage: etm image <file> [base address] [type]");
1460 target
= get_current_target(cmd_ctx
);
1462 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1464 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1468 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1470 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1476 image_close(etm_ctx
->image
);
1477 free(etm_ctx
->image
);
1478 command_print(cmd_ctx
, "previously loaded image found and closed");
1481 etm_ctx
->image
= malloc(sizeof(image_t
));
1482 etm_ctx
->image
->base_address_set
= 0;
1483 etm_ctx
->image
->start_address_set
= 0;
1485 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1488 etm_ctx
->image
->base_address_set
= 1;
1489 etm_ctx
->image
->base_address
= strtoul(args
[1], NULL
, 0);
1493 etm_ctx
->image
->base_address_set
= 0;
1496 if (image_open(etm_ctx
->image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
1498 command_print(cmd_ctx
, "image opening error: %s", etm_ctx
->image
->error_str
);
1499 free(etm_ctx
->image
);
1500 etm_ctx
->image
= NULL
;
1507 int handle_etm_dump_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1511 armv4_5_common_t
*armv4_5
;
1512 arm7_9_common_t
*arm7_9
;
1513 etm_context_t
*etm_ctx
;
1518 command_print(cmd_ctx
, "usage: etm dump <file>");
1522 target
= get_current_target(cmd_ctx
);
1524 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1526 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1530 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1532 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1536 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
)
1538 command_print(cmd_ctx
, "trace capture wasn't enabled, no trace data captured");
1542 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1544 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1545 command_print(cmd_ctx
, "trace capture not completed");
1549 /* read the trace data if it wasn't read already */
1550 if (etm_ctx
->trace_depth
== 0)
1551 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1553 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1555 command_print(cmd_ctx
, "file open error: %s", file
.error_str
);
1559 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1560 fileio_write_u32(&file
, etm_ctx
->portmode
);
1561 fileio_write_u32(&file
, etm_ctx
->tracemode
);
1562 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1564 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1566 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1567 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1568 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1571 fileio_close(&file
);
1576 int handle_etm_load_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1580 armv4_5_common_t
*armv4_5
;
1581 arm7_9_common_t
*arm7_9
;
1582 etm_context_t
*etm_ctx
;
1587 command_print(cmd_ctx
, "usage: etm load <file>");
1591 target
= get_current_target(cmd_ctx
);
1593 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1595 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1599 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1601 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1605 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1607 command_print(cmd_ctx
, "trace capture running, stop first");
1611 if (fileio_open(&file
, args
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1613 command_print(cmd_ctx
, "file open error: %s", file
.error_str
);
1619 command_print(cmd_ctx
, "size isn't a multiple of 4, no valid trace data");
1623 if (etm_ctx
->trace_depth
> 0)
1625 free(etm_ctx
->trace_data
);
1628 fileio_read_u32(&file
, &etm_ctx
->capture_status
);
1629 fileio_read_u32(&file
, &etm_ctx
->portmode
);
1630 fileio_read_u32(&file
, &etm_ctx
->tracemode
);
1631 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1633 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
1635 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1637 u32 pipestat
, packet
, flags
;
1638 fileio_read_u32(&file
, &pipestat
);
1639 fileio_read_u32(&file
, &packet
);
1640 fileio_read_u32(&file
, &flags
);
1641 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1642 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1643 etm_ctx
->trace_data
[i
].flags
= flags
;
1646 fileio_close(&file
);
1651 int handle_etm_trigger_percent_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1654 armv4_5_common_t
*armv4_5
;
1655 arm7_9_common_t
*arm7_9
;
1656 etm_context_t
*etm_ctx
;
1658 target
= get_current_target(cmd_ctx
);
1660 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1662 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1666 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1668 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1674 u32 new_value
= strtoul(args
[0], NULL
, 0);
1676 if ((new_value
< 2) || (new_value
> 100))
1678 command_print(cmd_ctx
, "valid settings are 2% to 100%");
1682 etm_ctx
->trigger_percent
= new_value
;
1686 command_print(cmd_ctx
, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx
->trigger_percent
);
1691 int handle_etm_start_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1694 armv4_5_common_t
*armv4_5
;
1695 arm7_9_common_t
*arm7_9
;
1696 etm_context_t
*etm_ctx
;
1697 reg_t
*etm_ctrl_reg
;
1699 target
= get_current_target(cmd_ctx
);
1701 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1703 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1707 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1709 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1713 /* invalidate old tracing data */
1714 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1715 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1717 free(arm7_9
->etm_ctx
->trace_data
);
1719 arm7_9
->etm_ctx
->trace_depth
= 0;
1721 etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1722 etm_get_reg(etm_ctrl_reg
);
1724 /* Clear programming bit (10), set port selection bit (11) */
1725 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1727 etm_store_reg(etm_ctrl_reg
);
1728 jtag_execute_queue();
1730 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1735 int handle_etm_stop_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1738 armv4_5_common_t
*armv4_5
;
1739 arm7_9_common_t
*arm7_9
;
1740 etm_context_t
*etm_ctx
;
1741 reg_t
*etm_ctrl_reg
;
1743 target
= get_current_target(cmd_ctx
);
1745 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1747 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1751 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1753 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1757 etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1758 etm_get_reg(etm_ctrl_reg
);
1760 /* Set programming bit (10), clear port selection bit (11) */
1761 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
1763 etm_store_reg(etm_ctrl_reg
);
1764 jtag_execute_queue();
1766 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
1771 int handle_etm_analyze_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1774 armv4_5_common_t
*armv4_5
;
1775 arm7_9_common_t
*arm7_9
;
1776 etm_context_t
*etm_ctx
;
1778 target
= get_current_target(cmd_ctx
);
1780 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1782 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1786 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1788 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1792 etmv1_analyze_trace(etm_ctx
, cmd_ctx
);
1797 int etm_register_commands(struct command_context_s
*cmd_ctx
)
1799 etm_cmd
= register_command(cmd_ctx
, NULL
, "etm", NULL
, COMMAND_ANY
, "Embedded Trace Macrocell");
1801 register_command(cmd_ctx
, etm_cmd
, "config", handle_etm_config_command
, COMMAND_CONFIG
, NULL
);
1806 int etm_register_user_commands(struct command_context_s
*cmd_ctx
)
1808 register_command(cmd_ctx
, etm_cmd
, "tracemode", handle_etm_tracemode_command
,
1809 COMMAND_EXEC
, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
1811 register_command(cmd_ctx
, etm_cmd
, "info", handle_etm_info_command
,
1812 COMMAND_EXEC
, "display info about the current target's ETM");
1814 register_command(cmd_ctx
, etm_cmd
, "trigger_percent <percent>", handle_etm_trigger_percent_command
,
1815 COMMAND_EXEC
, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1816 register_command(cmd_ctx
, etm_cmd
, "status", handle_etm_status_command
,
1817 COMMAND_EXEC
, "display current target's ETM status");
1818 register_command(cmd_ctx
, etm_cmd
, "start", handle_etm_start_command
,
1819 COMMAND_EXEC
, "start ETM trace collection");
1820 register_command(cmd_ctx
, etm_cmd
, "stop", handle_etm_stop_command
,
1821 COMMAND_EXEC
, "stop ETM trace collection");
1823 register_command(cmd_ctx
, etm_cmd
, "analyze", handle_etm_analyze_command
,
1824 COMMAND_EXEC
, "anaylze collected ETM trace");
1826 register_command(cmd_ctx
, etm_cmd
, "image", handle_etm_image_command
,
1827 COMMAND_EXEC
, "load image from <file> [base address]");
1829 register_command(cmd_ctx
, etm_cmd
, "dump", handle_etm_dump_command
,
1830 COMMAND_EXEC
, "dump captured trace data <file>");
1831 register_command(cmd_ctx
, etm_cmd
, "load", handle_etm_load_command
,
1832 COMMAND_EXEC
, "load trace data for analysis <file>");
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