Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
ETM: start support for ETMv2+
[openocd.git] / src / target / etm.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "armv4_5.h"
25 #include "etb.h"
26 #include "image.h"
27 #include "arm_disassembler.h"
28
29
30 /*
31 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
32 *
33 * ETM modules collect instruction and/or data trace information, compress
34 * it, and transfer it to a debugging host through either a (buffered) trace
35 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
36 *
37 * There are several generations of these modules. Original versions have
38 * JTAG access through a dedicated scan chain. Recent versions have added
39 * access via coprocessor instructions, memory addressing, and the ARM Debug
40 * Interface v5 (ADIv5); and phased out direct JTAG access.
41 *
42 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
43 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
44 * implying non-JTAG connectivity options.
45 *
46 * Relevant documentation includes:
47 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
48 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
49 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
50 */
51
52 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
53
54 enum {
55 RO, /* read/only */
56 WO, /* write/only */
57 RW, /* read/write */
58 };
59
60 struct etm_reg_info {
61 uint8_t addr;
62 uint8_t size; /* low-N of 32 bits */
63 uint8_t mode; /* RO, WO, RW */
64 uint8_t bcd_vers; /* 1.0, 2.0, etc */
65 char *name;
66 };
67
68 /*
69 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
70 * (Or on some processors, through coprocessor operations.)
71 * Newer versions of ETM make some W/O registers R/W, and
72 * provide definitions for some previously-unused bits.
73 */
74
75 /* core registers used to version/configure the ETM */
76 static const struct etm_reg_info etm_core[] = {
77 /* NOTE: we "know" the order here ... */
78 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
79 { ETM_ID, 32, RO, 0x20, "ETM_id", },
80 };
81
82 /* basic registers that are always there given the right ETM version */
83 static const struct etm_reg_info etm_basic[] = {
84 /* ETM Trace Registers */
85 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
86 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
87 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
88 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
89 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
90
91 /* TraceEnable configuration */
92 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
93 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
94 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
95 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
96
97 /* ViewData configuration (data trace) */
98 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
99 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
100 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
101 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
102
103 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
104
105 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
106 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
107 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
108 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
109 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
110 };
111
112 static const struct etm_reg_info etm_fifofull[] = {
113 /* FIFOFULL configuration */
114 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
115 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
116 };
117
118 static const struct etm_reg_info etm_addr_comp[] = {
119 /* Address comparator register pairs */
120 #define ADDR_COMPARATOR(i) \
121 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
122 "ETM_addr_" #i "_comparator_value", }, \
123 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
124 "ETM_addr_" #i "_access_type", }
125 ADDR_COMPARATOR(1),
126 ADDR_COMPARATOR(2),
127 ADDR_COMPARATOR(3),
128 ADDR_COMPARATOR(4),
129 ADDR_COMPARATOR(5),
130 ADDR_COMPARATOR(6),
131 ADDR_COMPARATOR(7),
132 ADDR_COMPARATOR(8),
133
134 ADDR_COMPARATOR(9),
135 ADDR_COMPARATOR(10),
136 ADDR_COMPARATOR(11),
137 ADDR_COMPARATOR(12),
138 ADDR_COMPARATOR(13),
139 ADDR_COMPARATOR(14),
140 ADDR_COMPARATOR(15),
141 ADDR_COMPARATOR(16),
142 #undef ADDR_COMPARATOR
143 };
144
145 static const struct etm_reg_info etm_data_comp[] = {
146 /* Data Value Comparators (NOTE: odd addresses are reserved) */
147 #define DATA_COMPARATOR(i) \
148 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
149 "ETM_data_" #i "_comparator_value", }, \
150 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
151 "ETM_data_" #i "_comparator_mask", }
152 DATA_COMPARATOR(1),
153 DATA_COMPARATOR(2),
154 DATA_COMPARATOR(3),
155 DATA_COMPARATOR(4),
156 DATA_COMPARATOR(5),
157 DATA_COMPARATOR(6),
158 DATA_COMPARATOR(7),
159 DATA_COMPARATOR(8),
160 #undef DATA_COMPARATOR
161 };
162
163 static const struct etm_reg_info etm_counters[] = {
164 #define ETM_COUNTER(i) \
165 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
166 "ETM_counter_" #i "_reload_value", }, \
167 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
168 "ETM_counter_" #i "_enable", }, \
169 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
170 "ETM_counter_" #i "_reload_event", }, \
171 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
172 "ETM_counter_" #i "_value", }
173 ETM_COUNTER(1),
174 ETM_COUNTER(2),
175 ETM_COUNTER(3),
176 ETM_COUNTER(4),
177 #undef ETM_COUNTER
178 };
179
180 static const struct etm_reg_info etm_sequencer[] = {
181 #define ETM_SEQ(i) \
182 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
183 "ETM_sequencer_event" #i, }
184 ETM_SEQ(0), /* 1->2 */
185 ETM_SEQ(1), /* 2->1 */
186 ETM_SEQ(2), /* 2->3 */
187 ETM_SEQ(3), /* 3->1 */
188 ETM_SEQ(4), /* 3->2 */
189 ETM_SEQ(5), /* 1->3 */
190 #undef ETM_SEQ
191 /* 0x66 reserved */
192 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
193 };
194
195 static const struct etm_reg_info etm_outputs[] = {
196 #define ETM_OUTPUT(i) \
197 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
198 "ETM_external_output" #i, }
199
200 ETM_OUTPUT(1),
201 ETM_OUTPUT(2),
202 ETM_OUTPUT(3),
203 ETM_OUTPUT(4),
204 #undef ETM_OUTPUT
205 };
206
207 #if 0
208 /* registers from 0x6c..0x7f were added after ETMv1.3 */
209
210 /* Context ID Comparators */
211 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
212 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
213 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
214 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
215 #endif
216
217 static int etm_reg_arch_type = -1;
218
219 static int etm_get_reg(reg_t *reg);
220 static int etm_read_reg_w_check(reg_t *reg,
221 uint8_t* check_value, uint8_t* check_mask);
222 static int etm_register_user_commands(struct command_context_s *cmd_ctx);
223 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
224 static int etm_write_reg(reg_t *reg, uint32_t value);
225
226 static command_t *etm_cmd;
227
228
229 /* Look up register by ID ... most ETM instances only
230 * support a subset of the possible registers.
231 */
232 static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
233 {
234 reg_cache_t *cache = etm_ctx->reg_cache;
235 int i;
236
237 for (i = 0; i < cache->num_regs; i++) {
238 struct etm_reg_s *reg = cache->reg_list[i].arch_info;
239
240 if (reg->reg_info->addr == id)
241 return &cache->reg_list[i];
242 }
243
244 /* caller asking for nonexistent register is a bug! */
245 /* REVISIT say which of the N targets was involved */
246 LOG_ERROR("ETM: register 0x%02x not available", id);
247 return NULL;
248 }
249
250 static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info,
251 reg_cache_t *cache, etm_reg_t *ereg,
252 const struct etm_reg_info *r, unsigned nreg)
253 {
254 reg_t *reg = cache->reg_list;
255
256 reg += cache->num_regs;
257 ereg += cache->num_regs;
258
259 /* add up to "nreg" registers from "r", if supported by this
260 * version of the ETM, to the specified cache.
261 */
262 for (; nreg--; r++) {
263
264 /* this ETM may be too old to have some registers */
265 if (r->bcd_vers > bcd_vers)
266 continue;
267
268 reg->name = r->name;
269 reg->size = r->size;
270 reg->value = &ereg->value;
271 reg->arch_info = ereg;
272 reg->arch_type = etm_reg_arch_type;
273 reg++;
274 cache->num_regs++;
275
276 ereg->reg_info = r;
277 ereg->jtag_info = jtag_info;
278 ereg++;
279 }
280 }
281
282 reg_cache_t *etm_build_reg_cache(target_t *target,
283 arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
284 {
285 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
286 reg_t *reg_list = NULL;
287 etm_reg_t *arch_info = NULL;
288 unsigned bcd_vers, config;
289
290 /* register a register arch-type for etm registers only once */
291 if (etm_reg_arch_type == -1)
292 etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
293 etm_set_reg_w_exec);
294
295 /* the actual registers are kept in two arrays */
296 reg_list = calloc(128, sizeof(reg_t));
297 arch_info = calloc(128, sizeof(etm_reg_t));
298
299 /* fill in values for the reg cache */
300 reg_cache->name = "etm registers";
301 reg_cache->next = NULL;
302 reg_cache->reg_list = reg_list;
303 reg_cache->num_regs = 0;
304
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
307 */
308 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
309 etm_core, 1);
310
311 etm_get_reg(reg_list);
312 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
313 config = etm_ctx->config;
314
315 /* figure ETM version then add base registers */
316 if (config & (1 << 31)) {
317 bcd_vers = 0x20;
318 LOG_WARNING("ETMv2+ support is incomplete");
319
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
324 */
325 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
326 etm_core + 1, 1);
327 etm_get_reg(reg_list + 1);
328 etm_ctx->id = buf_get_u32(
329 (void *)&arch_info[1].value, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
331 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
332
333 } else {
334 switch (config >> 28) {
335 case 7:
336 case 5:
337 case 3:
338 bcd_vers = 0x13;
339 break;
340 case 4:
341 case 2:
342 bcd_vers = 0x12;
343 break;
344 case 1:
345 bcd_vers = 0x11;
346 break;
347 case 0:
348 bcd_vers = 0x10;
349 break;
350 default:
351 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
352 free(reg_cache);
353 free(reg_list);
354 free(arch_info);
355 return ERROR_OK;
356 }
357 }
358 etm_ctx->bcd_vers = bcd_vers;
359 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
360
361 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
362 etm_basic, ARRAY_SIZE(etm_basic));
363
364 /* address and data comparators; counters; outputs */
365 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
366 etm_addr_comp, 4 * (0x0f & (config >> 0)));
367 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
368 etm_data_comp, 2 * (0x0f & (config >> 4)));
369 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
370 etm_counters, 4 * (0x07 & (config >> 13)));
371 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
372 etm_outputs, (0x07 & (config >> 20)));
373
374 /* FIFOFULL presence is optional
375 * REVISIT for ETMv1.2 and later, don't bother adding this
376 * unless ETM_SYS_CONFIG says it's also *supported* ...
377 */
378 if (config & (1 << 23))
379 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
380 etm_fifofull, ARRAY_SIZE(etm_fifofull));
381
382 /* sequencer is optional (for state-dependant triggering) */
383 if (config & (1 << 16))
384 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
385 etm_sequencer, ARRAY_SIZE(etm_sequencer));
386
387 /* REVISIT could realloc and likely save half the memory
388 * in the two chunks we allocated...
389 */
390
391 /* the ETM might have an ETB connected */
392 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
393 {
394 etb_t *etb = etm_ctx->capture_driver_priv;
395
396 if (!etb)
397 {
398 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
399 free(reg_cache);
400 free(reg_list);
401 free(arch_info);
402 return ERROR_OK;
403 }
404
405 reg_cache->next = etb_build_reg_cache(etb);
406
407 etb->reg_cache = reg_cache->next;
408 }
409
410 etm_ctx->reg_cache = reg_cache;
411 return reg_cache;
412 }
413
414 static int etm_read_reg(reg_t *reg)
415 {
416 return etm_read_reg_w_check(reg, NULL, NULL);
417 }
418
419 static int etm_store_reg(reg_t *reg)
420 {
421 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
422 }
423
424 int etm_setup(target_t *target)
425 {
426 int retval;
427 uint32_t etm_ctrl_value;
428 struct arm *arm = target_to_arm(target);
429 etm_context_t *etm_ctx = arm->etm;
430 reg_t *etm_ctrl_reg;
431
432 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
433 if (!etm_ctrl_reg)
434 return ERROR_OK;
435
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg);
438 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
439
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value &= ~0x1;
442
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
445 */
446 etm_ctrl_value = (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
449 & ~ETM_PORT_CLOCK_MASK)
450 | etm_ctx->portmode;
451
452 buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
453 etm_store_reg(etm_ctrl_reg);
454
455 if ((retval = jtag_execute_queue()) != ERROR_OK)
456 return retval;
457
458 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
459 * verify that those width and mode settings are OK ...
460 */
461
462 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
463 {
464 LOG_ERROR("ETM capture driver initialization failed");
465 return retval;
466 }
467 return ERROR_OK;
468 }
469
470 static int etm_get_reg(reg_t *reg)
471 {
472 int retval;
473
474 if ((retval = etm_read_reg(reg)) != ERROR_OK)
475 {
476 LOG_ERROR("BUG: error scheduling etm register read");
477 return retval;
478 }
479
480 if ((retval = jtag_execute_queue()) != ERROR_OK)
481 {
482 LOG_ERROR("register read failed");
483 return retval;
484 }
485
486 return ERROR_OK;
487 }
488
489 static int etm_read_reg_w_check(reg_t *reg,
490 uint8_t* check_value, uint8_t* check_mask)
491 {
492 etm_reg_t *etm_reg = reg->arch_info;
493 const struct etm_reg_info *r = etm_reg->reg_info;
494 uint8_t reg_addr = r->addr & 0x7f;
495 scan_field_t fields[3];
496
497 if (etm_reg->reg_info->mode == WO) {
498 LOG_ERROR("BUG: can't read write-only register %s", r->name);
499 return ERROR_INVALID_ARGUMENTS;
500 }
501
502 LOG_DEBUG("%s (%u)", r->name, reg_addr);
503
504 jtag_set_end_state(TAP_IDLE);
505 arm_jtag_scann(etm_reg->jtag_info, 0x6);
506 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
507
508 fields[0].tap = etm_reg->jtag_info->tap;
509 fields[0].num_bits = 32;
510 fields[0].out_value = reg->value;
511 fields[0].in_value = NULL;
512 fields[0].check_value = NULL;
513 fields[0].check_mask = NULL;
514
515 fields[1].tap = etm_reg->jtag_info->tap;
516 fields[1].num_bits = 7;
517 fields[1].out_value = malloc(1);
518 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
519 fields[1].in_value = NULL;
520 fields[1].check_value = NULL;
521 fields[1].check_mask = NULL;
522
523 fields[2].tap = etm_reg->jtag_info->tap;
524 fields[2].num_bits = 1;
525 fields[2].out_value = malloc(1);
526 buf_set_u32(fields[2].out_value, 0, 1, 0);
527 fields[2].in_value = NULL;
528 fields[2].check_value = NULL;
529 fields[2].check_mask = NULL;
530
531 jtag_add_dr_scan(3, fields, jtag_get_end_state());
532
533 fields[0].in_value = reg->value;
534 fields[0].check_value = check_value;
535 fields[0].check_mask = check_mask;
536
537 jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
538
539 free(fields[1].out_value);
540 free(fields[2].out_value);
541
542 return ERROR_OK;
543 }
544
545 static int etm_set_reg(reg_t *reg, uint32_t value)
546 {
547 int retval;
548
549 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
550 {
551 LOG_ERROR("BUG: error scheduling etm register write");
552 return retval;
553 }
554
555 buf_set_u32(reg->value, 0, reg->size, value);
556 reg->valid = 1;
557 reg->dirty = 0;
558
559 return ERROR_OK;
560 }
561
562 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
563 {
564 int retval;
565
566 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
567
568 if ((retval = jtag_execute_queue()) != ERROR_OK)
569 {
570 LOG_ERROR("register write failed");
571 return retval;
572 }
573 return ERROR_OK;
574 }
575
576 static int etm_write_reg(reg_t *reg, uint32_t value)
577 {
578 etm_reg_t *etm_reg = reg->arch_info;
579 const struct etm_reg_info *r = etm_reg->reg_info;
580 uint8_t reg_addr = r->addr & 0x7f;
581 scan_field_t fields[3];
582
583 if (etm_reg->reg_info->mode == RO) {
584 LOG_ERROR("BUG: can't write read--only register %s", r->name);
585 return ERROR_INVALID_ARGUMENTS;
586 }
587
588 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
589
590 jtag_set_end_state(TAP_IDLE);
591 arm_jtag_scann(etm_reg->jtag_info, 0x6);
592 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
593
594 fields[0].tap = etm_reg->jtag_info->tap;
595 fields[0].num_bits = 32;
596 uint8_t tmp1[4];
597 fields[0].out_value = tmp1;
598 buf_set_u32(fields[0].out_value, 0, 32, value);
599 fields[0].in_value = NULL;
600
601 fields[1].tap = etm_reg->jtag_info->tap;
602 fields[1].num_bits = 7;
603 uint8_t tmp2;
604 fields[1].out_value = &tmp2;
605 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
606 fields[1].in_value = NULL;
607
608 fields[2].tap = etm_reg->jtag_info->tap;
609 fields[2].num_bits = 1;
610 uint8_t tmp3;
611 fields[2].out_value = &tmp3;
612 buf_set_u32(fields[2].out_value, 0, 1, 1);
613 fields[2].in_value = NULL;
614
615 jtag_add_dr_scan(3, fields, jtag_get_end_state());
616
617 return ERROR_OK;
618 }
619
620
621 /* ETM trace analysis functionality
622 *
623 */
624 extern etm_capture_driver_t etm_dummy_capture_driver;
625 #if BUILD_OOCD_TRACE == 1
626 extern etm_capture_driver_t oocd_trace_capture_driver;
627 #endif
628
629 static etm_capture_driver_t *etm_capture_drivers[] =
630 {
631 &etb_capture_driver,
632 &etm_dummy_capture_driver,
633 #if BUILD_OOCD_TRACE == 1
634 &oocd_trace_capture_driver,
635 #endif
636 NULL
637 };
638
639 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
640 {
641 int i;
642 int section = -1;
643 uint32_t size_read;
644 uint32_t opcode;
645 int retval;
646
647 if (!ctx->image)
648 return ERROR_TRACE_IMAGE_UNAVAILABLE;
649
650 /* search for the section the current instruction belongs to */
651 for (i = 0; i < ctx->image->num_sections; i++)
652 {
653 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
654 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
655 {
656 section = i;
657 break;
658 }
659 }
660
661 if (section == -1)
662 {
663 /* current instruction couldn't be found in the image */
664 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
665 }
666
667 if (ctx->core_state == ARMV4_5_STATE_ARM)
668 {
669 uint8_t buf[4];
670 if ((retval = image_read_section(ctx->image, section,
671 ctx->current_pc - ctx->image->sections[section].base_address,
672 4, buf, &size_read)) != ERROR_OK)
673 {
674 LOG_ERROR("error while reading instruction: %i", retval);
675 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
676 }
677 opcode = target_buffer_get_u32(ctx->target, buf);
678 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
679 }
680 else if (ctx->core_state == ARMV4_5_STATE_THUMB)
681 {
682 uint8_t buf[2];
683 if ((retval = image_read_section(ctx->image, section,
684 ctx->current_pc - ctx->image->sections[section].base_address,
685 2, buf, &size_read)) != ERROR_OK)
686 {
687 LOG_ERROR("error while reading instruction: %i", retval);
688 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
689 }
690 opcode = target_buffer_get_u16(ctx->target, buf);
691 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
692 }
693 else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
694 {
695 LOG_ERROR("BUG: tracing of jazelle code not supported");
696 return ERROR_FAIL;
697 }
698 else
699 {
700 LOG_ERROR("BUG: unknown core state encountered");
701 return ERROR_FAIL;
702 }
703
704 return ERROR_OK;
705 }
706
707 static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
708 {
709 while (ctx->data_index < ctx->trace_depth)
710 {
711 /* if the caller specified an address packet offset, skip until the
712 * we reach the n-th cycle marked with tracesync */
713 if (apo > 0)
714 {
715 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
716 apo--;
717
718 if (apo > 0)
719 {
720 ctx->data_index++;
721 ctx->data_half = 0;
722 }
723 continue;
724 }
725
726 /* no tracedata output during a TD cycle
727 * or in a trigger cycle */
728 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
729 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
730 {
731 ctx->data_index++;
732 ctx->data_half = 0;
733 continue;
734 }
735
736 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
737 {
738 if (ctx->data_half == 0)
739 {
740 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
741 ctx->data_half = 1;
742 }
743 else
744 {
745 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
746 ctx->data_half = 0;
747 ctx->data_index++;
748 }
749 }
750 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
751 {
752 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
753 ctx->data_index++;
754 }
755 else
756 {
757 /* on a 4-bit port, a packet will be output during two consecutive cycles */
758 if (ctx->data_index > (ctx->trace_depth - 2))
759 return -1;
760
761 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
762 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
763 ctx->data_index += 2;
764 }
765
766 return 0;
767 }
768
769 return -1;
770 }
771
772 static int etmv1_branch_address(etm_context_t *ctx)
773 {
774 int retval;
775 uint8_t packet;
776 int shift = 0;
777 int apo;
778 uint32_t i;
779
780 /* quit analysis if less than two cycles are left in the trace
781 * because we can't extract the APO */
782 if (ctx->data_index > (ctx->trace_depth - 2))
783 return -1;
784
785 /* a BE could be output during an APO cycle, skip the current
786 * and continue with the new one */
787 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
788 return 1;
789 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
790 return 2;
791
792 /* address packet offset encoded in the next two cycles' pipestat bits */
793 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
794 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
795
796 /* count number of tracesync cycles between current pipe_index and data_index
797 * i.e. the number of tracesyncs that data_index already passed by
798 * to subtract them from the APO */
799 for (i = ctx->pipe_index; i < ctx->data_index; i++)
800 {
801 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
802 apo--;
803 }
804
805 /* extract up to four 7-bit packets */
806 do {
807 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
808 return -1;
809 ctx->last_branch &= ~(0x7f << shift);
810 ctx->last_branch |= (packet & 0x7f) << shift;
811 shift += 7;
812 } while ((packet & 0x80) && (shift < 28));
813
814 /* one last packet holding 4 bits of the address, plus the branch reason code */
815 if ((shift == 28) && (packet & 0x80))
816 {
817 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
818 return -1;
819 ctx->last_branch &= 0x0fffffff;
820 ctx->last_branch |= (packet & 0x0f) << 28;
821 ctx->last_branch_reason = (packet & 0x70) >> 4;
822 shift += 4;
823 }
824 else
825 {
826 ctx->last_branch_reason = 0;
827 }
828
829 if (shift == 32)
830 {
831 ctx->pc_ok = 1;
832 }
833
834 /* if a full address was output, we might have branched into Jazelle state */
835 if ((shift == 32) && (packet & 0x80))
836 {
837 ctx->core_state = ARMV4_5_STATE_JAZELLE;
838 }
839 else
840 {
841 /* if we didn't branch into Jazelle state, the current processor state is
842 * encoded in bit 0 of the branch target address */
843 if (ctx->last_branch & 0x1)
844 {
845 ctx->core_state = ARMV4_5_STATE_THUMB;
846 ctx->last_branch &= ~0x1;
847 }
848 else
849 {
850 ctx->core_state = ARMV4_5_STATE_ARM;
851 ctx->last_branch &= ~0x3;
852 }
853 }
854
855 return 0;
856 }
857
858 static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
859 {
860 int j;
861 uint8_t buf[4];
862 int retval;
863
864 for (j = 0; j < size; j++)
865 {
866 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
867 return -1;
868 }
869
870 if (size == 8)
871 {
872 LOG_ERROR("TODO: add support for 64-bit values");
873 return -1;
874 }
875 else if (size == 4)
876 *data = target_buffer_get_u32(ctx->target, buf);
877 else if (size == 2)
878 *data = target_buffer_get_u16(ctx->target, buf);
879 else if (size == 1)
880 *data = buf[0];
881 else
882 return -1;
883
884 return 0;
885 }
886
887 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
888 {
889 int retval;
890 arm_instruction_t instruction;
891
892 /* read the trace data if it wasn't read already */
893 if (ctx->trace_depth == 0)
894 ctx->capture_driver->read_trace(ctx);
895
896 /* start at the beginning of the captured trace */
897 ctx->pipe_index = 0;
898 ctx->data_index = 0;
899 ctx->data_half = 0;
900
901 /* neither the PC nor the data pointer are valid */
902 ctx->pc_ok = 0;
903 ctx->ptr_ok = 0;
904
905 while (ctx->pipe_index < ctx->trace_depth)
906 {
907 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
908 uint32_t next_pc = ctx->current_pc;
909 uint32_t old_data_index = ctx->data_index;
910 uint32_t old_data_half = ctx->data_half;
911 uint32_t old_index = ctx->pipe_index;
912 uint32_t last_instruction = ctx->last_instruction;
913 uint32_t cycles = 0;
914 int current_pc_ok = ctx->pc_ok;
915
916 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
917 {
918 command_print(cmd_ctx, "--- trigger ---");
919 }
920
921 /* instructions execute in IE/D or BE/D cycles */
922 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
923 ctx->last_instruction = ctx->pipe_index;
924
925 /* if we don't have a valid pc skip until we reach an indirect branch */
926 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
927 {
928 ctx->pipe_index++;
929 continue;
930 }
931
932 /* any indirect branch could have interrupted instruction flow
933 * - the branch reason code could indicate a trace discontinuity
934 * - a branch to the exception vectors indicates an exception
935 */
936 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
937 {
938 /* backup current data index, to be able to consume the branch address
939 * before examining data address and values
940 */
941 old_data_index = ctx->data_index;
942 old_data_half = ctx->data_half;
943
944 ctx->last_instruction = ctx->pipe_index;
945
946 if ((retval = etmv1_branch_address(ctx)) != 0)
947 {
948 /* negative return value from etmv1_branch_address means we ran out of packets,
949 * quit analysing the trace */
950 if (retval < 0)
951 break;
952
953 /* a positive return values means the current branch was abandoned,
954 * and a new branch was encountered in cycle ctx->pipe_index + retval;
955 */
956 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
957 ctx->pipe_index += retval;
958 continue;
959 }
960
961 /* skip over APO cycles */
962 ctx->pipe_index += 2;
963
964 switch (ctx->last_branch_reason)
965 {
966 case 0x0: /* normal PC change */
967 next_pc = ctx->last_branch;
968 break;
969 case 0x1: /* tracing enabled */
970 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
971 ctx->current_pc = ctx->last_branch;
972 ctx->pipe_index++;
973 continue;
974 break;
975 case 0x2: /* trace restarted after FIFO overflow */
976 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
977 ctx->current_pc = ctx->last_branch;
978 ctx->pipe_index++;
979 continue;
980 break;
981 case 0x3: /* exit from debug state */
982 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
983 ctx->current_pc = ctx->last_branch;
984 ctx->pipe_index++;
985 continue;
986 break;
987 case 0x4: /* periodic synchronization point */
988 next_pc = ctx->last_branch;
989 /* if we had no valid PC prior to this synchronization point,
990 * we have to move on with the next trace cycle
991 */
992 if (!current_pc_ok)
993 {
994 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
995 ctx->current_pc = next_pc;
996 ctx->pipe_index++;
997 continue;
998 }
999 break;
1000 default: /* reserved */
1001 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
1002 return ERROR_FAIL;
1003 }
1004
1005 /* if we got here the branch was a normal PC change
1006 * (or a periodic synchronization point, which means the same for that matter)
1007 * if we didn't accquire a complete PC continue with the next cycle
1008 */
1009 if (!ctx->pc_ok)
1010 continue;
1011
1012 /* indirect branch to the exception vector means an exception occured */
1013 if ((ctx->last_branch <= 0x20)
1014 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1015 {
1016 if ((ctx->last_branch & 0xff) == 0x10)
1017 {
1018 command_print(cmd_ctx, "data abort");
1019 }
1020 else
1021 {
1022 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1023 ctx->current_pc = ctx->last_branch;
1024 ctx->pipe_index++;
1025 continue;
1026 }
1027 }
1028 }
1029
1030 /* an instruction was executed (or not, depending on the condition flags)
1031 * retrieve it from the image for displaying */
1032 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1033 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1034 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1035 {
1036 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1037 {
1038 /* can't continue tracing with no image available */
1039 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1040 {
1041 return retval;
1042 }
1043 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1044 {
1045 /* TODO: handle incomplete images
1046 * for now we just quit the analsysis*/
1047 return retval;
1048 }
1049 }
1050
1051 cycles = old_index - last_instruction;
1052 }
1053
1054 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1055 {
1056 uint32_t new_data_index = ctx->data_index;
1057 uint32_t new_data_half = ctx->data_half;
1058
1059 /* in case of a branch with data, the branch target address was consumed before
1060 * we temporarily go back to the saved data index */
1061 if (pipestat == STAT_BD)
1062 {
1063 ctx->data_index = old_data_index;
1064 ctx->data_half = old_data_half;
1065 }
1066
1067 if (ctx->tracemode & ETMV1_TRACE_ADDR)
1068 {
1069 uint8_t packet;
1070 int shift = 0;
1071
1072 do {
1073 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1074 return ERROR_ETM_ANALYSIS_FAILED;
1075 ctx->last_ptr &= ~(0x7f << shift);
1076 ctx->last_ptr |= (packet & 0x7f) << shift;
1077 shift += 7;
1078 } while ((packet & 0x80) && (shift < 32));
1079
1080 if (shift >= 32)
1081 ctx->ptr_ok = 1;
1082
1083 if (ctx->ptr_ok)
1084 {
1085 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1086 }
1087 }
1088
1089 if (ctx->tracemode & ETMV1_TRACE_DATA)
1090 {
1091 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1092 {
1093 int i;
1094 for (i = 0; i < 16; i++)
1095 {
1096 if (instruction.info.load_store_multiple.register_list & (1 << i))
1097 {
1098 uint32_t data;
1099 if (etmv1_data(ctx, 4, &data) != 0)
1100 return ERROR_ETM_ANALYSIS_FAILED;
1101 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1102 }
1103 }
1104 }
1105 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1106 {
1107 uint32_t data;
1108 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1109 return ERROR_ETM_ANALYSIS_FAILED;
1110 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1111 }
1112 }
1113
1114 /* restore data index after consuming BD address and data */
1115 if (pipestat == STAT_BD)
1116 {
1117 ctx->data_index = new_data_index;
1118 ctx->data_half = new_data_half;
1119 }
1120 }
1121
1122 /* adjust PC */
1123 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1124 {
1125 if (((instruction.type == ARM_B) ||
1126 (instruction.type == ARM_BL) ||
1127 (instruction.type == ARM_BLX)) &&
1128 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1129 {
1130 next_pc = instruction.info.b_bl_bx_blx.target_address;
1131 }
1132 else
1133 {
1134 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1135 }
1136 }
1137 else if (pipestat == STAT_IN)
1138 {
1139 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1140 }
1141
1142 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1143 {
1144 char cycles_text[32] = "";
1145
1146 /* if the trace was captured with cycle accurate tracing enabled,
1147 * output the number of cycles since the last executed instruction
1148 */
1149 if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1150 {
1151 snprintf(cycles_text, 32, " (%i %s)",
1152 (int)cycles,
1153 (cycles == 1) ? "cycle" : "cycles");
1154 }
1155
1156 command_print(cmd_ctx, "%s%s%s",
1157 instruction.text,
1158 (pipestat == STAT_IN) ? " (not executed)" : "",
1159 cycles_text);
1160
1161 ctx->current_pc = next_pc;
1162
1163 /* packets for an instruction don't start on or before the preceding
1164 * functional pipestat (i.e. other than WT or TD)
1165 */
1166 if (ctx->data_index <= ctx->pipe_index)
1167 {
1168 ctx->data_index = ctx->pipe_index + 1;
1169 ctx->data_half = 0;
1170 }
1171 }
1172
1173 ctx->pipe_index += 1;
1174 }
1175
1176 return ERROR_OK;
1177 }
1178
1179 static int handle_etm_tracemode_command_update(
1180 struct command_context_s *cmd_ctx,
1181 char **args, etmv1_tracemode_t *mode)
1182 {
1183 etmv1_tracemode_t tracemode;
1184
1185 /* what parts of data access are traced? */
1186 if (strcmp(args[0], "none") == 0)
1187 tracemode = ETMV1_TRACE_NONE;
1188 else if (strcmp(args[0], "data") == 0)
1189 tracemode = ETMV1_TRACE_DATA;
1190 else if (strcmp(args[0], "address") == 0)
1191 tracemode = ETMV1_TRACE_ADDR;
1192 else if (strcmp(args[0], "all") == 0)
1193 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1194 else
1195 {
1196 command_print(cmd_ctx, "invalid option '%s'", args[0]);
1197 return ERROR_INVALID_ARGUMENTS;
1198 }
1199
1200 uint8_t context_id;
1201 COMMAND_PARSE_NUMBER(u8, args[1], context_id);
1202 switch (context_id)
1203 {
1204 case 0:
1205 tracemode |= ETMV1_CONTEXTID_NONE;
1206 break;
1207 case 8:
1208 tracemode |= ETMV1_CONTEXTID_8;
1209 break;
1210 case 16:
1211 tracemode |= ETMV1_CONTEXTID_16;
1212 break;
1213 case 32:
1214 tracemode |= ETMV1_CONTEXTID_32;
1215 break;
1216 default:
1217 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1218 return ERROR_INVALID_ARGUMENTS;
1219 }
1220
1221 if (strcmp(args[2], "enable") == 0)
1222 tracemode |= ETMV1_CYCLE_ACCURATE;
1223 else if (strcmp(args[2], "disable") == 0)
1224 tracemode |= 0;
1225 else
1226 {
1227 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1228 return ERROR_INVALID_ARGUMENTS;
1229 }
1230
1231 if (strcmp(args[3], "enable") == 0)
1232 tracemode |= ETMV1_BRANCH_OUTPUT;
1233 else if (strcmp(args[3], "disable") == 0)
1234 tracemode |= 0;
1235 else
1236 {
1237 command_print(cmd_ctx, "invalid option '%s'", args[3]);
1238 return ERROR_INVALID_ARGUMENTS;
1239 }
1240
1241 /* IGNORED:
1242 * - CPRT tracing (coprocessor register transfers)
1243 * - debug request (causes debug entry on trigger)
1244 * - stall on FIFOFULL (preventing tracedata lossage)
1245 */
1246 *mode = tracemode;
1247
1248 return ERROR_OK;
1249 }
1250
1251 static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx,
1252 char *cmd, char **args, int argc)
1253 {
1254 target_t *target = get_current_target(cmd_ctx);
1255 struct arm *arm = target_to_arm(target);
1256 struct etm *etm;
1257
1258 if (!is_arm(arm)) {
1259 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1260 return ERROR_FAIL;
1261 }
1262
1263 etm = arm->etm;
1264 if (!etm) {
1265 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1266 return ERROR_FAIL;
1267 }
1268
1269 etmv1_tracemode_t tracemode = etm->tracemode;
1270
1271 switch (argc)
1272 {
1273 case 0:
1274 break;
1275 case 4:
1276 handle_etm_tracemode_command_update(cmd_ctx, args, &tracemode);
1277 break;
1278 default:
1279 command_print(cmd_ctx, "usage: configure trace mode "
1280 "<none | data | address | all> "
1281 "<context id bits> <cycle accurate> <branch output>");
1282 return ERROR_FAIL;
1283 }
1284
1285 /**
1286 * todo: fail if parameters were invalid for this hardware,
1287 * or couldn't be written; display actual hardware state...
1288 */
1289
1290 command_print(cmd_ctx, "current tracemode configuration:");
1291
1292 switch (tracemode & ETMV1_TRACE_MASK)
1293 {
1294 case ETMV1_TRACE_NONE:
1295 command_print(cmd_ctx, "data tracing: none");
1296 break;
1297 case ETMV1_TRACE_DATA:
1298 command_print(cmd_ctx, "data tracing: data only");
1299 break;
1300 case ETMV1_TRACE_ADDR:
1301 command_print(cmd_ctx, "data tracing: address only");
1302 break;
1303 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1304 command_print(cmd_ctx, "data tracing: address and data");
1305 break;
1306 }
1307
1308 switch (tracemode & ETMV1_CONTEXTID_MASK)
1309 {
1310 case ETMV1_CONTEXTID_NONE:
1311 command_print(cmd_ctx, "contextid tracing: none");
1312 break;
1313 case ETMV1_CONTEXTID_8:
1314 command_print(cmd_ctx, "contextid tracing: 8 bit");
1315 break;
1316 case ETMV1_CONTEXTID_16:
1317 command_print(cmd_ctx, "contextid tracing: 16 bit");
1318 break;
1319 case ETMV1_CONTEXTID_32:
1320 command_print(cmd_ctx, "contextid tracing: 32 bit");
1321 break;
1322 }
1323
1324 if (tracemode & ETMV1_CYCLE_ACCURATE)
1325 {
1326 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1327 }
1328 else
1329 {
1330 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1331 }
1332
1333 if (tracemode & ETMV1_BRANCH_OUTPUT)
1334 {
1335 command_print(cmd_ctx, "full branch address output enabled");
1336 }
1337 else
1338 {
1339 command_print(cmd_ctx, "full branch address output disabled");
1340 }
1341
1342 /* only update ETM_CTRL register if tracemode changed */
1343 if (etm->tracemode != tracemode)
1344 {
1345 reg_t *etm_ctrl_reg;
1346
1347 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1348 if (!etm_ctrl_reg)
1349 return ERROR_FAIL;
1350
1351 etm_get_reg(etm_ctrl_reg);
1352
1353 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1354 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1355 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1356 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1357 etm_store_reg(etm_ctrl_reg);
1358
1359 etm->tracemode = tracemode;
1360
1361 /* invalidate old trace data */
1362 etm->capture_status = TRACE_IDLE;
1363 if (etm->trace_depth > 0)
1364 {
1365 free(etm->trace_data);
1366 etm->trace_data = NULL;
1367 }
1368 etm->trace_depth = 0;
1369 }
1370
1371 return ERROR_OK;
1372 }
1373
1374 static int handle_etm_config_command(struct command_context_s *cmd_ctx,
1375 char *cmd, char **args, int argc)
1376 {
1377 target_t *target;
1378 struct arm *arm;
1379 etm_portmode_t portmode = 0x0;
1380 struct etm *etm_ctx;
1381 int i;
1382
1383 if (argc != 5)
1384 return ERROR_COMMAND_SYNTAX_ERROR;
1385
1386 target = get_target(args[0]);
1387 if (!target)
1388 {
1389 LOG_ERROR("target '%s' not defined", args[0]);
1390 return ERROR_FAIL;
1391 }
1392
1393 arm = target_to_arm(target);
1394 if (!is_arm(arm)) {
1395 command_print(cmd_ctx, "target '%s' is '%s'; not an ARM",
1396 target->cmd_name, target_get_name(target));
1397 return ERROR_FAIL;
1398 }
1399
1400 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1401 * version we'll be using!! -- so we can't know how to validate
1402 * params yet. "etm config" should likely be *AFTER* hookup...
1403 *
1404 * - Many more widths might be supported ... and we can easily
1405 * check whether our setting "took".
1406 *
1407 * - The "clock" and "mode" bits are interpreted differently.
1408 * See ARM IHI 0014O table 2-17 for the old behavior, and
1409 * table 2-18 for the new. With ETB it's best to specify
1410 * "normal full" ...
1411 */
1412 uint8_t port_width;
1413 COMMAND_PARSE_NUMBER(u8, args[1], port_width);
1414 switch (port_width)
1415 {
1416 /* before ETMv3.0 */
1417 case 4:
1418 portmode |= ETM_PORT_4BIT;
1419 break;
1420 case 8:
1421 portmode |= ETM_PORT_8BIT;
1422 break;
1423 case 16:
1424 portmode |= ETM_PORT_16BIT;
1425 break;
1426 /* ETMv3.0 and later*/
1427 case 24:
1428 portmode |= ETM_PORT_24BIT;
1429 break;
1430 case 32:
1431 portmode |= ETM_PORT_32BIT;
1432 break;
1433 case 48:
1434 portmode |= ETM_PORT_48BIT;
1435 break;
1436 case 64:
1437 portmode |= ETM_PORT_64BIT;
1438 break;
1439 case 1:
1440 portmode |= ETM_PORT_1BIT;
1441 break;
1442 case 2:
1443 portmode |= ETM_PORT_2BIT;
1444 break;
1445 default:
1446 command_print(cmd_ctx,
1447 "unsupported ETM port width '%s'", args[1]);
1448 return ERROR_FAIL;
1449 }
1450
1451 if (strcmp("normal", args[2]) == 0)
1452 {
1453 portmode |= ETM_PORT_NORMAL;
1454 }
1455 else if (strcmp("multiplexed", args[2]) == 0)
1456 {
1457 portmode |= ETM_PORT_MUXED;
1458 }
1459 else if (strcmp("demultiplexed", args[2]) == 0)
1460 {
1461 portmode |= ETM_PORT_DEMUXED;
1462 }
1463 else
1464 {
1465 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1466 return ERROR_FAIL;
1467 }
1468
1469 if (strcmp("half", args[3]) == 0)
1470 {
1471 portmode |= ETM_PORT_HALF_CLOCK;
1472 }
1473 else if (strcmp("full", args[3]) == 0)
1474 {
1475 portmode |= ETM_PORT_FULL_CLOCK;
1476 }
1477 else
1478 {
1479 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1480 return ERROR_FAIL;
1481 }
1482
1483 etm_ctx = calloc(1, sizeof(etm_context_t));
1484 if (!etm_ctx) {
1485 LOG_DEBUG("out of memory");
1486 return ERROR_FAIL;
1487 }
1488
1489 for (i = 0; etm_capture_drivers[i]; i++)
1490 {
1491 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1492 {
1493 int retval;
1494 if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1495 {
1496 free(etm_ctx);
1497 return retval;
1498 }
1499
1500 etm_ctx->capture_driver = etm_capture_drivers[i];
1501
1502 break;
1503 }
1504 }
1505
1506 if (!etm_capture_drivers[i])
1507 {
1508 /* no supported capture driver found, don't register an ETM */
1509 free(etm_ctx);
1510 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1511 return ERROR_FAIL;
1512 }
1513
1514 etm_ctx->target = target;
1515 etm_ctx->trigger_percent = 50;
1516 etm_ctx->trace_data = NULL;
1517 etm_ctx->portmode = portmode;
1518 etm_ctx->core_state = ARMV4_5_STATE_ARM;
1519
1520 arm->etm = etm_ctx;
1521
1522 return etm_register_user_commands(cmd_ctx);
1523 }
1524
1525 static int handle_etm_info_command(struct command_context_s *cmd_ctx,
1526 char *cmd, char **args, int argc)
1527 {
1528 target_t *target;
1529 struct arm *arm;
1530 etm_context_t *etm;
1531 reg_t *etm_sys_config_reg;
1532 int max_port_size;
1533 uint32_t config;
1534
1535 target = get_current_target(cmd_ctx);
1536 arm = target_to_arm(target);
1537 if (!is_arm(arm))
1538 {
1539 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1540 return ERROR_FAIL;
1541 }
1542
1543 etm = arm->etm;
1544 if (!etm)
1545 {
1546 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1547 return ERROR_FAIL;
1548 }
1549
1550 command_print(cmd_ctx, "ETM v%d.%d",
1551 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1552 command_print(cmd_ctx, "pairs of address comparators: %i",
1553 (int) (etm->config >> 0) & 0x0f);
1554 command_print(cmd_ctx, "data comparators: %i",
1555 (int) (etm->config >> 4) & 0x0f);
1556 command_print(cmd_ctx, "memory map decoders: %i",
1557 (int) (etm->config >> 8) & 0x1f);
1558 command_print(cmd_ctx, "number of counters: %i",
1559 (int) (etm->config >> 13) & 0x07);
1560 command_print(cmd_ctx, "sequencer %spresent",
1561 (int) (etm->config & (1 << 16)) ? "" : "not ");
1562 command_print(cmd_ctx, "number of ext. inputs: %i",
1563 (int) (etm->config >> 17) & 0x07);
1564 command_print(cmd_ctx, "number of ext. outputs: %i",
1565 (int) (etm->config >> 20) & 0x07);
1566 command_print(cmd_ctx, "FIFO full %spresent",
1567 (int) (etm->config & (1 << 23)) ? "" : "not ");
1568 if (etm->bcd_vers < 0x20)
1569 command_print(cmd_ctx, "protocol version: %i",
1570 (int) (etm->config >> 28) & 0x07);
1571 else {
1572 command_print(cmd_ctx,
1573 "coprocessor and memory access %ssupported",
1574 (etm->config & (1 << 26)) ? "" : "not ");
1575 command_print(cmd_ctx, "trace start/stop %spresent",
1576 (etm->config & (1 << 26)) ? "" : "not ");
1577 command_print(cmd_ctx, "number of context comparators: %i",
1578 (int) (etm->config >> 24) & 0x03);
1579 }
1580
1581 /* SYS_CONFIG isn't present before ETMv1.2 */
1582 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1583 if (!etm_sys_config_reg)
1584 return ERROR_OK;
1585
1586 etm_get_reg(etm_sys_config_reg);
1587 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1588
1589 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1590
1591 max_port_size = config & 0x7;
1592 if (etm->bcd_vers >= 0x30)
1593 max_port_size |= (config >> 6) & 0x08;
1594 switch (max_port_size)
1595 {
1596 /* before ETMv3.0 */
1597 case 0:
1598 max_port_size = 4;
1599 break;
1600 case 1:
1601 max_port_size = 8;
1602 break;
1603 case 2:
1604 max_port_size = 16;
1605 break;
1606 /* ETMv3.0 and later*/
1607 case 3:
1608 max_port_size = 24;
1609 break;
1610 case 4:
1611 max_port_size = 32;
1612 break;
1613 case 5:
1614 max_port_size = 48;
1615 break;
1616 case 6:
1617 max_port_size = 64;
1618 break;
1619 case 8:
1620 max_port_size = 1;
1621 break;
1622 case 9:
1623 max_port_size = 2;
1624 break;
1625 default:
1626 LOG_ERROR("Illegal max_port_size");
1627 return ERROR_FAIL;
1628 }
1629 command_print(cmd_ctx, "max. port size: %i", max_port_size);
1630
1631 if (etm->bcd_vers < 0x30) {
1632 command_print(cmd_ctx, "half-rate clocking %ssupported",
1633 (config & (1 << 3)) ? "" : "not ");
1634 command_print(cmd_ctx, "full-rate clocking %ssupported",
1635 (config & (1 << 4)) ? "" : "not ");
1636 command_print(cmd_ctx, "normal trace format %ssupported",
1637 (config & (1 << 5)) ? "" : "not ");
1638 command_print(cmd_ctx, "multiplex trace format %ssupported",
1639 (config & (1 << 6)) ? "" : "not ");
1640 command_print(cmd_ctx, "demultiplex trace format %ssupported",
1641 (config & (1 << 7)) ? "" : "not ");
1642 } else {
1643 /* REVISIT show which size and format are selected ... */
1644 command_print(cmd_ctx, "current port size %ssupported",
1645 (config & (1 << 10)) ? "" : "not ");
1646 command_print(cmd_ctx, "current trace format %ssupported",
1647 (config & (1 << 11)) ? "" : "not ");
1648 }
1649 if (etm->bcd_vers >= 0x21)
1650 command_print(cmd_ctx, "fetch comparisons %ssupported",
1651 (config & (1 << 17)) ? "not " : "");
1652 command_print(cmd_ctx, "FIFO full %ssupported",
1653 (config & (1 << 8)) ? "" : "not ");
1654
1655 return ERROR_OK;
1656 }
1657
1658 static int handle_etm_status_command(struct command_context_s *cmd_ctx,
1659 char *cmd, char **args, int argc)
1660 {
1661 target_t *target;
1662 struct arm *arm;
1663 etm_context_t *etm;
1664 trace_status_t trace_status;
1665
1666 target = get_current_target(cmd_ctx);
1667 arm = target_to_arm(target);
1668 if (!is_arm(arm))
1669 {
1670 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1671 return ERROR_FAIL;
1672 }
1673
1674 etm = arm->etm;
1675 if (!etm)
1676 {
1677 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1678 return ERROR_FAIL;
1679 }
1680
1681 /* ETM status */
1682 if (etm->bcd_vers >= 0x11) {
1683 reg_t *reg;
1684
1685 reg = etm_reg_lookup(etm, ETM_STATUS);
1686 if (!reg)
1687 return ERROR_FAIL;
1688 if (etm_get_reg(reg) == ERROR_OK) {
1689 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1690
1691 command_print(cmd_ctx, "etm: %s%s%s%s",
1692 /* bit(1) == progbit */
1693 (etm->bcd_vers >= 0x12)
1694 ? ((s & (1 << 1))
1695 ? "disabled" : "enabled")
1696 : "?",
1697 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1698 ? " triggered" : "",
1699 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1700 ? " start/stop" : "",
1701 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1702 ? " untraced-overflow" : "");
1703 } /* else ignore and try showing trace port status */
1704 }
1705
1706 /* Trace Port Driver status */
1707 trace_status = etm->capture_driver->status(etm);
1708 if (trace_status == TRACE_IDLE)
1709 {
1710 command_print(cmd_ctx, "%s: idle", etm->capture_driver->name);
1711 }
1712 else
1713 {
1714 static char *completed = " completed";
1715 static char *running = " is running";
1716 static char *overflowed = ", overflowed";
1717 static char *triggered = ", triggered";
1718
1719 command_print(cmd_ctx, "%s: trace collection%s%s%s",
1720 etm->capture_driver->name,
1721 (trace_status & TRACE_RUNNING) ? running : completed,
1722 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1723 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1724
1725 if (etm->trace_depth > 0)
1726 {
1727 command_print(cmd_ctx, "%i frames of trace data read",
1728 (int)(etm->trace_depth));
1729 }
1730 }
1731
1732 return ERROR_OK;
1733 }
1734
1735 static int handle_etm_image_command(struct command_context_s *cmd_ctx,
1736 char *cmd, char **args, int argc)
1737 {
1738 target_t *target;
1739 struct arm *arm;
1740 etm_context_t *etm_ctx;
1741
1742 if (argc < 1)
1743 {
1744 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1745 return ERROR_FAIL;
1746 }
1747
1748 target = get_current_target(cmd_ctx);
1749 arm = target_to_arm(target);
1750 if (!is_arm(arm))
1751 {
1752 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1753 return ERROR_FAIL;
1754 }
1755
1756 etm_ctx = arm->etm;
1757 if (!etm_ctx)
1758 {
1759 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1760 return ERROR_FAIL;
1761 }
1762
1763 if (etm_ctx->image)
1764 {
1765 image_close(etm_ctx->image);
1766 free(etm_ctx->image);
1767 command_print(cmd_ctx, "previously loaded image found and closed");
1768 }
1769
1770 etm_ctx->image = malloc(sizeof(image_t));
1771 etm_ctx->image->base_address_set = 0;
1772 etm_ctx->image->start_address_set = 0;
1773
1774 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1775 if (argc >= 2)
1776 {
1777 etm_ctx->image->base_address_set = 1;
1778 COMMAND_PARSE_NUMBER(int, args[1], etm_ctx->image->base_address);
1779 }
1780 else
1781 {
1782 etm_ctx->image->base_address_set = 0;
1783 }
1784
1785 if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1786 {
1787 free(etm_ctx->image);
1788 etm_ctx->image = NULL;
1789 return ERROR_FAIL;
1790 }
1791
1792 return ERROR_OK;
1793 }
1794
1795 static int handle_etm_dump_command(struct command_context_s *cmd_ctx,
1796 char *cmd, char **args, int argc)
1797 {
1798 fileio_t file;
1799 target_t *target;
1800 struct arm *arm;
1801 etm_context_t *etm_ctx;
1802 uint32_t i;
1803
1804 if (argc != 1)
1805 {
1806 command_print(cmd_ctx, "usage: etm dump <file>");
1807 return ERROR_FAIL;
1808 }
1809
1810 target = get_current_target(cmd_ctx);
1811 arm = target_to_arm(target);
1812 if (!is_arm(arm))
1813 {
1814 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1815 return ERROR_FAIL;
1816 }
1817
1818 etm_ctx = arm->etm;
1819 if (!etm_ctx)
1820 {
1821 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1822 return ERROR_FAIL;
1823 }
1824
1825 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1826 {
1827 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1828 return ERROR_OK;
1829 }
1830
1831 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1832 {
1833 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1834 command_print(cmd_ctx, "trace capture not completed");
1835 return ERROR_FAIL;
1836 }
1837
1838 /* read the trace data if it wasn't read already */
1839 if (etm_ctx->trace_depth == 0)
1840 etm_ctx->capture_driver->read_trace(etm_ctx);
1841
1842 if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1843 {
1844 return ERROR_FAIL;
1845 }
1846
1847 fileio_write_u32(&file, etm_ctx->capture_status);
1848 fileio_write_u32(&file, etm_ctx->portmode);
1849 fileio_write_u32(&file, etm_ctx->tracemode);
1850 fileio_write_u32(&file, etm_ctx->trace_depth);
1851
1852 for (i = 0; i < etm_ctx->trace_depth; i++)
1853 {
1854 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1855 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1856 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1857 }
1858
1859 fileio_close(&file);
1860
1861 return ERROR_OK;
1862 }
1863
1864 static int handle_etm_load_command(struct command_context_s *cmd_ctx,
1865 char *cmd, char **args, int argc)
1866 {
1867 fileio_t file;
1868 target_t *target;
1869 struct arm *arm;
1870 etm_context_t *etm_ctx;
1871 uint32_t i;
1872
1873 if (argc != 1)
1874 {
1875 command_print(cmd_ctx, "usage: etm load <file>");
1876 return ERROR_FAIL;
1877 }
1878
1879 target = get_current_target(cmd_ctx);
1880 arm = target_to_arm(target);
1881 if (!is_arm(arm))
1882 {
1883 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1884 return ERROR_FAIL;
1885 }
1886
1887 etm_ctx = arm->etm;
1888 if (!etm_ctx)
1889 {
1890 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1891 return ERROR_FAIL;
1892 }
1893
1894 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1895 {
1896 command_print(cmd_ctx, "trace capture running, stop first");
1897 return ERROR_FAIL;
1898 }
1899
1900 if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1901 {
1902 return ERROR_FAIL;
1903 }
1904
1905 if (file.size % 4)
1906 {
1907 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1908 fileio_close(&file);
1909 return ERROR_FAIL;
1910 }
1911
1912 if (etm_ctx->trace_depth > 0)
1913 {
1914 free(etm_ctx->trace_data);
1915 etm_ctx->trace_data = NULL;
1916 }
1917
1918 {
1919 uint32_t tmp;
1920 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1921 fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1922 fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1923 fileio_read_u32(&file, &etm_ctx->trace_depth);
1924 }
1925 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1926 if (etm_ctx->trace_data == NULL)
1927 {
1928 command_print(cmd_ctx, "not enough memory to perform operation");
1929 fileio_close(&file);
1930 return ERROR_FAIL;
1931 }
1932
1933 for (i = 0; i < etm_ctx->trace_depth; i++)
1934 {
1935 uint32_t pipestat, packet, flags;
1936 fileio_read_u32(&file, &pipestat);
1937 fileio_read_u32(&file, &packet);
1938 fileio_read_u32(&file, &flags);
1939 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1940 etm_ctx->trace_data[i].packet = packet & 0xffff;
1941 etm_ctx->trace_data[i].flags = flags;
1942 }
1943
1944 fileio_close(&file);
1945
1946 return ERROR_OK;
1947 }
1948
1949 static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx,
1950 char *cmd, char **args, int argc)
1951 {
1952 target_t *target;
1953 struct arm *arm;
1954 etm_context_t *etm_ctx;
1955
1956 target = get_current_target(cmd_ctx);
1957 arm = target_to_arm(target);
1958 if (!is_arm(arm))
1959 {
1960 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1961 return ERROR_FAIL;
1962 }
1963
1964 etm_ctx = arm->etm;
1965 if (!etm_ctx)
1966 {
1967 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1968 return ERROR_FAIL;
1969 }
1970
1971 if (argc > 0)
1972 {
1973 uint32_t new_value;
1974 COMMAND_PARSE_NUMBER(u32, args[0], new_value);
1975
1976 if ((new_value < 2) || (new_value > 100))
1977 {
1978 command_print(cmd_ctx, "valid settings are 2%% to 100%%");
1979 }
1980 else
1981 {
1982 etm_ctx->trigger_percent = new_value;
1983 }
1984 }
1985
1986 command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1987
1988 return ERROR_OK;
1989 }
1990
1991 static int handle_etm_start_command(struct command_context_s *cmd_ctx,
1992 char *cmd, char **args, int argc)
1993 {
1994 target_t *target;
1995 struct arm *arm;
1996 etm_context_t *etm_ctx;
1997 reg_t *etm_ctrl_reg;
1998
1999 target = get_current_target(cmd_ctx);
2000 arm = target_to_arm(target);
2001 if (!is_arm(arm))
2002 {
2003 command_print(cmd_ctx, "ETM: current target isn't an ARM");
2004 return ERROR_FAIL;
2005 }
2006
2007 etm_ctx = arm->etm;
2008 if (!etm_ctx)
2009 {
2010 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2011 return ERROR_FAIL;
2012 }
2013
2014 /* invalidate old tracing data */
2015 etm_ctx->capture_status = TRACE_IDLE;
2016 if (etm_ctx->trace_depth > 0)
2017 {
2018 free(etm_ctx->trace_data);
2019 etm_ctx->trace_data = NULL;
2020 }
2021 etm_ctx->trace_depth = 0;
2022
2023 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2024 if (!etm_ctrl_reg)
2025 return ERROR_FAIL;
2026
2027 etm_get_reg(etm_ctrl_reg);
2028
2029 /* Clear programming bit (10), set port selection bit (11) */
2030 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
2031
2032 etm_store_reg(etm_ctrl_reg);
2033 jtag_execute_queue();
2034
2035 etm_ctx->capture_driver->start_capture(etm_ctx);
2036
2037 return ERROR_OK;
2038 }
2039
2040 static int handle_etm_stop_command(struct command_context_s *cmd_ctx,
2041 char *cmd, char **args, int argc)
2042 {
2043 target_t *target;
2044 struct arm *arm;
2045 etm_context_t *etm_ctx;
2046 reg_t *etm_ctrl_reg;
2047
2048 target = get_current_target(cmd_ctx);
2049 arm = target_to_arm(target);
2050 if (!is_arm(arm))
2051 {
2052 command_print(cmd_ctx, "ETM: current target isn't an ARM");
2053 return ERROR_FAIL;
2054 }
2055
2056 etm_ctx = arm->etm;
2057 if (!etm_ctx)
2058 {
2059 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2060 return ERROR_FAIL;
2061 }
2062
2063 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2064 if (!etm_ctrl_reg)
2065 return ERROR_FAIL;
2066
2067 etm_get_reg(etm_ctrl_reg);
2068
2069 /* Set programming bit (10), clear port selection bit (11) */
2070 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2071
2072 etm_store_reg(etm_ctrl_reg);
2073 jtag_execute_queue();
2074
2075 etm_ctx->capture_driver->stop_capture(etm_ctx);
2076
2077 return ERROR_OK;
2078 }
2079
2080 static int handle_etm_analyze_command(struct command_context_s *cmd_ctx,
2081 char *cmd, char **args, int argc)
2082 {
2083 target_t *target;
2084 struct arm *arm;
2085 etm_context_t *etm_ctx;
2086 int retval;
2087
2088 target = get_current_target(cmd_ctx);
2089 arm = target_to_arm(target);
2090 if (!is_arm(arm))
2091 {
2092 command_print(cmd_ctx, "ETM: current target isn't an ARM");
2093 return ERROR_FAIL;
2094 }
2095
2096 etm_ctx = arm->etm;
2097 if (!etm_ctx)
2098 {
2099 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2100 return ERROR_FAIL;
2101 }
2102
2103 if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
2104 {
2105 switch (retval)
2106 {
2107 case ERROR_ETM_ANALYSIS_FAILED:
2108 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
2109 break;
2110 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2111 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
2112 break;
2113 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2114 command_print(cmd_ctx, "no image available for trace analysis");
2115 break;
2116 default:
2117 command_print(cmd_ctx, "unknown error: %i", retval);
2118 }
2119 }
2120
2121 return retval;
2122 }
2123
2124 int etm_register_commands(struct command_context_s *cmd_ctx)
2125 {
2126 etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
2127
2128 register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
2129 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2130
2131 return ERROR_OK;
2132 }
2133
2134 static int etm_register_user_commands(struct command_context_s *cmd_ctx)
2135 {
2136 register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
2137 COMMAND_EXEC, "configure/display trace mode: "
2138 "<none | data | address | all> "
2139 "<context_id_bits> <cycle_accurate> <branch_output>");
2140
2141 register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
2142 COMMAND_EXEC, "display info about the current target's ETM");
2143
2144 register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
2145 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2146 register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
2147 COMMAND_EXEC, "display current target's ETM status");
2148 register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
2149 COMMAND_EXEC, "start ETM trace collection");
2150 register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
2151 COMMAND_EXEC, "stop ETM trace collection");
2152
2153 register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
2154 COMMAND_EXEC, "anaylze collected ETM trace");
2155
2156 register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
2157 COMMAND_EXEC, "load image from <file> [base address]");
2158
2159 register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
2160 COMMAND_EXEC, "dump captured trace data <file>");
2161 register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
2162 COMMAND_EXEC, "load trace data for analysis <file>");
2163
2164 return ERROR_OK;
2165 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)