1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "arm_disassembler.h"
31 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
33 * ETM modules collect instruction and/or data trace information, compress
34 * it, and transfer it to a debugging host through either a (buffered) trace
35 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
37 * There are several generations of these modules. Original versions have
38 * JTAG access through a dedicated scan chain. Recent versions have added
39 * access via coprocessor instructions, memory addressing, and the ARM Debug
40 * Interface v5 (ADIv5); and phased out direct JTAG access.
42 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
43 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
44 * implying non-JTAG connectivity options.
46 * Relevant documentation includes:
47 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
48 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
49 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
52 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
62 uint8_t size
; /* low-N of 32 bits */
63 uint8_t mode
; /* RO, WO, RW */
64 uint8_t bcd_vers
; /* 1.0, 2.0, etc */
69 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
70 * (Or on some processors, through coprocessor operations.)
71 * Newer versions of ETM make some W/O registers R/W, and
72 * provide definitions for some previously-unused bits.
75 /* core registers used to version/configure the ETM */
76 static const struct etm_reg_info etm_core
[] = {
77 /* NOTE: we "know" the order here ... */
78 { ETM_CONFIG
, 32, RO
, 0x10, "ETM_config", },
79 { ETM_ID
, 32, RO
, 0x20, "ETM_id", },
82 /* basic registers that are always there given the right ETM version */
83 static const struct etm_reg_info etm_basic
[] = {
84 /* ETM Trace Registers */
85 { ETM_CTRL
, 32, RW
, 0x10, "ETM_ctrl", },
86 { ETM_TRIG_EVENT
, 17, WO
, 0x10, "ETM_trig_event", },
87 { ETM_ASIC_CTRL
, 8, WO
, 0x10, "ETM_asic_ctrl", },
88 { ETM_STATUS
, 3, RO
, 0x11, "ETM_status", },
89 { ETM_SYS_CONFIG
, 9, RO
, 0x12, "ETM_sys_config", },
91 /* TraceEnable configuration */
92 { ETM_TRACE_RESOURCE_CTRL
, 32, WO
, 0x12, "ETM_trace_resource_ctrl", },
93 { ETM_TRACE_EN_CTRL2
, 16, WO
, 0x12, "ETM_trace_en_ctrl2", },
94 { ETM_TRACE_EN_EVENT
, 17, WO
, 0x10, "ETM_trace_en_event", },
95 { ETM_TRACE_EN_CTRL1
, 26, WO
, 0x10, "ETM_trace_en_ctrl1", },
97 /* ViewData configuration (data trace) */
98 { ETM_VIEWDATA_EVENT
, 17, WO
, 0x10, "ETM_viewdata_event", },
99 { ETM_VIEWDATA_CTRL1
, 32, WO
, 0x10, "ETM_viewdata_ctrl1", },
100 { ETM_VIEWDATA_CTRL2
, 32, WO
, 0x10, "ETM_viewdata_ctrl2", },
101 { ETM_VIEWDATA_CTRL3
, 17, WO
, 0x10, "ETM_viewdata_ctrl3", },
103 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
105 { 0x78, 12, WO
, 0x20, "ETM_sync_freq", },
106 { 0x7a, 22, RO
, 0x31, "ETM_config_code_ext", },
107 { 0x7b, 32, WO
, 0x31, "ETM_ext_input_select", },
108 { 0x7c, 32, WO
, 0x34, "ETM_trace_start_stop", },
109 { 0x7d, 8, WO
, 0x34, "ETM_behavior_control", },
112 static const struct etm_reg_info etm_fifofull
[] = {
113 /* FIFOFULL configuration */
114 { ETM_FIFOFULL_REGION
, 25, WO
, 0x10, "ETM_fifofull_region", },
115 { ETM_FIFOFULL_LEVEL
, 8, WO
, 0x10, "ETM_fifofull_level", },
118 static const struct etm_reg_info etm_addr_comp
[] = {
119 /* Address comparator register pairs */
120 #define ADDR_COMPARATOR(i) \
121 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
122 "ETM_addr_" #i "_comparator_value", }, \
123 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
124 "ETM_addr_" #i "_access_type", }
142 #undef ADDR_COMPARATOR
145 static const struct etm_reg_info etm_data_comp
[] = {
146 /* Data Value Comparators (NOTE: odd addresses are reserved) */
147 #define DATA_COMPARATOR(i) \
148 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
149 "ETM_data_" #i "_comparator_value", }, \
150 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
151 "ETM_data_" #i "_comparator_mask", }
160 #undef DATA_COMPARATOR
163 static const struct etm_reg_info etm_counters
[] = {
164 #define ETM_COUNTER(i) \
165 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
166 "ETM_counter_" #i "_reload_value", }, \
167 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
168 "ETM_counter_" #i "_enable", }, \
169 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
170 "ETM_counter_" #i "_reload_event", }, \
171 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
172 "ETM_counter_" #i "_value", }
180 static const struct etm_reg_info etm_sequencer
[] = {
182 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
183 "ETM_sequencer_event" #i, }
184 ETM_SEQ(0), /* 1->2 */
185 ETM_SEQ(1), /* 2->1 */
186 ETM_SEQ(2), /* 2->3 */
187 ETM_SEQ(3), /* 3->1 */
188 ETM_SEQ(4), /* 3->2 */
189 ETM_SEQ(5), /* 1->3 */
192 { ETM_SEQUENCER_STATE
, 2, RO
, 0x10, "ETM_sequencer_state", },
195 static const struct etm_reg_info etm_outputs
[] = {
196 #define ETM_OUTPUT(i) \
197 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
198 "ETM_external_output" #i, }
208 /* registers from 0x6c..0x7f were added after ETMv1.3 */
210 /* Context ID Comparators */
211 { 0x6c, 32, RO
, 0x20, "ETM_contextid_comparator_value1", }
212 { 0x6d, 32, RO
, 0x20, "ETM_contextid_comparator_value2", }
213 { 0x6e, 32, RO
, 0x20, "ETM_contextid_comparator_value3", }
214 { 0x6f, 32, RO
, 0x20, "ETM_contextid_comparator_mask", }
217 static int etm_reg_arch_type
= -1;
219 static int etm_get_reg(reg_t
*reg
);
220 static int etm_read_reg_w_check(reg_t
*reg
,
221 uint8_t* check_value
, uint8_t* check_mask
);
222 static int etm_register_user_commands(struct command_context_s
*cmd_ctx
);
223 static int etm_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
);
224 static int etm_write_reg(reg_t
*reg
, uint32_t value
);
226 static command_t
*etm_cmd
;
229 /* Look up register by ID ... most ETM instances only
230 * support a subset of the possible registers.
232 static reg_t
*etm_reg_lookup(etm_context_t
*etm_ctx
, unsigned id
)
234 reg_cache_t
*cache
= etm_ctx
->reg_cache
;
237 for (i
= 0; i
< cache
->num_regs
; i
++) {
238 struct etm_reg_s
*reg
= cache
->reg_list
[i
].arch_info
;
240 if (reg
->reg_info
->addr
== id
)
241 return &cache
->reg_list
[i
];
244 /* caller asking for nonexistent register is a bug! */
245 /* REVISIT say which of the N targets was involved */
246 LOG_ERROR("ETM: register 0x%02x not available", id
);
250 static void etm_reg_add(unsigned bcd_vers
, arm_jtag_t
*jtag_info
,
251 reg_cache_t
*cache
, etm_reg_t
*ereg
,
252 const struct etm_reg_info
*r
, unsigned nreg
)
254 reg_t
*reg
= cache
->reg_list
;
256 reg
+= cache
->num_regs
;
257 ereg
+= cache
->num_regs
;
259 /* add up to "nreg" registers from "r", if supported by this
260 * version of the ETM, to the specified cache.
262 for (; nreg
--; r
++) {
264 /* this ETM may be too old to have some registers */
265 if (r
->bcd_vers
> bcd_vers
)
270 reg
->value
= &ereg
->value
;
271 reg
->arch_info
= ereg
;
272 reg
->arch_type
= etm_reg_arch_type
;
277 ereg
->jtag_info
= jtag_info
;
282 reg_cache_t
*etm_build_reg_cache(target_t
*target
,
283 arm_jtag_t
*jtag_info
, etm_context_t
*etm_ctx
)
285 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
286 reg_t
*reg_list
= NULL
;
287 etm_reg_t
*arch_info
= NULL
;
288 unsigned bcd_vers
, config
;
290 /* register a register arch-type for etm registers only once */
291 if (etm_reg_arch_type
== -1)
292 etm_reg_arch_type
= register_reg_arch_type(etm_get_reg
,
295 /* the actual registers are kept in two arrays */
296 reg_list
= calloc(128, sizeof(reg_t
));
297 arch_info
= calloc(128, sizeof(etm_reg_t
));
299 /* fill in values for the reg cache */
300 reg_cache
->name
= "etm registers";
301 reg_cache
->next
= NULL
;
302 reg_cache
->reg_list
= reg_list
;
303 reg_cache
->num_regs
= 0;
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
308 etm_reg_add(0x10, jtag_info
, reg_cache
, arch_info
,
311 etm_get_reg(reg_list
);
312 etm_ctx
->config
= buf_get_u32((void *)&arch_info
->value
, 0, 32);
313 config
= etm_ctx
->config
;
315 /* figure ETM version then add base registers */
316 if (config
& (1 << 31)) {
318 LOG_WARNING("ETMv2+ support is incomplete");
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
325 etm_reg_add(0x20, jtag_info
, reg_cache
, arch_info
,
327 etm_get_reg(reg_list
+ 1);
328 etm_ctx
->id
= buf_get_u32(
329 (void *)&arch_info
[1].value
, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx
->id
);
331 bcd_vers
= 0x10 + (((etm_ctx
->id
) >> 4) & 0xff);
334 switch (config
>> 28) {
351 LOG_WARNING("Bad ETMv1 protocol %d", config
>> 28);
358 etm_ctx
->bcd_vers
= bcd_vers
;
359 LOG_INFO("ETM v%d.%d", bcd_vers
>> 4, bcd_vers
& 0xf);
361 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
362 etm_basic
, ARRAY_SIZE(etm_basic
));
364 /* address and data comparators; counters; outputs */
365 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
366 etm_addr_comp
, 4 * (0x0f & (config
>> 0)));
367 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
368 etm_data_comp
, 2 * (0x0f & (config
>> 4)));
369 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
370 etm_counters
, 4 * (0x07 & (config
>> 13)));
371 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
372 etm_outputs
, (0x07 & (config
>> 20)));
374 /* FIFOFULL presence is optional
375 * REVISIT for ETMv1.2 and later, don't bother adding this
376 * unless ETM_SYS_CONFIG says it's also *supported* ...
378 if (config
& (1 << 23))
379 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
380 etm_fifofull
, ARRAY_SIZE(etm_fifofull
));
382 /* sequencer is optional (for state-dependant triggering) */
383 if (config
& (1 << 16))
384 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
385 etm_sequencer
, ARRAY_SIZE(etm_sequencer
));
387 /* REVISIT could realloc and likely save half the memory
388 * in the two chunks we allocated...
391 /* the ETM might have an ETB connected */
392 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0)
394 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
398 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
405 reg_cache
->next
= etb_build_reg_cache(etb
);
407 etb
->reg_cache
= reg_cache
->next
;
410 etm_ctx
->reg_cache
= reg_cache
;
414 static int etm_read_reg(reg_t
*reg
)
416 return etm_read_reg_w_check(reg
, NULL
, NULL
);
419 static int etm_store_reg(reg_t
*reg
)
421 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
424 int etm_setup(target_t
*target
)
427 uint32_t etm_ctrl_value
;
428 struct arm
*arm
= target_to_arm(target
);
429 etm_context_t
*etm_ctx
= arm
->etm
;
432 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg
);
438 etm_ctrl_value
= buf_get_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
);
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value
&= ~0x1;
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
446 etm_ctrl_value
= (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
449 & ~ETM_PORT_CLOCK_MASK
)
452 buf_set_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
, etm_ctrl_value
);
453 etm_store_reg(etm_ctrl_reg
);
455 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
458 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
459 * verify that those width and mode settings are OK ...
462 if ((retval
= etm_ctx
->capture_driver
->init(etm_ctx
)) != ERROR_OK
)
464 LOG_ERROR("ETM capture driver initialization failed");
470 static int etm_get_reg(reg_t
*reg
)
474 if ((retval
= etm_read_reg(reg
)) != ERROR_OK
)
476 LOG_ERROR("BUG: error scheduling etm register read");
480 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
482 LOG_ERROR("register read failed");
489 static int etm_read_reg_w_check(reg_t
*reg
,
490 uint8_t* check_value
, uint8_t* check_mask
)
492 etm_reg_t
*etm_reg
= reg
->arch_info
;
493 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
494 uint8_t reg_addr
= r
->addr
& 0x7f;
495 scan_field_t fields
[3];
497 if (etm_reg
->reg_info
->mode
== WO
) {
498 LOG_ERROR("BUG: can't read write-only register %s", r
->name
);
499 return ERROR_INVALID_ARGUMENTS
;
502 LOG_DEBUG("%s (%u)", r
->name
, reg_addr
);
504 jtag_set_end_state(TAP_IDLE
);
505 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
506 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
508 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
509 fields
[0].num_bits
= 32;
510 fields
[0].out_value
= reg
->value
;
511 fields
[0].in_value
= NULL
;
512 fields
[0].check_value
= NULL
;
513 fields
[0].check_mask
= NULL
;
515 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
516 fields
[1].num_bits
= 7;
517 fields
[1].out_value
= malloc(1);
518 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
519 fields
[1].in_value
= NULL
;
520 fields
[1].check_value
= NULL
;
521 fields
[1].check_mask
= NULL
;
523 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
524 fields
[2].num_bits
= 1;
525 fields
[2].out_value
= malloc(1);
526 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
527 fields
[2].in_value
= NULL
;
528 fields
[2].check_value
= NULL
;
529 fields
[2].check_mask
= NULL
;
531 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
533 fields
[0].in_value
= reg
->value
;
534 fields
[0].check_value
= check_value
;
535 fields
[0].check_mask
= check_mask
;
537 jtag_add_dr_scan_check(3, fields
, jtag_get_end_state());
539 free(fields
[1].out_value
);
540 free(fields
[2].out_value
);
545 static int etm_set_reg(reg_t
*reg
, uint32_t value
)
549 if ((retval
= etm_write_reg(reg
, value
)) != ERROR_OK
)
551 LOG_ERROR("BUG: error scheduling etm register write");
555 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
562 static int etm_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
)
566 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
568 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
570 LOG_ERROR("register write failed");
576 static int etm_write_reg(reg_t
*reg
, uint32_t value
)
578 etm_reg_t
*etm_reg
= reg
->arch_info
;
579 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
580 uint8_t reg_addr
= r
->addr
& 0x7f;
581 scan_field_t fields
[3];
583 if (etm_reg
->reg_info
->mode
== RO
) {
584 LOG_ERROR("BUG: can't write read--only register %s", r
->name
);
585 return ERROR_INVALID_ARGUMENTS
;
588 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32
"", r
->name
, reg_addr
, value
);
590 jtag_set_end_state(TAP_IDLE
);
591 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
592 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
594 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
595 fields
[0].num_bits
= 32;
597 fields
[0].out_value
= tmp1
;
598 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
599 fields
[0].in_value
= NULL
;
601 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
602 fields
[1].num_bits
= 7;
604 fields
[1].out_value
= &tmp2
;
605 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
606 fields
[1].in_value
= NULL
;
608 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
609 fields
[2].num_bits
= 1;
611 fields
[2].out_value
= &tmp3
;
612 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
613 fields
[2].in_value
= NULL
;
615 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
621 /* ETM trace analysis functionality
624 extern etm_capture_driver_t etm_dummy_capture_driver
;
625 #if BUILD_OOCD_TRACE == 1
626 extern etm_capture_driver_t oocd_trace_capture_driver
;
629 static etm_capture_driver_t
*etm_capture_drivers
[] =
632 &etm_dummy_capture_driver
,
633 #if BUILD_OOCD_TRACE == 1
634 &oocd_trace_capture_driver
,
639 static int etm_read_instruction(etm_context_t
*ctx
, arm_instruction_t
*instruction
)
648 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
650 /* search for the section the current instruction belongs to */
651 for (i
= 0; i
< ctx
->image
->num_sections
; i
++)
653 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
654 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
> ctx
->current_pc
))
663 /* current instruction couldn't be found in the image */
664 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
667 if (ctx
->core_state
== ARMV4_5_STATE_ARM
)
670 if ((retval
= image_read_section(ctx
->image
, section
,
671 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
672 4, buf
, &size_read
)) != ERROR_OK
)
674 LOG_ERROR("error while reading instruction: %i", retval
);
675 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
677 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
678 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
680 else if (ctx
->core_state
== ARMV4_5_STATE_THUMB
)
683 if ((retval
= image_read_section(ctx
->image
, section
,
684 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
685 2, buf
, &size_read
)) != ERROR_OK
)
687 LOG_ERROR("error while reading instruction: %i", retval
);
688 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
690 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
691 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
693 else if (ctx
->core_state
== ARMV4_5_STATE_JAZELLE
)
695 LOG_ERROR("BUG: tracing of jazelle code not supported");
700 LOG_ERROR("BUG: unknown core state encountered");
707 static int etmv1_next_packet(etm_context_t
*ctx
, uint8_t *packet
, int apo
)
709 while (ctx
->data_index
< ctx
->trace_depth
)
711 /* if the caller specified an address packet offset, skip until the
712 * we reach the n-th cycle marked with tracesync */
715 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
726 /* no tracedata output during a TD cycle
727 * or in a trigger cycle */
728 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
729 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
))
736 if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
)
738 if (ctx
->data_half
== 0)
740 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
745 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
750 else if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
752 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
757 /* on a 4-bit port, a packet will be output during two consecutive cycles */
758 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
761 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
762 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
763 ctx
->data_index
+= 2;
772 static int etmv1_branch_address(etm_context_t
*ctx
)
780 /* quit analysis if less than two cycles are left in the trace
781 * because we can't extract the APO */
782 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
785 /* a BE could be output during an APO cycle, skip the current
786 * and continue with the new one */
787 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
789 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
792 /* address packet offset encoded in the next two cycles' pipestat bits */
793 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
794 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
796 /* count number of tracesync cycles between current pipe_index and data_index
797 * i.e. the number of tracesyncs that data_index already passed by
798 * to subtract them from the APO */
799 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++)
801 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
805 /* extract up to four 7-bit packets */
807 if ((retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0)) != 0)
809 ctx
->last_branch
&= ~(0x7f << shift
);
810 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
812 } while ((packet
& 0x80) && (shift
< 28));
814 /* one last packet holding 4 bits of the address, plus the branch reason code */
815 if ((shift
== 28) && (packet
& 0x80))
817 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
819 ctx
->last_branch
&= 0x0fffffff;
820 ctx
->last_branch
|= (packet
& 0x0f) << 28;
821 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
826 ctx
->last_branch_reason
= 0;
834 /* if a full address was output, we might have branched into Jazelle state */
835 if ((shift
== 32) && (packet
& 0x80))
837 ctx
->core_state
= ARMV4_5_STATE_JAZELLE
;
841 /* if we didn't branch into Jazelle state, the current processor state is
842 * encoded in bit 0 of the branch target address */
843 if (ctx
->last_branch
& 0x1)
845 ctx
->core_state
= ARMV4_5_STATE_THUMB
;
846 ctx
->last_branch
&= ~0x1;
850 ctx
->core_state
= ARMV4_5_STATE_ARM
;
851 ctx
->last_branch
&= ~0x3;
858 static int etmv1_data(etm_context_t
*ctx
, int size
, uint32_t *data
)
864 for (j
= 0; j
< size
; j
++)
866 if ((retval
= etmv1_next_packet(ctx
, &buf
[j
], 0)) != 0)
872 LOG_ERROR("TODO: add support for 64-bit values");
876 *data
= target_buffer_get_u32(ctx
->target
, buf
);
878 *data
= target_buffer_get_u16(ctx
->target
, buf
);
887 static int etmv1_analyze_trace(etm_context_t
*ctx
, struct command_context_s
*cmd_ctx
)
890 arm_instruction_t instruction
;
892 /* read the trace data if it wasn't read already */
893 if (ctx
->trace_depth
== 0)
894 ctx
->capture_driver
->read_trace(ctx
);
896 /* start at the beginning of the captured trace */
901 /* neither the PC nor the data pointer are valid */
905 while (ctx
->pipe_index
< ctx
->trace_depth
)
907 uint8_t pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
908 uint32_t next_pc
= ctx
->current_pc
;
909 uint32_t old_data_index
= ctx
->data_index
;
910 uint32_t old_data_half
= ctx
->data_half
;
911 uint32_t old_index
= ctx
->pipe_index
;
912 uint32_t last_instruction
= ctx
->last_instruction
;
914 int current_pc_ok
= ctx
->pc_ok
;
916 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
918 command_print(cmd_ctx
, "--- trigger ---");
921 /* instructions execute in IE/D or BE/D cycles */
922 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
923 ctx
->last_instruction
= ctx
->pipe_index
;
925 /* if we don't have a valid pc skip until we reach an indirect branch */
926 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
))
932 /* any indirect branch could have interrupted instruction flow
933 * - the branch reason code could indicate a trace discontinuity
934 * - a branch to the exception vectors indicates an exception
936 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
))
938 /* backup current data index, to be able to consume the branch address
939 * before examining data address and values
941 old_data_index
= ctx
->data_index
;
942 old_data_half
= ctx
->data_half
;
944 ctx
->last_instruction
= ctx
->pipe_index
;
946 if ((retval
= etmv1_branch_address(ctx
)) != 0)
948 /* negative return value from etmv1_branch_address means we ran out of packets,
949 * quit analysing the trace */
953 /* a positive return values means the current branch was abandoned,
954 * and a new branch was encountered in cycle ctx->pipe_index + retval;
956 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
957 ctx
->pipe_index
+= retval
;
961 /* skip over APO cycles */
962 ctx
->pipe_index
+= 2;
964 switch (ctx
->last_branch_reason
)
966 case 0x0: /* normal PC change */
967 next_pc
= ctx
->last_branch
;
969 case 0x1: /* tracing enabled */
970 command_print(cmd_ctx
, "--- tracing enabled at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
971 ctx
->current_pc
= ctx
->last_branch
;
975 case 0x2: /* trace restarted after FIFO overflow */
976 command_print(cmd_ctx
, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
977 ctx
->current_pc
= ctx
->last_branch
;
981 case 0x3: /* exit from debug state */
982 command_print(cmd_ctx
, "--- exit from debug state at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
983 ctx
->current_pc
= ctx
->last_branch
;
987 case 0x4: /* periodic synchronization point */
988 next_pc
= ctx
->last_branch
;
989 /* if we had no valid PC prior to this synchronization point,
990 * we have to move on with the next trace cycle
994 command_print(cmd_ctx
, "--- periodic synchronization point at 0x%8.8" PRIx32
" ---", next_pc
);
995 ctx
->current_pc
= next_pc
;
1000 default: /* reserved */
1001 LOG_ERROR("BUG: branch reason code 0x%" PRIx32
" is reserved", ctx
->last_branch_reason
);
1005 /* if we got here the branch was a normal PC change
1006 * (or a periodic synchronization point, which means the same for that matter)
1007 * if we didn't accquire a complete PC continue with the next cycle
1012 /* indirect branch to the exception vector means an exception occured */
1013 if ((ctx
->last_branch
<= 0x20)
1014 || ((ctx
->last_branch
>= 0xffff0000) && (ctx
->last_branch
<= 0xffff0020)))
1016 if ((ctx
->last_branch
& 0xff) == 0x10)
1018 command_print(cmd_ctx
, "data abort");
1022 command_print(cmd_ctx
, "exception vector 0x%2.2" PRIx32
"", ctx
->last_branch
);
1023 ctx
->current_pc
= ctx
->last_branch
;
1030 /* an instruction was executed (or not, depending on the condition flags)
1031 * retrieve it from the image for displaying */
1032 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
1033 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
1034 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4))))
1036 if ((retval
= etm_read_instruction(ctx
, &instruction
)) != ERROR_OK
)
1038 /* can't continue tracing with no image available */
1039 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
1043 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
1045 /* TODO: handle incomplete images
1046 * for now we just quit the analsysis*/
1051 cycles
= old_index
- last_instruction
;
1054 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
))
1056 uint32_t new_data_index
= ctx
->data_index
;
1057 uint32_t new_data_half
= ctx
->data_half
;
1059 /* in case of a branch with data, the branch target address was consumed before
1060 * we temporarily go back to the saved data index */
1061 if (pipestat
== STAT_BD
)
1063 ctx
->data_index
= old_data_index
;
1064 ctx
->data_half
= old_data_half
;
1067 if (ctx
->tracemode
& ETMV1_TRACE_ADDR
)
1073 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
1074 return ERROR_ETM_ANALYSIS_FAILED
;
1075 ctx
->last_ptr
&= ~(0x7f << shift
);
1076 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
1078 } while ((packet
& 0x80) && (shift
< 32));
1085 command_print(cmd_ctx
, "address: 0x%8.8" PRIx32
"", ctx
->last_ptr
);
1089 if (ctx
->tracemode
& ETMV1_TRACE_DATA
)
1091 if ((instruction
.type
== ARM_LDM
) || (instruction
.type
== ARM_STM
))
1094 for (i
= 0; i
< 16; i
++)
1096 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
1099 if (etmv1_data(ctx
, 4, &data
) != 0)
1100 return ERROR_ETM_ANALYSIS_FAILED
;
1101 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1105 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_STRH
))
1108 if (etmv1_data(ctx
, arm_access_size(&instruction
), &data
) != 0)
1109 return ERROR_ETM_ANALYSIS_FAILED
;
1110 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1114 /* restore data index after consuming BD address and data */
1115 if (pipestat
== STAT_BD
)
1117 ctx
->data_index
= new_data_index
;
1118 ctx
->data_half
= new_data_half
;
1123 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
1125 if (((instruction
.type
== ARM_B
) ||
1126 (instruction
.type
== ARM_BL
) ||
1127 (instruction
.type
== ARM_BLX
)) &&
1128 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff))
1130 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
1134 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
1137 else if (pipestat
== STAT_IN
)
1139 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
1142 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
))
1144 char cycles_text
[32] = "";
1146 /* if the trace was captured with cycle accurate tracing enabled,
1147 * output the number of cycles since the last executed instruction
1149 if (ctx
->tracemode
& ETMV1_CYCLE_ACCURATE
)
1151 snprintf(cycles_text
, 32, " (%i %s)",
1153 (cycles
== 1) ? "cycle" : "cycles");
1156 command_print(cmd_ctx
, "%s%s%s",
1158 (pipestat
== STAT_IN
) ? " (not executed)" : "",
1161 ctx
->current_pc
= next_pc
;
1163 /* packets for an instruction don't start on or before the preceding
1164 * functional pipestat (i.e. other than WT or TD)
1166 if (ctx
->data_index
<= ctx
->pipe_index
)
1168 ctx
->data_index
= ctx
->pipe_index
+ 1;
1173 ctx
->pipe_index
+= 1;
1179 static int handle_etm_tracemode_command_update(
1180 struct command_context_s
*cmd_ctx
,
1181 char **args
, etmv1_tracemode_t
*mode
)
1183 etmv1_tracemode_t tracemode
;
1185 /* what parts of data access are traced? */
1186 if (strcmp(args
[0], "none") == 0)
1187 tracemode
= ETMV1_TRACE_NONE
;
1188 else if (strcmp(args
[0], "data") == 0)
1189 tracemode
= ETMV1_TRACE_DATA
;
1190 else if (strcmp(args
[0], "address") == 0)
1191 tracemode
= ETMV1_TRACE_ADDR
;
1192 else if (strcmp(args
[0], "all") == 0)
1193 tracemode
= ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
;
1196 command_print(cmd_ctx
, "invalid option '%s'", args
[0]);
1197 return ERROR_INVALID_ARGUMENTS
;
1201 COMMAND_PARSE_NUMBER(u8
, args
[1], context_id
);
1205 tracemode
|= ETMV1_CONTEXTID_NONE
;
1208 tracemode
|= ETMV1_CONTEXTID_8
;
1211 tracemode
|= ETMV1_CONTEXTID_16
;
1214 tracemode
|= ETMV1_CONTEXTID_32
;
1217 command_print(cmd_ctx
, "invalid option '%s'", args
[1]);
1218 return ERROR_INVALID_ARGUMENTS
;
1221 if (strcmp(args
[2], "enable") == 0)
1222 tracemode
|= ETMV1_CYCLE_ACCURATE
;
1223 else if (strcmp(args
[2], "disable") == 0)
1227 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1228 return ERROR_INVALID_ARGUMENTS
;
1231 if (strcmp(args
[3], "enable") == 0)
1232 tracemode
|= ETMV1_BRANCH_OUTPUT
;
1233 else if (strcmp(args
[3], "disable") == 0)
1237 command_print(cmd_ctx
, "invalid option '%s'", args
[3]);
1238 return ERROR_INVALID_ARGUMENTS
;
1242 * - CPRT tracing (coprocessor register transfers)
1243 * - debug request (causes debug entry on trigger)
1244 * - stall on FIFOFULL (preventing tracedata lossage)
1251 COMMAND_HANDLER(handle_etm_tracemode_command
)
1253 target_t
*target
= get_current_target(cmd_ctx
);
1254 struct arm
*arm
= target_to_arm(target
);
1258 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1264 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1268 etmv1_tracemode_t tracemode
= etm
->tracemode
;
1275 handle_etm_tracemode_command_update(cmd_ctx
, args
, &tracemode
);
1278 command_print(cmd_ctx
, "usage: configure trace mode "
1279 "<none | data | address | all> "
1280 "<context id bits> <cycle accurate> <branch output>");
1285 * todo: fail if parameters were invalid for this hardware,
1286 * or couldn't be written; display actual hardware state...
1289 command_print(cmd_ctx
, "current tracemode configuration:");
1291 switch (tracemode
& ETMV1_TRACE_MASK
)
1293 case ETMV1_TRACE_NONE
:
1294 command_print(cmd_ctx
, "data tracing: none");
1296 case ETMV1_TRACE_DATA
:
1297 command_print(cmd_ctx
, "data tracing: data only");
1299 case ETMV1_TRACE_ADDR
:
1300 command_print(cmd_ctx
, "data tracing: address only");
1302 case ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
:
1303 command_print(cmd_ctx
, "data tracing: address and data");
1307 switch (tracemode
& ETMV1_CONTEXTID_MASK
)
1309 case ETMV1_CONTEXTID_NONE
:
1310 command_print(cmd_ctx
, "contextid tracing: none");
1312 case ETMV1_CONTEXTID_8
:
1313 command_print(cmd_ctx
, "contextid tracing: 8 bit");
1315 case ETMV1_CONTEXTID_16
:
1316 command_print(cmd_ctx
, "contextid tracing: 16 bit");
1318 case ETMV1_CONTEXTID_32
:
1319 command_print(cmd_ctx
, "contextid tracing: 32 bit");
1323 if (tracemode
& ETMV1_CYCLE_ACCURATE
)
1325 command_print(cmd_ctx
, "cycle-accurate tracing enabled");
1329 command_print(cmd_ctx
, "cycle-accurate tracing disabled");
1332 if (tracemode
& ETMV1_BRANCH_OUTPUT
)
1334 command_print(cmd_ctx
, "full branch address output enabled");
1338 command_print(cmd_ctx
, "full branch address output disabled");
1341 /* only update ETM_CTRL register if tracemode changed */
1342 if (etm
->tracemode
!= tracemode
)
1344 reg_t
*etm_ctrl_reg
;
1346 etm_ctrl_reg
= etm_reg_lookup(etm
, ETM_CTRL
);
1350 etm_get_reg(etm_ctrl_reg
);
1352 buf_set_u32(etm_ctrl_reg
->value
, 2, 2, tracemode
& ETMV1_TRACE_MASK
);
1353 buf_set_u32(etm_ctrl_reg
->value
, 14, 2, (tracemode
& ETMV1_CONTEXTID_MASK
) >> 4);
1354 buf_set_u32(etm_ctrl_reg
->value
, 12, 1, (tracemode
& ETMV1_CYCLE_ACCURATE
) >> 8);
1355 buf_set_u32(etm_ctrl_reg
->value
, 8, 1, (tracemode
& ETMV1_BRANCH_OUTPUT
) >> 9);
1356 etm_store_reg(etm_ctrl_reg
);
1358 etm
->tracemode
= tracemode
;
1360 /* invalidate old trace data */
1361 etm
->capture_status
= TRACE_IDLE
;
1362 if (etm
->trace_depth
> 0)
1364 free(etm
->trace_data
);
1365 etm
->trace_data
= NULL
;
1367 etm
->trace_depth
= 0;
1373 COMMAND_HANDLER(handle_etm_config_command
)
1377 etm_portmode_t portmode
= 0x0;
1378 struct etm
*etm_ctx
;
1382 return ERROR_COMMAND_SYNTAX_ERROR
;
1384 target
= get_target(args
[0]);
1387 LOG_ERROR("target '%s' not defined", args
[0]);
1391 arm
= target_to_arm(target
);
1393 command_print(cmd_ctx
, "target '%s' is '%s'; not an ARM",
1394 target
->cmd_name
, target_get_name(target
));
1398 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1399 * version we'll be using!! -- so we can't know how to validate
1400 * params yet. "etm config" should likely be *AFTER* hookup...
1402 * - Many more widths might be supported ... and we can easily
1403 * check whether our setting "took".
1405 * - The "clock" and "mode" bits are interpreted differently.
1406 * See ARM IHI 0014O table 2-17 for the old behavior, and
1407 * table 2-18 for the new. With ETB it's best to specify
1411 COMMAND_PARSE_NUMBER(u8
, args
[1], port_width
);
1414 /* before ETMv3.0 */
1416 portmode
|= ETM_PORT_4BIT
;
1419 portmode
|= ETM_PORT_8BIT
;
1422 portmode
|= ETM_PORT_16BIT
;
1424 /* ETMv3.0 and later*/
1426 portmode
|= ETM_PORT_24BIT
;
1429 portmode
|= ETM_PORT_32BIT
;
1432 portmode
|= ETM_PORT_48BIT
;
1435 portmode
|= ETM_PORT_64BIT
;
1438 portmode
|= ETM_PORT_1BIT
;
1441 portmode
|= ETM_PORT_2BIT
;
1444 command_print(cmd_ctx
,
1445 "unsupported ETM port width '%s'", args
[1]);
1449 if (strcmp("normal", args
[2]) == 0)
1451 portmode
|= ETM_PORT_NORMAL
;
1453 else if (strcmp("multiplexed", args
[2]) == 0)
1455 portmode
|= ETM_PORT_MUXED
;
1457 else if (strcmp("demultiplexed", args
[2]) == 0)
1459 portmode
|= ETM_PORT_DEMUXED
;
1463 command_print(cmd_ctx
, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args
[2]);
1467 if (strcmp("half", args
[3]) == 0)
1469 portmode
|= ETM_PORT_HALF_CLOCK
;
1471 else if (strcmp("full", args
[3]) == 0)
1473 portmode
|= ETM_PORT_FULL_CLOCK
;
1477 command_print(cmd_ctx
, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args
[3]);
1481 etm_ctx
= calloc(1, sizeof(etm_context_t
));
1483 LOG_DEBUG("out of memory");
1487 for (i
= 0; etm_capture_drivers
[i
]; i
++)
1489 if (strcmp(args
[4], etm_capture_drivers
[i
]->name
) == 0)
1492 if ((retval
= etm_capture_drivers
[i
]->register_commands(cmd_ctx
)) != ERROR_OK
)
1498 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1504 if (!etm_capture_drivers
[i
])
1506 /* no supported capture driver found, don't register an ETM */
1508 LOG_ERROR("trace capture driver '%s' not found", args
[4]);
1512 etm_ctx
->target
= target
;
1513 etm_ctx
->trigger_percent
= 50;
1514 etm_ctx
->trace_data
= NULL
;
1515 etm_ctx
->portmode
= portmode
;
1516 etm_ctx
->core_state
= ARMV4_5_STATE_ARM
;
1520 return etm_register_user_commands(cmd_ctx
);
1523 COMMAND_HANDLER(handle_etm_info_command
)
1528 reg_t
*etm_sys_config_reg
;
1532 target
= get_current_target(cmd_ctx
);
1533 arm
= target_to_arm(target
);
1536 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1543 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1547 command_print(cmd_ctx
, "ETM v%d.%d",
1548 etm
->bcd_vers
>> 4, etm
->bcd_vers
& 0xf);
1549 command_print(cmd_ctx
, "pairs of address comparators: %i",
1550 (int) (etm
->config
>> 0) & 0x0f);
1551 command_print(cmd_ctx
, "data comparators: %i",
1552 (int) (etm
->config
>> 4) & 0x0f);
1553 command_print(cmd_ctx
, "memory map decoders: %i",
1554 (int) (etm
->config
>> 8) & 0x1f);
1555 command_print(cmd_ctx
, "number of counters: %i",
1556 (int) (etm
->config
>> 13) & 0x07);
1557 command_print(cmd_ctx
, "sequencer %spresent",
1558 (int) (etm
->config
& (1 << 16)) ? "" : "not ");
1559 command_print(cmd_ctx
, "number of ext. inputs: %i",
1560 (int) (etm
->config
>> 17) & 0x07);
1561 command_print(cmd_ctx
, "number of ext. outputs: %i",
1562 (int) (etm
->config
>> 20) & 0x07);
1563 command_print(cmd_ctx
, "FIFO full %spresent",
1564 (int) (etm
->config
& (1 << 23)) ? "" : "not ");
1565 if (etm
->bcd_vers
< 0x20)
1566 command_print(cmd_ctx
, "protocol version: %i",
1567 (int) (etm
->config
>> 28) & 0x07);
1569 command_print(cmd_ctx
,
1570 "coprocessor and memory access %ssupported",
1571 (etm
->config
& (1 << 26)) ? "" : "not ");
1572 command_print(cmd_ctx
, "trace start/stop %spresent",
1573 (etm
->config
& (1 << 26)) ? "" : "not ");
1574 command_print(cmd_ctx
, "number of context comparators: %i",
1575 (int) (etm
->config
>> 24) & 0x03);
1578 /* SYS_CONFIG isn't present before ETMv1.2 */
1579 etm_sys_config_reg
= etm_reg_lookup(etm
, ETM_SYS_CONFIG
);
1580 if (!etm_sys_config_reg
)
1583 etm_get_reg(etm_sys_config_reg
);
1584 config
= buf_get_u32(etm_sys_config_reg
->value
, 0, 32);
1586 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config
);
1588 max_port_size
= config
& 0x7;
1589 if (etm
->bcd_vers
>= 0x30)
1590 max_port_size
|= (config
>> 6) & 0x08;
1591 switch (max_port_size
)
1593 /* before ETMv3.0 */
1603 /* ETMv3.0 and later*/
1623 LOG_ERROR("Illegal max_port_size");
1626 command_print(cmd_ctx
, "max. port size: %i", max_port_size
);
1628 if (etm
->bcd_vers
< 0x30) {
1629 command_print(cmd_ctx
, "half-rate clocking %ssupported",
1630 (config
& (1 << 3)) ? "" : "not ");
1631 command_print(cmd_ctx
, "full-rate clocking %ssupported",
1632 (config
& (1 << 4)) ? "" : "not ");
1633 command_print(cmd_ctx
, "normal trace format %ssupported",
1634 (config
& (1 << 5)) ? "" : "not ");
1635 command_print(cmd_ctx
, "multiplex trace format %ssupported",
1636 (config
& (1 << 6)) ? "" : "not ");
1637 command_print(cmd_ctx
, "demultiplex trace format %ssupported",
1638 (config
& (1 << 7)) ? "" : "not ");
1640 /* REVISIT show which size and format are selected ... */
1641 command_print(cmd_ctx
, "current port size %ssupported",
1642 (config
& (1 << 10)) ? "" : "not ");
1643 command_print(cmd_ctx
, "current trace format %ssupported",
1644 (config
& (1 << 11)) ? "" : "not ");
1646 if (etm
->bcd_vers
>= 0x21)
1647 command_print(cmd_ctx
, "fetch comparisons %ssupported",
1648 (config
& (1 << 17)) ? "not " : "");
1649 command_print(cmd_ctx
, "FIFO full %ssupported",
1650 (config
& (1 << 8)) ? "" : "not ");
1655 COMMAND_HANDLER(handle_etm_status_command
)
1660 trace_status_t trace_status
;
1662 target
= get_current_target(cmd_ctx
);
1663 arm
= target_to_arm(target
);
1666 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1673 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1678 if (etm
->bcd_vers
>= 0x11) {
1681 reg
= etm_reg_lookup(etm
, ETM_STATUS
);
1684 if (etm_get_reg(reg
) == ERROR_OK
) {
1685 unsigned s
= buf_get_u32(reg
->value
, 0, reg
->size
);
1687 command_print(cmd_ctx
, "etm: %s%s%s%s",
1688 /* bit(1) == progbit */
1689 (etm
->bcd_vers
>= 0x12)
1691 ? "disabled" : "enabled")
1693 ((s
& (1 << 3)) && etm
->bcd_vers
>= 0x31)
1694 ? " triggered" : "",
1695 ((s
& (1 << 2)) && etm
->bcd_vers
>= 0x12)
1696 ? " start/stop" : "",
1697 ((s
& (1 << 0)) && etm
->bcd_vers
>= 0x11)
1698 ? " untraced-overflow" : "");
1699 } /* else ignore and try showing trace port status */
1702 /* Trace Port Driver status */
1703 trace_status
= etm
->capture_driver
->status(etm
);
1704 if (trace_status
== TRACE_IDLE
)
1706 command_print(cmd_ctx
, "%s: idle", etm
->capture_driver
->name
);
1710 static char *completed
= " completed";
1711 static char *running
= " is running";
1712 static char *overflowed
= ", overflowed";
1713 static char *triggered
= ", triggered";
1715 command_print(cmd_ctx
, "%s: trace collection%s%s%s",
1716 etm
->capture_driver
->name
,
1717 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1718 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1719 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1721 if (etm
->trace_depth
> 0)
1723 command_print(cmd_ctx
, "%i frames of trace data read",
1724 (int)(etm
->trace_depth
));
1731 COMMAND_HANDLER(handle_etm_image_command
)
1735 etm_context_t
*etm_ctx
;
1739 command_print(cmd_ctx
, "usage: etm image <file> [base address] [type]");
1743 target
= get_current_target(cmd_ctx
);
1744 arm
= target_to_arm(target
);
1747 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1754 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1760 image_close(etm_ctx
->image
);
1761 free(etm_ctx
->image
);
1762 command_print(cmd_ctx
, "previously loaded image found and closed");
1765 etm_ctx
->image
= malloc(sizeof(image_t
));
1766 etm_ctx
->image
->base_address_set
= 0;
1767 etm_ctx
->image
->start_address_set
= 0;
1769 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1772 etm_ctx
->image
->base_address_set
= 1;
1773 COMMAND_PARSE_NUMBER(int, args
[1], etm_ctx
->image
->base_address
);
1777 etm_ctx
->image
->base_address_set
= 0;
1780 if (image_open(etm_ctx
->image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
1782 free(etm_ctx
->image
);
1783 etm_ctx
->image
= NULL
;
1790 COMMAND_HANDLER(handle_etm_dump_command
)
1795 etm_context_t
*etm_ctx
;
1800 command_print(cmd_ctx
, "usage: etm dump <file>");
1804 target
= get_current_target(cmd_ctx
);
1805 arm
= target_to_arm(target
);
1808 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1815 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1819 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
)
1821 command_print(cmd_ctx
, "trace capture wasn't enabled, no trace data captured");
1825 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1827 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1828 command_print(cmd_ctx
, "trace capture not completed");
1832 /* read the trace data if it wasn't read already */
1833 if (etm_ctx
->trace_depth
== 0)
1834 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1836 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1841 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1842 fileio_write_u32(&file
, etm_ctx
->portmode
);
1843 fileio_write_u32(&file
, etm_ctx
->tracemode
);
1844 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1846 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1848 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1849 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1850 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1853 fileio_close(&file
);
1858 COMMAND_HANDLER(handle_etm_load_command
)
1863 etm_context_t
*etm_ctx
;
1868 command_print(cmd_ctx
, "usage: etm load <file>");
1872 target
= get_current_target(cmd_ctx
);
1873 arm
= target_to_arm(target
);
1876 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1883 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1887 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1889 command_print(cmd_ctx
, "trace capture running, stop first");
1893 if (fileio_open(&file
, args
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1900 command_print(cmd_ctx
, "size isn't a multiple of 4, no valid trace data");
1901 fileio_close(&file
);
1905 if (etm_ctx
->trace_depth
> 0)
1907 free(etm_ctx
->trace_data
);
1908 etm_ctx
->trace_data
= NULL
;
1913 fileio_read_u32(&file
, &tmp
); etm_ctx
->capture_status
= tmp
;
1914 fileio_read_u32(&file
, &tmp
); etm_ctx
->portmode
= tmp
;
1915 fileio_read_u32(&file
, &tmp
); etm_ctx
->tracemode
= tmp
;
1916 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1918 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
1919 if (etm_ctx
->trace_data
== NULL
)
1921 command_print(cmd_ctx
, "not enough memory to perform operation");
1922 fileio_close(&file
);
1926 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1928 uint32_t pipestat
, packet
, flags
;
1929 fileio_read_u32(&file
, &pipestat
);
1930 fileio_read_u32(&file
, &packet
);
1931 fileio_read_u32(&file
, &flags
);
1932 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1933 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1934 etm_ctx
->trace_data
[i
].flags
= flags
;
1937 fileio_close(&file
);
1942 COMMAND_HANDLER(handle_etm_trigger_percent_command
)
1946 etm_context_t
*etm_ctx
;
1948 target
= get_current_target(cmd_ctx
);
1949 arm
= target_to_arm(target
);
1952 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1959 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1966 COMMAND_PARSE_NUMBER(u32
, args
[0], new_value
);
1968 if ((new_value
< 2) || (new_value
> 100))
1970 command_print(cmd_ctx
, "valid settings are 2%% to 100%%");
1974 etm_ctx
->trigger_percent
= new_value
;
1978 command_print(cmd_ctx
, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx
->trigger_percent
)));
1983 COMMAND_HANDLER(handle_etm_start_command
)
1987 etm_context_t
*etm_ctx
;
1988 reg_t
*etm_ctrl_reg
;
1990 target
= get_current_target(cmd_ctx
);
1991 arm
= target_to_arm(target
);
1994 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
2001 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
2005 /* invalidate old tracing data */
2006 etm_ctx
->capture_status
= TRACE_IDLE
;
2007 if (etm_ctx
->trace_depth
> 0)
2009 free(etm_ctx
->trace_data
);
2010 etm_ctx
->trace_data
= NULL
;
2012 etm_ctx
->trace_depth
= 0;
2014 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
2018 etm_get_reg(etm_ctrl_reg
);
2020 /* Clear programming bit (10), set port selection bit (11) */
2021 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
2023 etm_store_reg(etm_ctrl_reg
);
2024 jtag_execute_queue();
2026 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
2031 COMMAND_HANDLER(handle_etm_stop_command
)
2035 etm_context_t
*etm_ctx
;
2036 reg_t
*etm_ctrl_reg
;
2038 target
= get_current_target(cmd_ctx
);
2039 arm
= target_to_arm(target
);
2042 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
2049 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
2053 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
2057 etm_get_reg(etm_ctrl_reg
);
2059 /* Set programming bit (10), clear port selection bit (11) */
2060 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
2062 etm_store_reg(etm_ctrl_reg
);
2063 jtag_execute_queue();
2065 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
2070 COMMAND_HANDLER(handle_etm_analyze_command
)
2074 etm_context_t
*etm_ctx
;
2077 target
= get_current_target(cmd_ctx
);
2078 arm
= target_to_arm(target
);
2081 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
2088 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
2092 if ((retval
= etmv1_analyze_trace(etm_ctx
, cmd_ctx
)) != ERROR_OK
)
2096 case ERROR_ETM_ANALYSIS_FAILED
:
2097 command_print(cmd_ctx
, "further analysis failed (corrupted trace data or just end of data");
2099 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE
:
2100 command_print(cmd_ctx
, "no instruction for current address available, analysis aborted");
2102 case ERROR_TRACE_IMAGE_UNAVAILABLE
:
2103 command_print(cmd_ctx
, "no image available for trace analysis");
2106 command_print(cmd_ctx
, "unknown error: %i", retval
);
2113 int etm_register_commands(struct command_context_s
*cmd_ctx
)
2115 etm_cmd
= register_command(cmd_ctx
, NULL
, "etm", NULL
, COMMAND_ANY
, "Embedded Trace Macrocell");
2117 register_command(cmd_ctx
, etm_cmd
, "config", handle_etm_config_command
,
2118 COMMAND_CONFIG
, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2123 static int etm_register_user_commands(struct command_context_s
*cmd_ctx
)
2125 register_command(cmd_ctx
, etm_cmd
, "tracemode", handle_etm_tracemode_command
,
2126 COMMAND_EXEC
, "configure/display trace mode: "
2127 "<none | data | address | all> "
2128 "<context_id_bits> <cycle_accurate> <branch_output>");
2130 register_command(cmd_ctx
, etm_cmd
, "info", handle_etm_info_command
,
2131 COMMAND_EXEC
, "display info about the current target's ETM");
2133 register_command(cmd_ctx
, etm_cmd
, "trigger_percent", handle_etm_trigger_percent_command
,
2134 COMMAND_EXEC
, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2135 register_command(cmd_ctx
, etm_cmd
, "status", handle_etm_status_command
,
2136 COMMAND_EXEC
, "display current target's ETM status");
2137 register_command(cmd_ctx
, etm_cmd
, "start", handle_etm_start_command
,
2138 COMMAND_EXEC
, "start ETM trace collection");
2139 register_command(cmd_ctx
, etm_cmd
, "stop", handle_etm_stop_command
,
2140 COMMAND_EXEC
, "stop ETM trace collection");
2142 register_command(cmd_ctx
, etm_cmd
, "analyze", handle_etm_analyze_command
,
2143 COMMAND_EXEC
, "anaylze collected ETM trace");
2145 register_command(cmd_ctx
, etm_cmd
, "image", handle_etm_image_command
,
2146 COMMAND_EXEC
, "load image from <file> [base address]");
2148 register_command(cmd_ctx
, etm_cmd
, "dump", handle_etm_dump_command
,
2149 COMMAND_EXEC
, "dump captured trace data <file>");
2150 register_command(cmd_ctx
, etm_cmd
, "load", handle_etm_load_command
,
2151 COMMAND_EXEC
, "load trace data for analysis <file>");
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