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jtag: retire jtag_get/set_end_state()
[openocd.git] / src / target / etm.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm.h"
25 #include "etm.h"
26 #include "etb.h"
27 #include "image.h"
28 #include "arm_disassembler.h"
29 #include "register.h"
30 #include "etm_dummy.h"
31
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
34 #endif
35
36
37 /*
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
39 *
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
43 *
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
48 *
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
52 *
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
57 */
58
59 enum {
60 RO, /* read/only */
61 WO, /* write/only */
62 RW, /* read/write */
63 };
64
65 struct etm_reg_info {
66 uint8_t addr;
67 uint8_t size; /* low-N of 32 bits */
68 uint8_t mode; /* RO, WO, RW */
69 uint8_t bcd_vers; /* 1.0, 2.0, etc */
70 char *name;
71 };
72
73 /*
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
78 */
79
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
84 { ETM_ID, 32, RO, 0x20, "ETM_id", },
85 };
86
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
95
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
101
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
107
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
109
110 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
115 };
116
117 static const struct etm_reg_info etm_fifofull[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
121 };
122
123 static const struct etm_reg_info etm_addr_comp[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
130 ADDR_COMPARATOR(1),
131 ADDR_COMPARATOR(2),
132 ADDR_COMPARATOR(3),
133 ADDR_COMPARATOR(4),
134 ADDR_COMPARATOR(5),
135 ADDR_COMPARATOR(6),
136 ADDR_COMPARATOR(7),
137 ADDR_COMPARATOR(8),
138
139 ADDR_COMPARATOR(9),
140 ADDR_COMPARATOR(10),
141 ADDR_COMPARATOR(11),
142 ADDR_COMPARATOR(12),
143 ADDR_COMPARATOR(13),
144 ADDR_COMPARATOR(14),
145 ADDR_COMPARATOR(15),
146 ADDR_COMPARATOR(16),
147 #undef ADDR_COMPARATOR
148 };
149
150 static const struct etm_reg_info etm_data_comp[] = {
151 /* Data Value Comparators (NOTE: odd addresses are reserved) */
152 #define DATA_COMPARATOR(i) \
153 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
154 "ETM_data_" #i "_comparator_value", }, \
155 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
156 "ETM_data_" #i "_comparator_mask", }
157 DATA_COMPARATOR(1),
158 DATA_COMPARATOR(2),
159 DATA_COMPARATOR(3),
160 DATA_COMPARATOR(4),
161 DATA_COMPARATOR(5),
162 DATA_COMPARATOR(6),
163 DATA_COMPARATOR(7),
164 DATA_COMPARATOR(8),
165 #undef DATA_COMPARATOR
166 };
167
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
178 ETM_COUNTER(1),
179 ETM_COUNTER(2),
180 ETM_COUNTER(3),
181 ETM_COUNTER(4),
182 #undef ETM_COUNTER
183 };
184
185 static const struct etm_reg_info etm_sequencer[] = {
186 #define ETM_SEQ(i) \
187 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
188 "ETM_sequencer_event" #i, }
189 ETM_SEQ(0), /* 1->2 */
190 ETM_SEQ(1), /* 2->1 */
191 ETM_SEQ(2), /* 2->3 */
192 ETM_SEQ(3), /* 3->1 */
193 ETM_SEQ(4), /* 3->2 */
194 ETM_SEQ(5), /* 1->3 */
195 #undef ETM_SEQ
196 /* 0x66 reserved */
197 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
198 };
199
200 static const struct etm_reg_info etm_outputs[] = {
201 #define ETM_OUTPUT(i) \
202 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
203 "ETM_external_output" #i, }
204
205 ETM_OUTPUT(1),
206 ETM_OUTPUT(2),
207 ETM_OUTPUT(3),
208 ETM_OUTPUT(4),
209 #undef ETM_OUTPUT
210 };
211
212 #if 0
213 /* registers from 0x6c..0x7f were added after ETMv1.3 */
214
215 /* Context ID Comparators */
216 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
217 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
218 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
219 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
220 #endif
221
222 static int etm_get_reg(struct reg *reg);
223 static int etm_read_reg_w_check(struct reg *reg,
224 uint8_t* check_value, uint8_t* check_mask);
225 static int etm_register_user_commands(struct command_context *cmd_ctx);
226 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
227 static int etm_write_reg(struct reg *reg, uint32_t value);
228
229 static const struct reg_arch_type etm_scan6_type = {
230 .get = etm_get_reg,
231 .set = etm_set_reg_w_exec,
232 };
233
234 /* Look up register by ID ... most ETM instances only
235 * support a subset of the possible registers.
236 */
237 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
238 {
239 struct reg_cache *cache = etm_ctx->reg_cache;
240 unsigned i;
241
242 for (i = 0; i < cache->num_regs; i++) {
243 struct etm_reg *reg = cache->reg_list[i].arch_info;
244
245 if (reg->reg_info->addr == id)
246 return &cache->reg_list[i];
247 }
248
249 /* caller asking for nonexistent register is a bug! */
250 /* REVISIT say which of the N targets was involved */
251 LOG_ERROR("ETM: register 0x%02x not available", id);
252 return NULL;
253 }
254
255 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
256 struct reg_cache *cache, struct etm_reg *ereg,
257 const struct etm_reg_info *r, unsigned nreg)
258 {
259 struct reg *reg = cache->reg_list;
260
261 reg += cache->num_regs;
262 ereg += cache->num_regs;
263
264 /* add up to "nreg" registers from "r", if supported by this
265 * version of the ETM, to the specified cache.
266 */
267 for (; nreg--; r++) {
268
269 /* this ETM may be too old to have some registers */
270 if (r->bcd_vers > bcd_vers)
271 continue;
272
273 reg->name = r->name;
274 reg->size = r->size;
275 reg->value = &ereg->value;
276 reg->arch_info = ereg;
277 reg->type = &etm_scan6_type;
278 reg++;
279 cache->num_regs++;
280
281 ereg->reg_info = r;
282 ereg->jtag_info = jtag_info;
283 ereg++;
284 }
285 }
286
287 struct reg_cache *etm_build_reg_cache(struct target *target,
288 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
289 {
290 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
291 struct reg *reg_list = NULL;
292 struct etm_reg *arch_info = NULL;
293 unsigned bcd_vers, config;
294
295 /* the actual registers are kept in two arrays */
296 reg_list = calloc(128, sizeof(struct reg));
297 arch_info = calloc(128, sizeof(struct etm_reg));
298
299 /* fill in values for the reg cache */
300 reg_cache->name = "etm registers";
301 reg_cache->next = NULL;
302 reg_cache->reg_list = reg_list;
303 reg_cache->num_regs = 0;
304
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
307 */
308 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
309 etm_core, 1);
310
311 etm_get_reg(reg_list);
312 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
313 config = etm_ctx->config;
314
315 /* figure ETM version then add base registers */
316 if (config & (1 << 31)) {
317 bcd_vers = 0x20;
318 LOG_WARNING("ETMv2+ support is incomplete");
319
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
324 */
325 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
326 etm_core + 1, 1);
327 etm_get_reg(reg_list + 1);
328 etm_ctx->id = buf_get_u32(
329 (void *)&arch_info[1].value, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
331 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
332
333 } else {
334 switch (config >> 28) {
335 case 7:
336 case 5:
337 case 3:
338 bcd_vers = 0x13;
339 break;
340 case 4:
341 case 2:
342 bcd_vers = 0x12;
343 break;
344 case 1:
345 bcd_vers = 0x11;
346 break;
347 case 0:
348 bcd_vers = 0x10;
349 break;
350 default:
351 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
352 goto fail;
353 }
354 }
355 etm_ctx->bcd_vers = bcd_vers;
356 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
357
358 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
359 etm_basic, ARRAY_SIZE(etm_basic));
360
361 /* address and data comparators; counters; outputs */
362 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
363 etm_addr_comp, 4 * (0x0f & (config >> 0)));
364 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
365 etm_data_comp, 2 * (0x0f & (config >> 4)));
366 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
367 etm_counters, 4 * (0x07 & (config >> 13)));
368 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
369 etm_outputs, (0x07 & (config >> 20)));
370
371 /* FIFOFULL presence is optional
372 * REVISIT for ETMv1.2 and later, don't bother adding this
373 * unless ETM_SYS_CONFIG says it's also *supported* ...
374 */
375 if (config & (1 << 23))
376 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
377 etm_fifofull, ARRAY_SIZE(etm_fifofull));
378
379 /* sequencer is optional (for state-dependant triggering) */
380 if (config & (1 << 16))
381 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
382 etm_sequencer, ARRAY_SIZE(etm_sequencer));
383
384 /* REVISIT could realloc and likely save half the memory
385 * in the two chunks we allocated...
386 */
387
388 /* the ETM might have an ETB connected */
389 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
390 {
391 struct etb *etb = etm_ctx->capture_driver_priv;
392
393 if (!etb)
394 {
395 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
396 goto fail;
397 }
398
399 reg_cache->next = etb_build_reg_cache(etb);
400
401 etb->reg_cache = reg_cache->next;
402 }
403
404 etm_ctx->reg_cache = reg_cache;
405 return reg_cache;
406
407 fail:
408 free(reg_cache);
409 free(reg_list);
410 free(arch_info);
411 return NULL;
412 }
413
414 static int etm_read_reg(struct reg *reg)
415 {
416 return etm_read_reg_w_check(reg, NULL, NULL);
417 }
418
419 static int etm_store_reg(struct reg *reg)
420 {
421 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
422 }
423
424 int etm_setup(struct target *target)
425 {
426 int retval;
427 uint32_t etm_ctrl_value;
428 struct arm *arm = target_to_arm(target);
429 struct etm_context *etm_ctx = arm->etm;
430 struct reg *etm_ctrl_reg;
431
432 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
433 if (!etm_ctrl_reg)
434 return ERROR_OK;
435
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg);
438 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
439
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
442
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
445 */
446 etm_ctrl_value = (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
449 & ~ETM_CTRL_DBGRQ
450 & ~ETM_PORT_CLOCK_MASK)
451 | etm_ctx->control;
452
453 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
454 etm_store_reg(etm_ctrl_reg);
455
456 etm_ctx->control = etm_ctrl_value;
457
458 if ((retval = jtag_execute_queue()) != ERROR_OK)
459 return retval;
460
461 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
462 * verify that those width and mode settings are OK ...
463 */
464
465 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
466 {
467 LOG_ERROR("ETM capture driver initialization failed");
468 return retval;
469 }
470 return ERROR_OK;
471 }
472
473 static int etm_get_reg(struct reg *reg)
474 {
475 int retval;
476
477 if ((retval = etm_read_reg(reg)) != ERROR_OK)
478 {
479 LOG_ERROR("BUG: error scheduling etm register read");
480 return retval;
481 }
482
483 if ((retval = jtag_execute_queue()) != ERROR_OK)
484 {
485 LOG_ERROR("register read failed");
486 return retval;
487 }
488
489 return ERROR_OK;
490 }
491
492 static int etm_read_reg_w_check(struct reg *reg,
493 uint8_t* check_value, uint8_t* check_mask)
494 {
495 struct etm_reg *etm_reg = reg->arch_info;
496 const struct etm_reg_info *r = etm_reg->reg_info;
497 uint8_t reg_addr = r->addr & 0x7f;
498 struct scan_field fields[3];
499
500 if (etm_reg->reg_info->mode == WO) {
501 LOG_ERROR("BUG: can't read write-only register %s", r->name);
502 return ERROR_INVALID_ARGUMENTS;
503 }
504
505 LOG_DEBUG("%s (%u)", r->name, reg_addr);
506
507 arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
508 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
509
510 fields[0].num_bits = 32;
511 fields[0].out_value = reg->value;
512 fields[0].in_value = NULL;
513 fields[0].check_value = NULL;
514 fields[0].check_mask = NULL;
515
516 fields[1].num_bits = 7;
517 fields[1].out_value = malloc(1);
518 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
519 fields[1].in_value = NULL;
520 fields[1].check_value = NULL;
521 fields[1].check_mask = NULL;
522
523 fields[2].num_bits = 1;
524 fields[2].out_value = malloc(1);
525 buf_set_u32(fields[2].out_value, 0, 1, 0);
526 fields[2].in_value = NULL;
527 fields[2].check_value = NULL;
528 fields[2].check_mask = NULL;
529
530 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
531
532 fields[0].in_value = reg->value;
533 fields[0].check_value = check_value;
534 fields[0].check_mask = check_mask;
535
536 jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
537
538 free(fields[1].out_value);
539 free(fields[2].out_value);
540
541 return ERROR_OK;
542 }
543
544 static int etm_set_reg(struct reg *reg, uint32_t value)
545 {
546 int retval;
547
548 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
549 {
550 LOG_ERROR("BUG: error scheduling etm register write");
551 return retval;
552 }
553
554 buf_set_u32(reg->value, 0, reg->size, value);
555 reg->valid = 1;
556 reg->dirty = 0;
557
558 return ERROR_OK;
559 }
560
561 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
562 {
563 int retval;
564
565 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
566
567 if ((retval = jtag_execute_queue()) != ERROR_OK)
568 {
569 LOG_ERROR("register write failed");
570 return retval;
571 }
572 return ERROR_OK;
573 }
574
575 static int etm_write_reg(struct reg *reg, uint32_t value)
576 {
577 struct etm_reg *etm_reg = reg->arch_info;
578 const struct etm_reg_info *r = etm_reg->reg_info;
579 uint8_t reg_addr = r->addr & 0x7f;
580 struct scan_field fields[3];
581
582 if (etm_reg->reg_info->mode == RO) {
583 LOG_ERROR("BUG: can't write read--only register %s", r->name);
584 return ERROR_INVALID_ARGUMENTS;
585 }
586
587 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
588
589 arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
590 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
591
592 fields[0].num_bits = 32;
593 uint8_t tmp1[4];
594 fields[0].out_value = tmp1;
595 buf_set_u32(fields[0].out_value, 0, 32, value);
596 fields[0].in_value = NULL;
597
598 fields[1].num_bits = 7;
599 uint8_t tmp2;
600 fields[1].out_value = &tmp2;
601 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
602 fields[1].in_value = NULL;
603
604 fields[2].num_bits = 1;
605 uint8_t tmp3;
606 fields[2].out_value = &tmp3;
607 buf_set_u32(fields[2].out_value, 0, 1, 1);
608 fields[2].in_value = NULL;
609
610 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
611
612 return ERROR_OK;
613 }
614
615
616 /* ETM trace analysis functionality */
617
618 static struct etm_capture_driver *etm_capture_drivers[] =
619 {
620 &etb_capture_driver,
621 &etm_dummy_capture_driver,
622 #if BUILD_OOCD_TRACE == 1
623 &oocd_trace_capture_driver,
624 #endif
625 NULL
626 };
627
628 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
629 {
630 int i;
631 int section = -1;
632 size_t size_read;
633 uint32_t opcode;
634 int retval;
635
636 if (!ctx->image)
637 return ERROR_TRACE_IMAGE_UNAVAILABLE;
638
639 /* search for the section the current instruction belongs to */
640 for (i = 0; i < ctx->image->num_sections; i++)
641 {
642 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
643 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
644 {
645 section = i;
646 break;
647 }
648 }
649
650 if (section == -1)
651 {
652 /* current instruction couldn't be found in the image */
653 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
654 }
655
656 if (ctx->core_state == ARM_STATE_ARM)
657 {
658 uint8_t buf[4];
659 if ((retval = image_read_section(ctx->image, section,
660 ctx->current_pc - ctx->image->sections[section].base_address,
661 4, buf, &size_read)) != ERROR_OK)
662 {
663 LOG_ERROR("error while reading instruction: %i", retval);
664 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
665 }
666 opcode = target_buffer_get_u32(ctx->target, buf);
667 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
668 }
669 else if (ctx->core_state == ARM_STATE_THUMB)
670 {
671 uint8_t buf[2];
672 if ((retval = image_read_section(ctx->image, section,
673 ctx->current_pc - ctx->image->sections[section].base_address,
674 2, buf, &size_read)) != ERROR_OK)
675 {
676 LOG_ERROR("error while reading instruction: %i", retval);
677 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
678 }
679 opcode = target_buffer_get_u16(ctx->target, buf);
680 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
681 }
682 else if (ctx->core_state == ARM_STATE_JAZELLE)
683 {
684 LOG_ERROR("BUG: tracing of jazelle code not supported");
685 return ERROR_FAIL;
686 }
687 else
688 {
689 LOG_ERROR("BUG: unknown core state encountered");
690 return ERROR_FAIL;
691 }
692
693 return ERROR_OK;
694 }
695
696 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
697 {
698 while (ctx->data_index < ctx->trace_depth)
699 {
700 /* if the caller specified an address packet offset, skip until the
701 * we reach the n-th cycle marked with tracesync */
702 if (apo > 0)
703 {
704 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
705 apo--;
706
707 if (apo > 0)
708 {
709 ctx->data_index++;
710 ctx->data_half = 0;
711 }
712 continue;
713 }
714
715 /* no tracedata output during a TD cycle
716 * or in a trigger cycle */
717 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
718 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
719 {
720 ctx->data_index++;
721 ctx->data_half = 0;
722 continue;
723 }
724
725 /* FIXME there are more port widths than these... */
726 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
727 {
728 if (ctx->data_half == 0)
729 {
730 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
731 ctx->data_half = 1;
732 }
733 else
734 {
735 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
736 ctx->data_half = 0;
737 ctx->data_index++;
738 }
739 }
740 else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
741 {
742 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
743 ctx->data_index++;
744 }
745 else
746 {
747 /* on a 4-bit port, a packet will be output during two consecutive cycles */
748 if (ctx->data_index > (ctx->trace_depth - 2))
749 return -1;
750
751 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
752 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
753 ctx->data_index += 2;
754 }
755
756 return 0;
757 }
758
759 return -1;
760 }
761
762 static int etmv1_branch_address(struct etm_context *ctx)
763 {
764 int retval;
765 uint8_t packet;
766 int shift = 0;
767 int apo;
768 uint32_t i;
769
770 /* quit analysis if less than two cycles are left in the trace
771 * because we can't extract the APO */
772 if (ctx->data_index > (ctx->trace_depth - 2))
773 return -1;
774
775 /* a BE could be output during an APO cycle, skip the current
776 * and continue with the new one */
777 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
778 return 1;
779 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
780 return 2;
781
782 /* address packet offset encoded in the next two cycles' pipestat bits */
783 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
784 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
785
786 /* count number of tracesync cycles between current pipe_index and data_index
787 * i.e. the number of tracesyncs that data_index already passed by
788 * to subtract them from the APO */
789 for (i = ctx->pipe_index; i < ctx->data_index; i++)
790 {
791 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
792 apo--;
793 }
794
795 /* extract up to four 7-bit packets */
796 do {
797 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
798 return -1;
799 ctx->last_branch &= ~(0x7f << shift);
800 ctx->last_branch |= (packet & 0x7f) << shift;
801 shift += 7;
802 } while ((packet & 0x80) && (shift < 28));
803
804 /* one last packet holding 4 bits of the address, plus the branch reason code */
805 if ((shift == 28) && (packet & 0x80))
806 {
807 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
808 return -1;
809 ctx->last_branch &= 0x0fffffff;
810 ctx->last_branch |= (packet & 0x0f) << 28;
811 ctx->last_branch_reason = (packet & 0x70) >> 4;
812 shift += 4;
813 }
814 else
815 {
816 ctx->last_branch_reason = 0;
817 }
818
819 if (shift == 32)
820 {
821 ctx->pc_ok = 1;
822 }
823
824 /* if a full address was output, we might have branched into Jazelle state */
825 if ((shift == 32) && (packet & 0x80))
826 {
827 ctx->core_state = ARM_STATE_JAZELLE;
828 }
829 else
830 {
831 /* if we didn't branch into Jazelle state, the current processor state is
832 * encoded in bit 0 of the branch target address */
833 if (ctx->last_branch & 0x1)
834 {
835 ctx->core_state = ARM_STATE_THUMB;
836 ctx->last_branch &= ~0x1;
837 }
838 else
839 {
840 ctx->core_state = ARM_STATE_ARM;
841 ctx->last_branch &= ~0x3;
842 }
843 }
844
845 return 0;
846 }
847
848 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
849 {
850 int j;
851 uint8_t buf[4];
852 int retval;
853
854 for (j = 0; j < size; j++)
855 {
856 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
857 return -1;
858 }
859
860 if (size == 8)
861 {
862 LOG_ERROR("TODO: add support for 64-bit values");
863 return -1;
864 }
865 else if (size == 4)
866 *data = target_buffer_get_u32(ctx->target, buf);
867 else if (size == 2)
868 *data = target_buffer_get_u16(ctx->target, buf);
869 else if (size == 1)
870 *data = buf[0];
871 else
872 return -1;
873
874 return 0;
875 }
876
877 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
878 {
879 int retval;
880 struct arm_instruction instruction;
881
882 /* read the trace data if it wasn't read already */
883 if (ctx->trace_depth == 0)
884 ctx->capture_driver->read_trace(ctx);
885
886 /* start at the beginning of the captured trace */
887 ctx->pipe_index = 0;
888 ctx->data_index = 0;
889 ctx->data_half = 0;
890
891 /* neither the PC nor the data pointer are valid */
892 ctx->pc_ok = 0;
893 ctx->ptr_ok = 0;
894
895 while (ctx->pipe_index < ctx->trace_depth)
896 {
897 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
898 uint32_t next_pc = ctx->current_pc;
899 uint32_t old_data_index = ctx->data_index;
900 uint32_t old_data_half = ctx->data_half;
901 uint32_t old_index = ctx->pipe_index;
902 uint32_t last_instruction = ctx->last_instruction;
903 uint32_t cycles = 0;
904 int current_pc_ok = ctx->pc_ok;
905
906 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
907 {
908 command_print(cmd_ctx, "--- trigger ---");
909 }
910
911 /* instructions execute in IE/D or BE/D cycles */
912 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
913 ctx->last_instruction = ctx->pipe_index;
914
915 /* if we don't have a valid pc skip until we reach an indirect branch */
916 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
917 {
918 ctx->pipe_index++;
919 continue;
920 }
921
922 /* any indirect branch could have interrupted instruction flow
923 * - the branch reason code could indicate a trace discontinuity
924 * - a branch to the exception vectors indicates an exception
925 */
926 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
927 {
928 /* backup current data index, to be able to consume the branch address
929 * before examining data address and values
930 */
931 old_data_index = ctx->data_index;
932 old_data_half = ctx->data_half;
933
934 ctx->last_instruction = ctx->pipe_index;
935
936 if ((retval = etmv1_branch_address(ctx)) != 0)
937 {
938 /* negative return value from etmv1_branch_address means we ran out of packets,
939 * quit analysing the trace */
940 if (retval < 0)
941 break;
942
943 /* a positive return values means the current branch was abandoned,
944 * and a new branch was encountered in cycle ctx->pipe_index + retval;
945 */
946 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
947 ctx->pipe_index += retval;
948 continue;
949 }
950
951 /* skip over APO cycles */
952 ctx->pipe_index += 2;
953
954 switch (ctx->last_branch_reason)
955 {
956 case 0x0: /* normal PC change */
957 next_pc = ctx->last_branch;
958 break;
959 case 0x1: /* tracing enabled */
960 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
961 ctx->current_pc = ctx->last_branch;
962 ctx->pipe_index++;
963 continue;
964 break;
965 case 0x2: /* trace restarted after FIFO overflow */
966 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
967 ctx->current_pc = ctx->last_branch;
968 ctx->pipe_index++;
969 continue;
970 break;
971 case 0x3: /* exit from debug state */
972 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
973 ctx->current_pc = ctx->last_branch;
974 ctx->pipe_index++;
975 continue;
976 break;
977 case 0x4: /* periodic synchronization point */
978 next_pc = ctx->last_branch;
979 /* if we had no valid PC prior to this synchronization point,
980 * we have to move on with the next trace cycle
981 */
982 if (!current_pc_ok)
983 {
984 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
985 ctx->current_pc = next_pc;
986 ctx->pipe_index++;
987 continue;
988 }
989 break;
990 default: /* reserved */
991 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
992 return ERROR_FAIL;
993 }
994
995 /* if we got here the branch was a normal PC change
996 * (or a periodic synchronization point, which means the same for that matter)
997 * if we didn't accquire a complete PC continue with the next cycle
998 */
999 if (!ctx->pc_ok)
1000 continue;
1001
1002 /* indirect branch to the exception vector means an exception occured */
1003 if ((ctx->last_branch <= 0x20)
1004 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1005 {
1006 if ((ctx->last_branch & 0xff) == 0x10)
1007 {
1008 command_print(cmd_ctx, "data abort");
1009 }
1010 else
1011 {
1012 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1013 ctx->current_pc = ctx->last_branch;
1014 ctx->pipe_index++;
1015 continue;
1016 }
1017 }
1018 }
1019
1020 /* an instruction was executed (or not, depending on the condition flags)
1021 * retrieve it from the image for displaying */
1022 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1023 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1024 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1025 {
1026 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1027 {
1028 /* can't continue tracing with no image available */
1029 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1030 {
1031 return retval;
1032 }
1033 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1034 {
1035 /* TODO: handle incomplete images
1036 * for now we just quit the analsysis*/
1037 return retval;
1038 }
1039 }
1040
1041 cycles = old_index - last_instruction;
1042 }
1043
1044 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1045 {
1046 uint32_t new_data_index = ctx->data_index;
1047 uint32_t new_data_half = ctx->data_half;
1048
1049 /* in case of a branch with data, the branch target address was consumed before
1050 * we temporarily go back to the saved data index */
1051 if (pipestat == STAT_BD)
1052 {
1053 ctx->data_index = old_data_index;
1054 ctx->data_half = old_data_half;
1055 }
1056
1057 if (ctx->control & ETM_CTRL_TRACE_ADDR)
1058 {
1059 uint8_t packet;
1060 int shift = 0;
1061
1062 do {
1063 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1064 return ERROR_ETM_ANALYSIS_FAILED;
1065 ctx->last_ptr &= ~(0x7f << shift);
1066 ctx->last_ptr |= (packet & 0x7f) << shift;
1067 shift += 7;
1068 } while ((packet & 0x80) && (shift < 32));
1069
1070 if (shift >= 32)
1071 ctx->ptr_ok = 1;
1072
1073 if (ctx->ptr_ok)
1074 {
1075 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1076 }
1077 }
1078
1079 if (ctx->control & ETM_CTRL_TRACE_DATA)
1080 {
1081 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1082 {
1083 int i;
1084 for (i = 0; i < 16; i++)
1085 {
1086 if (instruction.info.load_store_multiple.register_list & (1 << i))
1087 {
1088 uint32_t data;
1089 if (etmv1_data(ctx, 4, &data) != 0)
1090 return ERROR_ETM_ANALYSIS_FAILED;
1091 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1092 }
1093 }
1094 }
1095 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1096 {
1097 uint32_t data;
1098 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1099 return ERROR_ETM_ANALYSIS_FAILED;
1100 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1101 }
1102 }
1103
1104 /* restore data index after consuming BD address and data */
1105 if (pipestat == STAT_BD)
1106 {
1107 ctx->data_index = new_data_index;
1108 ctx->data_half = new_data_half;
1109 }
1110 }
1111
1112 /* adjust PC */
1113 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1114 {
1115 if (((instruction.type == ARM_B) ||
1116 (instruction.type == ARM_BL) ||
1117 (instruction.type == ARM_BLX)) &&
1118 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1119 {
1120 next_pc = instruction.info.b_bl_bx_blx.target_address;
1121 }
1122 else
1123 {
1124 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1125 }
1126 }
1127 else if (pipestat == STAT_IN)
1128 {
1129 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1130 }
1131
1132 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1133 {
1134 char cycles_text[32] = "";
1135
1136 /* if the trace was captured with cycle accurate tracing enabled,
1137 * output the number of cycles since the last executed instruction
1138 */
1139 if (ctx->control & ETM_CTRL_CYCLE_ACCURATE)
1140 {
1141 snprintf(cycles_text, 32, " (%i %s)",
1142 (int)cycles,
1143 (cycles == 1) ? "cycle" : "cycles");
1144 }
1145
1146 command_print(cmd_ctx, "%s%s%s",
1147 instruction.text,
1148 (pipestat == STAT_IN) ? " (not executed)" : "",
1149 cycles_text);
1150
1151 ctx->current_pc = next_pc;
1152
1153 /* packets for an instruction don't start on or before the preceding
1154 * functional pipestat (i.e. other than WT or TD)
1155 */
1156 if (ctx->data_index <= ctx->pipe_index)
1157 {
1158 ctx->data_index = ctx->pipe_index + 1;
1159 ctx->data_half = 0;
1160 }
1161 }
1162
1163 ctx->pipe_index += 1;
1164 }
1165
1166 return ERROR_OK;
1167 }
1168
1169 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1170 uint32_t *mode)
1171 {
1172 uint32_t tracemode;
1173
1174 /* what parts of data access are traced? */
1175 if (strcmp(CMD_ARGV[0], "none") == 0)
1176 tracemode = 0;
1177 else if (strcmp(CMD_ARGV[0], "data") == 0)
1178 tracemode = ETM_CTRL_TRACE_DATA;
1179 else if (strcmp(CMD_ARGV[0], "address") == 0)
1180 tracemode = ETM_CTRL_TRACE_ADDR;
1181 else if (strcmp(CMD_ARGV[0], "all") == 0)
1182 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1183 else
1184 {
1185 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1186 return ERROR_INVALID_ARGUMENTS;
1187 }
1188
1189 uint8_t context_id;
1190 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1191 switch (context_id)
1192 {
1193 case 0:
1194 tracemode |= ETM_CTRL_CONTEXTID_NONE;
1195 break;
1196 case 8:
1197 tracemode |= ETM_CTRL_CONTEXTID_8;
1198 break;
1199 case 16:
1200 tracemode |= ETM_CTRL_CONTEXTID_16;
1201 break;
1202 case 32:
1203 tracemode |= ETM_CTRL_CONTEXTID_32;
1204 break;
1205 default:
1206 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1207 return ERROR_INVALID_ARGUMENTS;
1208 }
1209
1210 bool etmv1_cycle_accurate;
1211 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1212 if (etmv1_cycle_accurate)
1213 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1214
1215 bool etmv1_branch_output;
1216 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1217 if (etmv1_branch_output)
1218 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1219
1220 /* IGNORED:
1221 * - CPRT tracing (coprocessor register transfers)
1222 * - debug request (causes debug entry on trigger)
1223 * - stall on FIFOFULL (preventing tracedata lossage)
1224 */
1225 *mode = tracemode;
1226
1227 return ERROR_OK;
1228 }
1229
1230 COMMAND_HANDLER(handle_etm_tracemode_command)
1231 {
1232 struct target *target = get_current_target(CMD_CTX);
1233 struct arm *arm = target_to_arm(target);
1234 struct etm_context *etm;
1235
1236 if (!is_arm(arm)) {
1237 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1238 return ERROR_FAIL;
1239 }
1240
1241 etm = arm->etm;
1242 if (!etm) {
1243 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1244 return ERROR_FAIL;
1245 }
1246
1247 uint32_t tracemode = etm->control;
1248
1249 switch (CMD_ARGC)
1250 {
1251 case 0:
1252 break;
1253 case 4:
1254 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1255 &tracemode);
1256 break;
1257 default:
1258 command_print(CMD_CTX, "usage: tracemode "
1259 "('none'|'data'|'address'|'all') "
1260 "context_id_bits "
1261 "('enable'|'disable') "
1262 "('enable'|'disable')"
1263 );
1264 return ERROR_FAIL;
1265 }
1266
1267 /**
1268 * todo: fail if parameters were invalid for this hardware,
1269 * or couldn't be written; display actual hardware state...
1270 */
1271
1272 command_print(CMD_CTX, "current tracemode configuration:");
1273
1274 switch (tracemode & ETM_CTRL_TRACE_MASK)
1275 {
1276 default:
1277 command_print(CMD_CTX, "data tracing: none");
1278 break;
1279 case ETM_CTRL_TRACE_DATA:
1280 command_print(CMD_CTX, "data tracing: data only");
1281 break;
1282 case ETM_CTRL_TRACE_ADDR:
1283 command_print(CMD_CTX, "data tracing: address only");
1284 break;
1285 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1286 command_print(CMD_CTX, "data tracing: address and data");
1287 break;
1288 }
1289
1290 switch (tracemode & ETM_CTRL_CONTEXTID_MASK)
1291 {
1292 case ETM_CTRL_CONTEXTID_NONE:
1293 command_print(CMD_CTX, "contextid tracing: none");
1294 break;
1295 case ETM_CTRL_CONTEXTID_8:
1296 command_print(CMD_CTX, "contextid tracing: 8 bit");
1297 break;
1298 case ETM_CTRL_CONTEXTID_16:
1299 command_print(CMD_CTX, "contextid tracing: 16 bit");
1300 break;
1301 case ETM_CTRL_CONTEXTID_32:
1302 command_print(CMD_CTX, "contextid tracing: 32 bit");
1303 break;
1304 }
1305
1306 if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1307 {
1308 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1309 }
1310 else
1311 {
1312 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1313 }
1314
1315 if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1316 {
1317 command_print(CMD_CTX, "full branch address output enabled");
1318 }
1319 else
1320 {
1321 command_print(CMD_CTX, "full branch address output disabled");
1322 }
1323
1324 #define TRACEMODE_MASK ( \
1325 ETM_CTRL_CONTEXTID_MASK \
1326 | ETM_CTRL_BRANCH_OUTPUT \
1327 | ETM_CTRL_CYCLE_ACCURATE \
1328 | ETM_CTRL_TRACE_MASK \
1329 )
1330
1331 /* only update ETM_CTRL register if tracemode changed */
1332 if ((etm->control & TRACEMODE_MASK) != tracemode)
1333 {
1334 struct reg *etm_ctrl_reg;
1335
1336 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1337 if (!etm_ctrl_reg)
1338 return ERROR_FAIL;
1339
1340 etm->control &= ~TRACEMODE_MASK;
1341 etm->control |= tracemode & TRACEMODE_MASK;
1342
1343 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1344 etm_store_reg(etm_ctrl_reg);
1345
1346 /* invalidate old trace data */
1347 etm->capture_status = TRACE_IDLE;
1348 if (etm->trace_depth > 0)
1349 {
1350 free(etm->trace_data);
1351 etm->trace_data = NULL;
1352 }
1353 etm->trace_depth = 0;
1354 }
1355
1356 #undef TRACEMODE_MASK
1357
1358 return ERROR_OK;
1359 }
1360
1361 COMMAND_HANDLER(handle_etm_config_command)
1362 {
1363 struct target *target;
1364 struct arm *arm;
1365 uint32_t portmode = 0x0;
1366 struct etm_context *etm_ctx;
1367 int i;
1368
1369 if (CMD_ARGC != 5)
1370 return ERROR_COMMAND_SYNTAX_ERROR;
1371
1372 target = get_target(CMD_ARGV[0]);
1373 if (!target)
1374 {
1375 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1376 return ERROR_FAIL;
1377 }
1378
1379 arm = target_to_arm(target);
1380 if (!is_arm(arm)) {
1381 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1382 target_name(target),
1383 target_type_name(target));
1384 return ERROR_FAIL;
1385 }
1386
1387 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1388 * version we'll be using!! -- so we can't know how to validate
1389 * params yet. "etm config" should likely be *AFTER* hookup...
1390 *
1391 * - Many more widths might be supported ... and we can easily
1392 * check whether our setting "took".
1393 *
1394 * - The "clock" and "mode" bits are interpreted differently.
1395 * See ARM IHI 0014O table 2-17 for the old behavior, and
1396 * table 2-18 for the new. With ETB it's best to specify
1397 * "normal full" ...
1398 */
1399 uint8_t port_width;
1400 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1401 switch (port_width)
1402 {
1403 /* before ETMv3.0 */
1404 case 4:
1405 portmode |= ETM_PORT_4BIT;
1406 break;
1407 case 8:
1408 portmode |= ETM_PORT_8BIT;
1409 break;
1410 case 16:
1411 portmode |= ETM_PORT_16BIT;
1412 break;
1413 /* ETMv3.0 and later*/
1414 case 24:
1415 portmode |= ETM_PORT_24BIT;
1416 break;
1417 case 32:
1418 portmode |= ETM_PORT_32BIT;
1419 break;
1420 case 48:
1421 portmode |= ETM_PORT_48BIT;
1422 break;
1423 case 64:
1424 portmode |= ETM_PORT_64BIT;
1425 break;
1426 case 1:
1427 portmode |= ETM_PORT_1BIT;
1428 break;
1429 case 2:
1430 portmode |= ETM_PORT_2BIT;
1431 break;
1432 default:
1433 command_print(CMD_CTX,
1434 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1435 return ERROR_FAIL;
1436 }
1437
1438 if (strcmp("normal", CMD_ARGV[2]) == 0)
1439 {
1440 portmode |= ETM_PORT_NORMAL;
1441 }
1442 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1443 {
1444 portmode |= ETM_PORT_MUXED;
1445 }
1446 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1447 {
1448 portmode |= ETM_PORT_DEMUXED;
1449 }
1450 else
1451 {
1452 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1453 return ERROR_FAIL;
1454 }
1455
1456 if (strcmp("half", CMD_ARGV[3]) == 0)
1457 {
1458 portmode |= ETM_PORT_HALF_CLOCK;
1459 }
1460 else if (strcmp("full", CMD_ARGV[3]) == 0)
1461 {
1462 portmode |= ETM_PORT_FULL_CLOCK;
1463 }
1464 else
1465 {
1466 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1467 return ERROR_FAIL;
1468 }
1469
1470 etm_ctx = calloc(1, sizeof(struct etm_context));
1471 if (!etm_ctx) {
1472 LOG_DEBUG("out of memory");
1473 return ERROR_FAIL;
1474 }
1475
1476 for (i = 0; etm_capture_drivers[i]; i++)
1477 {
1478 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1479 {
1480 int retval = register_commands(CMD_CTX, NULL,
1481 etm_capture_drivers[i]->commands);
1482 if (ERROR_OK != retval)
1483 {
1484 free(etm_ctx);
1485 return retval;
1486 }
1487
1488 etm_ctx->capture_driver = etm_capture_drivers[i];
1489
1490 break;
1491 }
1492 }
1493
1494 if (!etm_capture_drivers[i])
1495 {
1496 /* no supported capture driver found, don't register an ETM */
1497 free(etm_ctx);
1498 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1499 return ERROR_FAIL;
1500 }
1501
1502 etm_ctx->target = target;
1503 etm_ctx->trace_data = NULL;
1504 etm_ctx->control = portmode;
1505 etm_ctx->core_state = ARM_STATE_ARM;
1506
1507 arm->etm = etm_ctx;
1508
1509 return etm_register_user_commands(CMD_CTX);
1510 }
1511
1512 COMMAND_HANDLER(handle_etm_info_command)
1513 {
1514 struct target *target;
1515 struct arm *arm;
1516 struct etm_context *etm;
1517 struct reg *etm_sys_config_reg;
1518 int max_port_size;
1519 uint32_t config;
1520
1521 target = get_current_target(CMD_CTX);
1522 arm = target_to_arm(target);
1523 if (!is_arm(arm))
1524 {
1525 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1526 return ERROR_FAIL;
1527 }
1528
1529 etm = arm->etm;
1530 if (!etm)
1531 {
1532 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1533 return ERROR_FAIL;
1534 }
1535
1536 command_print(CMD_CTX, "ETM v%d.%d",
1537 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1538 command_print(CMD_CTX, "pairs of address comparators: %i",
1539 (int) (etm->config >> 0) & 0x0f);
1540 command_print(CMD_CTX, "data comparators: %i",
1541 (int) (etm->config >> 4) & 0x0f);
1542 command_print(CMD_CTX, "memory map decoders: %i",
1543 (int) (etm->config >> 8) & 0x1f);
1544 command_print(CMD_CTX, "number of counters: %i",
1545 (int) (etm->config >> 13) & 0x07);
1546 command_print(CMD_CTX, "sequencer %spresent",
1547 (int) (etm->config & (1 << 16)) ? "" : "not ");
1548 command_print(CMD_CTX, "number of ext. inputs: %i",
1549 (int) (etm->config >> 17) & 0x07);
1550 command_print(CMD_CTX, "number of ext. outputs: %i",
1551 (int) (etm->config >> 20) & 0x07);
1552 command_print(CMD_CTX, "FIFO full %spresent",
1553 (int) (etm->config & (1 << 23)) ? "" : "not ");
1554 if (etm->bcd_vers < 0x20)
1555 command_print(CMD_CTX, "protocol version: %i",
1556 (int) (etm->config >> 28) & 0x07);
1557 else {
1558 command_print(CMD_CTX,
1559 "coprocessor and memory access %ssupported",
1560 (etm->config & (1 << 26)) ? "" : "not ");
1561 command_print(CMD_CTX, "trace start/stop %spresent",
1562 (etm->config & (1 << 26)) ? "" : "not ");
1563 command_print(CMD_CTX, "number of context comparators: %i",
1564 (int) (etm->config >> 24) & 0x03);
1565 }
1566
1567 /* SYS_CONFIG isn't present before ETMv1.2 */
1568 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1569 if (!etm_sys_config_reg)
1570 return ERROR_OK;
1571
1572 etm_get_reg(etm_sys_config_reg);
1573 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1574
1575 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1576
1577 max_port_size = config & 0x7;
1578 if (etm->bcd_vers >= 0x30)
1579 max_port_size |= (config >> 6) & 0x08;
1580 switch (max_port_size)
1581 {
1582 /* before ETMv3.0 */
1583 case 0:
1584 max_port_size = 4;
1585 break;
1586 case 1:
1587 max_port_size = 8;
1588 break;
1589 case 2:
1590 max_port_size = 16;
1591 break;
1592 /* ETMv3.0 and later*/
1593 case 3:
1594 max_port_size = 24;
1595 break;
1596 case 4:
1597 max_port_size = 32;
1598 break;
1599 case 5:
1600 max_port_size = 48;
1601 break;
1602 case 6:
1603 max_port_size = 64;
1604 break;
1605 case 8:
1606 max_port_size = 1;
1607 break;
1608 case 9:
1609 max_port_size = 2;
1610 break;
1611 default:
1612 LOG_ERROR("Illegal max_port_size");
1613 return ERROR_FAIL;
1614 }
1615 command_print(CMD_CTX, "max. port size: %i", max_port_size);
1616
1617 if (etm->bcd_vers < 0x30) {
1618 command_print(CMD_CTX, "half-rate clocking %ssupported",
1619 (config & (1 << 3)) ? "" : "not ");
1620 command_print(CMD_CTX, "full-rate clocking %ssupported",
1621 (config & (1 << 4)) ? "" : "not ");
1622 command_print(CMD_CTX, "normal trace format %ssupported",
1623 (config & (1 << 5)) ? "" : "not ");
1624 command_print(CMD_CTX, "multiplex trace format %ssupported",
1625 (config & (1 << 6)) ? "" : "not ");
1626 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1627 (config & (1 << 7)) ? "" : "not ");
1628 } else {
1629 /* REVISIT show which size and format are selected ... */
1630 command_print(CMD_CTX, "current port size %ssupported",
1631 (config & (1 << 10)) ? "" : "not ");
1632 command_print(CMD_CTX, "current trace format %ssupported",
1633 (config & (1 << 11)) ? "" : "not ");
1634 }
1635 if (etm->bcd_vers >= 0x21)
1636 command_print(CMD_CTX, "fetch comparisons %ssupported",
1637 (config & (1 << 17)) ? "not " : "");
1638 command_print(CMD_CTX, "FIFO full %ssupported",
1639 (config & (1 << 8)) ? "" : "not ");
1640
1641 return ERROR_OK;
1642 }
1643
1644 COMMAND_HANDLER(handle_etm_status_command)
1645 {
1646 struct target *target;
1647 struct arm *arm;
1648 struct etm_context *etm;
1649 trace_status_t trace_status;
1650
1651 target = get_current_target(CMD_CTX);
1652 arm = target_to_arm(target);
1653 if (!is_arm(arm))
1654 {
1655 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1656 return ERROR_FAIL;
1657 }
1658
1659 etm = arm->etm;
1660 if (!etm)
1661 {
1662 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1663 return ERROR_FAIL;
1664 }
1665
1666 /* ETM status */
1667 if (etm->bcd_vers >= 0x11) {
1668 struct reg *reg;
1669
1670 reg = etm_reg_lookup(etm, ETM_STATUS);
1671 if (!reg)
1672 return ERROR_FAIL;
1673 if (etm_get_reg(reg) == ERROR_OK) {
1674 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1675
1676 command_print(CMD_CTX, "etm: %s%s%s%s",
1677 /* bit(1) == progbit */
1678 (etm->bcd_vers >= 0x12)
1679 ? ((s & (1 << 1))
1680 ? "disabled" : "enabled")
1681 : "?",
1682 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1683 ? " triggered" : "",
1684 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1685 ? " start/stop" : "",
1686 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1687 ? " untraced-overflow" : "");
1688 } /* else ignore and try showing trace port status */
1689 }
1690
1691 /* Trace Port Driver status */
1692 trace_status = etm->capture_driver->status(etm);
1693 if (trace_status == TRACE_IDLE)
1694 {
1695 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1696 }
1697 else
1698 {
1699 static char *completed = " completed";
1700 static char *running = " is running";
1701 static char *overflowed = ", overflowed";
1702 static char *triggered = ", triggered";
1703
1704 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1705 etm->capture_driver->name,
1706 (trace_status & TRACE_RUNNING) ? running : completed,
1707 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1708 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1709
1710 if (etm->trace_depth > 0)
1711 {
1712 command_print(CMD_CTX, "%i frames of trace data read",
1713 (int)(etm->trace_depth));
1714 }
1715 }
1716
1717 return ERROR_OK;
1718 }
1719
1720 COMMAND_HANDLER(handle_etm_image_command)
1721 {
1722 struct target *target;
1723 struct arm *arm;
1724 struct etm_context *etm_ctx;
1725
1726 if (CMD_ARGC < 1)
1727 {
1728 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1729 return ERROR_FAIL;
1730 }
1731
1732 target = get_current_target(CMD_CTX);
1733 arm = target_to_arm(target);
1734 if (!is_arm(arm))
1735 {
1736 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1737 return ERROR_FAIL;
1738 }
1739
1740 etm_ctx = arm->etm;
1741 if (!etm_ctx)
1742 {
1743 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1744 return ERROR_FAIL;
1745 }
1746
1747 if (etm_ctx->image)
1748 {
1749 image_close(etm_ctx->image);
1750 free(etm_ctx->image);
1751 command_print(CMD_CTX, "previously loaded image found and closed");
1752 }
1753
1754 etm_ctx->image = malloc(sizeof(struct image));
1755 etm_ctx->image->base_address_set = 0;
1756 etm_ctx->image->start_address_set = 0;
1757
1758 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1759 if (CMD_ARGC >= 2)
1760 {
1761 etm_ctx->image->base_address_set = 1;
1762 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address);
1763 }
1764 else
1765 {
1766 etm_ctx->image->base_address_set = 0;
1767 }
1768
1769 if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1770 {
1771 free(etm_ctx->image);
1772 etm_ctx->image = NULL;
1773 return ERROR_FAIL;
1774 }
1775
1776 return ERROR_OK;
1777 }
1778
1779 COMMAND_HANDLER(handle_etm_dump_command)
1780 {
1781 struct fileio file;
1782 struct target *target;
1783 struct arm *arm;
1784 struct etm_context *etm_ctx;
1785 uint32_t i;
1786
1787 if (CMD_ARGC != 1)
1788 {
1789 command_print(CMD_CTX, "usage: etm dump <file>");
1790 return ERROR_FAIL;
1791 }
1792
1793 target = get_current_target(CMD_CTX);
1794 arm = target_to_arm(target);
1795 if (!is_arm(arm))
1796 {
1797 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1798 return ERROR_FAIL;
1799 }
1800
1801 etm_ctx = arm->etm;
1802 if (!etm_ctx)
1803 {
1804 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1805 return ERROR_FAIL;
1806 }
1807
1808 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1809 {
1810 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1811 return ERROR_OK;
1812 }
1813
1814 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1815 {
1816 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1817 command_print(CMD_CTX, "trace capture not completed");
1818 return ERROR_FAIL;
1819 }
1820
1821 /* read the trace data if it wasn't read already */
1822 if (etm_ctx->trace_depth == 0)
1823 etm_ctx->capture_driver->read_trace(etm_ctx);
1824
1825 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1826 {
1827 return ERROR_FAIL;
1828 }
1829
1830 fileio_write_u32(&file, etm_ctx->capture_status);
1831 fileio_write_u32(&file, etm_ctx->control);
1832 fileio_write_u32(&file, etm_ctx->trace_depth);
1833
1834 for (i = 0; i < etm_ctx->trace_depth; i++)
1835 {
1836 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1837 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1838 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1839 }
1840
1841 fileio_close(&file);
1842
1843 return ERROR_OK;
1844 }
1845
1846 COMMAND_HANDLER(handle_etm_load_command)
1847 {
1848 struct fileio file;
1849 struct target *target;
1850 struct arm *arm;
1851 struct etm_context *etm_ctx;
1852 uint32_t i;
1853
1854 if (CMD_ARGC != 1)
1855 {
1856 command_print(CMD_CTX, "usage: etm load <file>");
1857 return ERROR_FAIL;
1858 }
1859
1860 target = get_current_target(CMD_CTX);
1861 arm = target_to_arm(target);
1862 if (!is_arm(arm))
1863 {
1864 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1865 return ERROR_FAIL;
1866 }
1867
1868 etm_ctx = arm->etm;
1869 if (!etm_ctx)
1870 {
1871 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1872 return ERROR_FAIL;
1873 }
1874
1875 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1876 {
1877 command_print(CMD_CTX, "trace capture running, stop first");
1878 return ERROR_FAIL;
1879 }
1880
1881 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1882 {
1883 return ERROR_FAIL;
1884 }
1885
1886 if (file.size % 4)
1887 {
1888 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1889 fileio_close(&file);
1890 return ERROR_FAIL;
1891 }
1892
1893 if (etm_ctx->trace_depth > 0)
1894 {
1895 free(etm_ctx->trace_data);
1896 etm_ctx->trace_data = NULL;
1897 }
1898
1899 {
1900 uint32_t tmp;
1901 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1902 fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
1903 fileio_read_u32(&file, &etm_ctx->trace_depth);
1904 }
1905 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1906 if (etm_ctx->trace_data == NULL)
1907 {
1908 command_print(CMD_CTX, "not enough memory to perform operation");
1909 fileio_close(&file);
1910 return ERROR_FAIL;
1911 }
1912
1913 for (i = 0; i < etm_ctx->trace_depth; i++)
1914 {
1915 uint32_t pipestat, packet, flags;
1916 fileio_read_u32(&file, &pipestat);
1917 fileio_read_u32(&file, &packet);
1918 fileio_read_u32(&file, &flags);
1919 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1920 etm_ctx->trace_data[i].packet = packet & 0xffff;
1921 etm_ctx->trace_data[i].flags = flags;
1922 }
1923
1924 fileio_close(&file);
1925
1926 return ERROR_OK;
1927 }
1928
1929 COMMAND_HANDLER(handle_etm_start_command)
1930 {
1931 struct target *target;
1932 struct arm *arm;
1933 struct etm_context *etm_ctx;
1934 struct reg *etm_ctrl_reg;
1935
1936 target = get_current_target(CMD_CTX);
1937 arm = target_to_arm(target);
1938 if (!is_arm(arm))
1939 {
1940 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1941 return ERROR_FAIL;
1942 }
1943
1944 etm_ctx = arm->etm;
1945 if (!etm_ctx)
1946 {
1947 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1948 return ERROR_FAIL;
1949 }
1950
1951 /* invalidate old tracing data */
1952 etm_ctx->capture_status = TRACE_IDLE;
1953 if (etm_ctx->trace_depth > 0)
1954 {
1955 free(etm_ctx->trace_data);
1956 etm_ctx->trace_data = NULL;
1957 }
1958 etm_ctx->trace_depth = 0;
1959
1960 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1961 if (!etm_ctrl_reg)
1962 return ERROR_FAIL;
1963
1964 etm_get_reg(etm_ctrl_reg);
1965
1966 /* Clear programming bit (10), set port selection bit (11) */
1967 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1968
1969 etm_store_reg(etm_ctrl_reg);
1970 jtag_execute_queue();
1971
1972 etm_ctx->capture_driver->start_capture(etm_ctx);
1973
1974 return ERROR_OK;
1975 }
1976
1977 COMMAND_HANDLER(handle_etm_stop_command)
1978 {
1979 struct target *target;
1980 struct arm *arm;
1981 struct etm_context *etm_ctx;
1982 struct reg *etm_ctrl_reg;
1983
1984 target = get_current_target(CMD_CTX);
1985 arm = target_to_arm(target);
1986 if (!is_arm(arm))
1987 {
1988 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1989 return ERROR_FAIL;
1990 }
1991
1992 etm_ctx = arm->etm;
1993 if (!etm_ctx)
1994 {
1995 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1996 return ERROR_FAIL;
1997 }
1998
1999 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2000 if (!etm_ctrl_reg)
2001 return ERROR_FAIL;
2002
2003 etm_get_reg(etm_ctrl_reg);
2004
2005 /* Set programming bit (10), clear port selection bit (11) */
2006 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2007
2008 etm_store_reg(etm_ctrl_reg);
2009 jtag_execute_queue();
2010
2011 etm_ctx->capture_driver->stop_capture(etm_ctx);
2012
2013 return ERROR_OK;
2014 }
2015
2016 COMMAND_HANDLER(handle_etm_trigger_debug_command)
2017 {
2018 struct target *target;
2019 struct arm *arm;
2020 struct etm_context *etm;
2021
2022 target = get_current_target(CMD_CTX);
2023 arm = target_to_arm(target);
2024 if (!is_arm(arm))
2025 {
2026 command_print(CMD_CTX, "ETM: %s isn't an ARM",
2027 target_name(target));
2028 return ERROR_FAIL;
2029 }
2030
2031 etm = arm->etm;
2032 if (!etm)
2033 {
2034 command_print(CMD_CTX, "ETM: no ETM configured for %s",
2035 target_name(target));
2036 return ERROR_FAIL;
2037 }
2038
2039 if (CMD_ARGC == 1) {
2040 struct reg *etm_ctrl_reg;
2041 bool dbgrq;
2042
2043 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
2044 if (!etm_ctrl_reg)
2045 return ERROR_FAIL;
2046
2047 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
2048 if (dbgrq)
2049 etm->control |= ETM_CTRL_DBGRQ;
2050 else
2051 etm->control &= ~ETM_CTRL_DBGRQ;
2052
2053 /* etm->control will be written to hardware
2054 * the next time an "etm start" is issued.
2055 */
2056 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
2057 }
2058
2059 command_print(CMD_CTX, "ETM: %s debug halt",
2060 (etm->control & ETM_CTRL_DBGRQ)
2061 ? "triggers"
2062 : "does not trigger");
2063 return ERROR_OK;
2064 }
2065
2066 COMMAND_HANDLER(handle_etm_analyze_command)
2067 {
2068 struct target *target;
2069 struct arm *arm;
2070 struct etm_context *etm_ctx;
2071 int retval;
2072
2073 target = get_current_target(CMD_CTX);
2074 arm = target_to_arm(target);
2075 if (!is_arm(arm))
2076 {
2077 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2078 return ERROR_FAIL;
2079 }
2080
2081 etm_ctx = arm->etm;
2082 if (!etm_ctx)
2083 {
2084 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2085 return ERROR_FAIL;
2086 }
2087
2088 if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2089 {
2090 switch (retval)
2091 {
2092 case ERROR_ETM_ANALYSIS_FAILED:
2093 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2094 break;
2095 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2096 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2097 break;
2098 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2099 command_print(CMD_CTX, "no image available for trace analysis");
2100 break;
2101 default:
2102 command_print(CMD_CTX, "unknown error: %i", retval);
2103 }
2104 }
2105
2106 return retval;
2107 }
2108
2109 static const struct command_registration etm_config_command_handlers[] = {
2110 {
2111 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2112 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2113 *
2114 * Also, these parameters don't match ETM v3+ modules...
2115 */
2116 .name = "config",
2117 .handler = handle_etm_config_command,
2118 .mode = COMMAND_CONFIG,
2119 .help = "Set up ETM output port.",
2120 .usage = "target port_width port_mode clocking capture_driver",
2121 },
2122 COMMAND_REGISTRATION_DONE
2123 };
2124 const struct command_registration etm_command_handlers[] = {
2125 {
2126 .name = "etm",
2127 .mode = COMMAND_ANY,
2128 .help = "Emebdded Trace Macrocell command group",
2129 .chain = etm_config_command_handlers,
2130 },
2131 COMMAND_REGISTRATION_DONE
2132 };
2133
2134 static const struct command_registration etm_exec_command_handlers[] = {
2135 {
2136 .name = "tracemode",
2137 .handler = handle_etm_tracemode_command,
2138 .mode = COMMAND_EXEC,
2139 .help = "configure/display trace mode",
2140 .usage = "('none'|'data'|'address'|'all') "
2141 "context_id_bits "
2142 "['enable'|'disable'] "
2143 "['enable'|'disable']",
2144 },
2145 {
2146 .name = "info",
2147 .handler = handle_etm_info_command,
2148 .mode = COMMAND_EXEC,
2149 .help = "display info about the current target's ETM",
2150 },
2151 {
2152 .name = "status",
2153 .handler = handle_etm_status_command,
2154 .mode = COMMAND_EXEC,
2155 .help = "display current target's ETM status",
2156 },
2157 {
2158 .name = "start",
2159 .handler = handle_etm_start_command,
2160 .mode = COMMAND_EXEC,
2161 .help = "start ETM trace collection",
2162 },
2163 {
2164 .name = "stop",
2165 .handler = handle_etm_stop_command,
2166 .mode = COMMAND_EXEC,
2167 .help = "stop ETM trace collection",
2168 },
2169 {
2170 .name = "trigger_debug",
2171 .handler = handle_etm_trigger_debug_command,
2172 .mode = COMMAND_EXEC,
2173 .help = "enable/disable debug entry on trigger",
2174 .usage = "['enable'|'disable']",
2175 },
2176 {
2177 .name = "analyze",
2178 .handler = handle_etm_analyze_command,
2179 .mode = COMMAND_EXEC,
2180 .help = "analyze collected ETM trace",
2181 },
2182 {
2183 .name = "image",
2184 .handler = handle_etm_image_command,
2185 .mode = COMMAND_EXEC,
2186 .help = "load image from file with optional offset",
2187 .usage = "filename [offset]",
2188 },
2189 {
2190 .name = "dump",
2191 .handler = handle_etm_dump_command,
2192 .mode = COMMAND_EXEC,
2193 .help = "dump captured trace data to file",
2194 .usage = "filename",
2195 },
2196 {
2197 .name = "load",
2198 .handler = handle_etm_load_command,
2199 .mode = COMMAND_EXEC,
2200 .help = "load trace data for analysis <file>",
2201 },
2202 COMMAND_REGISTRATION_DONE
2203 };
2204
2205 static int etm_register_user_commands(struct command_context *cmd_ctx)
2206 {
2207 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2208 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2209 }
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