1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "arm_disassembler.h"
31 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
33 * ETM modules collect instruction and/or data trace information, compress
34 * it, and transfer it to a debugging host through either a (buffered) trace
35 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
37 * There are several generations of these modules. Original versions have
38 * JTAG access through a dedicated scan chain. Recent versions have added
39 * access via coprocessor instructions, memory addressing, and the ARM Debug
40 * Interface v5 (ADIv5); and phased out direct JTAG access.
42 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
43 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
44 * implying non-JTAG connectivity options.
46 * Relevant documentation includes:
47 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
48 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
49 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
52 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
62 uint8_t size
; /* low-N of 32 bits */
63 uint8_t mode
; /* RO, WO, RW */
64 uint8_t bcd_vers
; /* 1.0, 2.0, etc */
69 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
70 * (Or on some processors, through coprocessor operations.)
71 * Newer versions of ETM make some W/O registers R/W, and
72 * provide definitions for some previously-unused bits.
75 /* basic registers that are always there given the right ETM version */
76 static const struct etm_reg_info etm_core
[] = {
77 /* NOTE: we "know" ETM_CONFIG is listed first */
78 { ETM_CONFIG
, 32, RO
, 0x10, "ETM_config", },
80 /* ETM Trace Registers */
81 { ETM_CTRL
, 32, RW
, 0x10, "ETM_ctrl", },
82 { ETM_TRIG_EVENT
, 17, WO
, 0x10, "ETM_trig_event", },
83 { ETM_ASIC_CTRL
, 8, WO
, 0x10, "ETM_asic_ctrl", },
84 { ETM_STATUS
, 3, RO
, 0x11, "ETM_status", },
85 { ETM_SYS_CONFIG
, 9, RO
, 0x12, "ETM_sys_config", },
87 /* TraceEnable configuration */
88 { ETM_TRACE_RESOURCE_CTRL
, 32, WO
, 0x12, "ETM_trace_resource_ctrl", },
89 { ETM_TRACE_EN_CTRL2
, 16, WO
, 0x12, "ETM_trace_en_ctrl2", },
90 { ETM_TRACE_EN_EVENT
, 17, WO
, 0x10, "ETM_trace_en_event", },
91 { ETM_TRACE_EN_CTRL1
, 26, WO
, 0x10, "ETM_trace_en_ctrl1", },
93 /* ViewData configuration (data trace) */
94 { ETM_VIEWDATA_EVENT
, 17, WO
, 0x10, "ETM_viewdata_event", },
95 { ETM_VIEWDATA_CTRL1
, 32, WO
, 0x10, "ETM_viewdata_ctrl1", },
96 { ETM_VIEWDATA_CTRL2
, 32, WO
, 0x10, "ETM_viewdata_ctrl2", },
97 { ETM_VIEWDATA_CTRL3
, 17, WO
, 0x10, "ETM_viewdata_ctrl3", },
99 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
101 { 0x78, 12, WO
, 0x20, "ETM_sync_freq", },
102 { 0x79, 32, RO
, 0x20, "ETM_id", },
105 static const struct etm_reg_info etm_fifofull
[] = {
106 /* FIFOFULL configuration */
107 { ETM_FIFOFULL_REGION
, 25, WO
, 0x10, "ETM_fifofull_region", },
108 { ETM_FIFOFULL_LEVEL
, 8, WO
, 0x10, "ETM_fifofull_level", },
111 static const struct etm_reg_info etm_addr_comp
[] = {
112 /* Address comparator register pairs */
113 #define ADDR_COMPARATOR(i) \
114 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
115 "ETM_addr_" #i "_comparator_value", }, \
116 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
117 "ETM_addr_" #i "_access_type", }
135 #undef ADDR_COMPARATOR
138 static const struct etm_reg_info etm_data_comp
[] = {
139 /* Data Value Comparators (NOTE: odd addresses are reserved) */
140 #define DATA_COMPARATOR(i) \
141 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
142 "ETM_data_" #i "_comparator_value", }, \
143 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
144 "ETM_data_" #i "_comparator_mask", }
153 #undef DATA_COMPARATOR
156 static const struct etm_reg_info etm_counters
[] = {
157 #define ETM_COUNTER(i) \
158 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
159 "ETM_counter_" #i "_reload_value", }, \
160 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
161 "ETM_counter_" #i "_enable", }, \
162 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
163 "ETM_counter_" #i "_reload_event", }, \
164 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
165 "ETM_counter_" #i "_value", }
173 static const struct etm_reg_info etm_sequencer
[] = {
175 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
176 "ETM_sequencer_event" #i, }
177 ETM_SEQ(0), /* 1->2 */
178 ETM_SEQ(1), /* 2->1 */
179 ETM_SEQ(2), /* 2->3 */
180 ETM_SEQ(3), /* 3->1 */
181 ETM_SEQ(4), /* 3->2 */
182 ETM_SEQ(5), /* 1->3 */
185 { ETM_SEQUENCER_STATE
, 2, RO
, 0x10, "ETM_sequencer_state", },
188 static const struct etm_reg_info etm_outputs
[] = {
189 #define ETM_OUTPUT(i) \
190 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
191 "ETM_external_output" #i, }
201 /* registers from 0x6c..0x7f were added after ETMv1.3 */
203 /* Context ID Comparators */
204 { 0x6c, 32, RO
, 0x20, "ETM_contextid_comparator_value1", }
205 { 0x6d, 32, RO
, 0x20, "ETM_contextid_comparator_value2", }
206 { 0x6e, 32, RO
, 0x20, "ETM_contextid_comparator_value3", }
207 { 0x6f, 32, RO
, 0x20, "ETM_contextid_comparator_mask", }
210 static int etm_reg_arch_type
= -1;
212 static int etm_get_reg(reg_t
*reg
);
213 static int etm_read_reg_w_check(reg_t
*reg
,
214 uint8_t* check_value
, uint8_t* check_mask
);
215 static int etm_register_user_commands(struct command_context_s
*cmd_ctx
);
216 static int etm_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
);
217 static int etm_write_reg(reg_t
*reg
, uint32_t value
);
219 static command_t
*etm_cmd
;
222 /* Look up register by ID ... most ETM instances only
223 * support a subset of the possible registers.
225 static reg_t
*etm_reg_lookup(etm_context_t
*etm_ctx
, unsigned id
)
227 reg_cache_t
*cache
= etm_ctx
->reg_cache
;
230 for (i
= 0; i
< cache
->num_regs
; i
++) {
231 struct etm_reg_s
*reg
= cache
->reg_list
[i
].arch_info
;
233 if (reg
->reg_info
->addr
== id
)
234 return &cache
->reg_list
[i
];
237 /* caller asking for nonexistent register is a bug! */
238 /* REVISIT say which of the N targets was involved */
239 LOG_ERROR("ETM: register 0x%02x not available", id
);
243 static void etm_reg_add(unsigned bcd_vers
, arm_jtag_t
*jtag_info
,
244 reg_cache_t
*cache
, etm_reg_t
*ereg
,
245 const struct etm_reg_info
*r
, unsigned nreg
)
247 reg_t
*reg
= cache
->reg_list
;
249 reg
+= cache
->num_regs
;
250 ereg
+= cache
->num_regs
;
252 /* add up to "nreg" registers from "r", if supported by this
253 * version of the ETM, to the specified cache.
255 for (; nreg
--; r
++) {
257 /* this ETM may be too old to have some registers */
258 if (r
->bcd_vers
> bcd_vers
)
263 reg
->value
= &ereg
->value
;
264 reg
->arch_info
= ereg
;
265 reg
->arch_type
= etm_reg_arch_type
;
270 ereg
->jtag_info
= jtag_info
;
275 reg_cache_t
*etm_build_reg_cache(target_t
*target
,
276 arm_jtag_t
*jtag_info
, etm_context_t
*etm_ctx
)
278 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
279 reg_t
*reg_list
= NULL
;
280 etm_reg_t
*arch_info
= NULL
;
281 unsigned bcd_vers
, config
;
283 /* register a register arch-type for etm registers only once */
284 if (etm_reg_arch_type
== -1)
285 etm_reg_arch_type
= register_reg_arch_type(etm_get_reg
,
288 /* the actual registers are kept in two arrays */
289 reg_list
= calloc(128, sizeof(reg_t
));
290 arch_info
= calloc(128, sizeof(etm_reg_t
));
292 /* fill in values for the reg cache */
293 reg_cache
->name
= "etm registers";
294 reg_cache
->next
= NULL
;
295 reg_cache
->reg_list
= reg_list
;
296 reg_cache
->num_regs
= 0;
298 /* add ETM_CONFIG, then parse its values to see
299 * which other registers exist in this ETM
301 etm_reg_add(0x10, jtag_info
, reg_cache
, arch_info
,
304 etm_get_reg(reg_list
);
305 etm_ctx
->config
= buf_get_u32((void *)&arch_info
->value
, 0, 32);
306 config
= etm_ctx
->config
;
308 /* figure ETM version then add base registers */
309 if (config
& (1 << 31)) {
311 LOG_WARNING("ETMv2+ support is incomplete");
313 /* REVISIT read ID register, distinguish ETMv3.3 etc;
314 * don't presume trace start/stop support is present;
315 * and include any context ID comparator registers.
318 switch (config
>> 28) {
335 LOG_WARNING("Bad ETMv1 protocol %d", config
>> 28);
342 etm_ctx
->bcd_vers
= bcd_vers
;
343 LOG_INFO("ETM v%d.%d", bcd_vers
>> 4, bcd_vers
& 0xf);
345 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
346 etm_core
+ 1, ARRAY_SIZE(etm_core
) - 1);
348 /* address and data comparators; counters; outputs */
349 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
350 etm_addr_comp
, 4 * (0x0f & (config
>> 0)));
351 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
352 etm_data_comp
, 2 * (0x0f & (config
>> 4)));
353 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
354 etm_counters
, 4 * (0x07 & (config
>> 13)));
355 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
356 etm_outputs
, (0x07 & (config
>> 20)));
358 /* FIFOFULL presence is optional
359 * REVISIT for ETMv1.2 and later, don't bother adding this
360 * unless ETM_SYS_CONFIG says it's also *supported* ...
362 if (config
& (1 << 23))
363 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
364 etm_fifofull
, ARRAY_SIZE(etm_fifofull
));
366 /* sequencer is optional (for state-dependant triggering) */
367 if (config
& (1 << 16))
368 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
369 etm_sequencer
, ARRAY_SIZE(etm_sequencer
));
371 /* REVISIT could realloc and likely save half the memory
372 * in the two chunks we allocated...
375 /* the ETM might have an ETB connected */
376 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0)
378 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
382 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
389 reg_cache
->next
= etb_build_reg_cache(etb
);
391 etb
->reg_cache
= reg_cache
->next
;
398 static int etm_read_reg(reg_t
*reg
)
400 return etm_read_reg_w_check(reg
, NULL
, NULL
);
403 static int etm_store_reg(reg_t
*reg
)
405 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
408 int etm_setup(target_t
*target
)
411 uint32_t etm_ctrl_value
;
412 struct arm
*arm
= target_to_arm(target
);
413 etm_context_t
*etm_ctx
= arm
->etm
;
416 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
420 /* initialize some ETM control register settings */
421 etm_get_reg(etm_ctrl_reg
);
422 etm_ctrl_value
= buf_get_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
);
424 /* clear the ETM powerdown bit (0) */
425 etm_ctrl_value
&= ~0x1;
427 /* configure port width (6:4), mode (17:16) and clocking (13) */
428 etm_ctrl_value
= (etm_ctrl_value
&
429 ~ETM_PORT_WIDTH_MASK
& ~ETM_PORT_MODE_MASK
& ~ETM_PORT_CLOCK_MASK
)
432 buf_set_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
, etm_ctrl_value
);
433 etm_store_reg(etm_ctrl_reg
);
435 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
438 if ((retval
= etm_ctx
->capture_driver
->init(etm_ctx
)) != ERROR_OK
)
440 LOG_ERROR("ETM capture driver initialization failed");
446 static int etm_get_reg(reg_t
*reg
)
450 if ((retval
= etm_read_reg(reg
)) != ERROR_OK
)
452 LOG_ERROR("BUG: error scheduling etm register read");
456 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
458 LOG_ERROR("register read failed");
465 static int etm_read_reg_w_check(reg_t
*reg
,
466 uint8_t* check_value
, uint8_t* check_mask
)
468 etm_reg_t
*etm_reg
= reg
->arch_info
;
469 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
470 uint8_t reg_addr
= r
->addr
& 0x7f;
471 scan_field_t fields
[3];
473 if (etm_reg
->reg_info
->mode
== WO
) {
474 LOG_ERROR("BUG: can't read write-only register %s", r
->name
);
475 return ERROR_INVALID_ARGUMENTS
;
478 LOG_DEBUG("%s (%u)", r
->name
, reg_addr
);
480 jtag_set_end_state(TAP_IDLE
);
481 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
482 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
484 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
485 fields
[0].num_bits
= 32;
486 fields
[0].out_value
= reg
->value
;
487 fields
[0].in_value
= NULL
;
488 fields
[0].check_value
= NULL
;
489 fields
[0].check_mask
= NULL
;
491 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
492 fields
[1].num_bits
= 7;
493 fields
[1].out_value
= malloc(1);
494 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
495 fields
[1].in_value
= NULL
;
496 fields
[1].check_value
= NULL
;
497 fields
[1].check_mask
= NULL
;
499 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
500 fields
[2].num_bits
= 1;
501 fields
[2].out_value
= malloc(1);
502 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
503 fields
[2].in_value
= NULL
;
504 fields
[2].check_value
= NULL
;
505 fields
[2].check_mask
= NULL
;
507 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
509 fields
[0].in_value
= reg
->value
;
510 fields
[0].check_value
= check_value
;
511 fields
[0].check_mask
= check_mask
;
513 jtag_add_dr_scan_check(3, fields
, jtag_get_end_state());
515 free(fields
[1].out_value
);
516 free(fields
[2].out_value
);
521 static int etm_set_reg(reg_t
*reg
, uint32_t value
)
525 if ((retval
= etm_write_reg(reg
, value
)) != ERROR_OK
)
527 LOG_ERROR("BUG: error scheduling etm register write");
531 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
538 static int etm_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
)
542 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
544 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
546 LOG_ERROR("register write failed");
552 static int etm_write_reg(reg_t
*reg
, uint32_t value
)
554 etm_reg_t
*etm_reg
= reg
->arch_info
;
555 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
556 uint8_t reg_addr
= r
->addr
& 0x7f;
557 scan_field_t fields
[3];
559 if (etm_reg
->reg_info
->mode
== RO
) {
560 LOG_ERROR("BUG: can't write read--only register %s", r
->name
);
561 return ERROR_INVALID_ARGUMENTS
;
564 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32
"", r
->name
, reg_addr
, value
);
566 jtag_set_end_state(TAP_IDLE
);
567 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
568 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
570 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
571 fields
[0].num_bits
= 32;
573 fields
[0].out_value
= tmp1
;
574 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
575 fields
[0].in_value
= NULL
;
577 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
578 fields
[1].num_bits
= 7;
580 fields
[1].out_value
= &tmp2
;
581 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
582 fields
[1].in_value
= NULL
;
584 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
585 fields
[2].num_bits
= 1;
587 fields
[2].out_value
= &tmp3
;
588 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
589 fields
[2].in_value
= NULL
;
591 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
597 /* ETM trace analysis functionality
600 extern etm_capture_driver_t etm_dummy_capture_driver
;
601 #if BUILD_OOCD_TRACE == 1
602 extern etm_capture_driver_t oocd_trace_capture_driver
;
605 static etm_capture_driver_t
*etm_capture_drivers
[] =
608 &etm_dummy_capture_driver
,
609 #if BUILD_OOCD_TRACE == 1
610 &oocd_trace_capture_driver
,
615 static int etm_read_instruction(etm_context_t
*ctx
, arm_instruction_t
*instruction
)
624 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
626 /* search for the section the current instruction belongs to */
627 for (i
= 0; i
< ctx
->image
->num_sections
; i
++)
629 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
630 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
> ctx
->current_pc
))
639 /* current instruction couldn't be found in the image */
640 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
643 if (ctx
->core_state
== ARMV4_5_STATE_ARM
)
646 if ((retval
= image_read_section(ctx
->image
, section
,
647 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
648 4, buf
, &size_read
)) != ERROR_OK
)
650 LOG_ERROR("error while reading instruction: %i", retval
);
651 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
653 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
654 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
656 else if (ctx
->core_state
== ARMV4_5_STATE_THUMB
)
659 if ((retval
= image_read_section(ctx
->image
, section
,
660 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
661 2, buf
, &size_read
)) != ERROR_OK
)
663 LOG_ERROR("error while reading instruction: %i", retval
);
664 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
666 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
667 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
669 else if (ctx
->core_state
== ARMV4_5_STATE_JAZELLE
)
671 LOG_ERROR("BUG: tracing of jazelle code not supported");
676 LOG_ERROR("BUG: unknown core state encountered");
683 static int etmv1_next_packet(etm_context_t
*ctx
, uint8_t *packet
, int apo
)
685 while (ctx
->data_index
< ctx
->trace_depth
)
687 /* if the caller specified an address packet offset, skip until the
688 * we reach the n-th cycle marked with tracesync */
691 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
702 /* no tracedata output during a TD cycle
703 * or in a trigger cycle */
704 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
705 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
))
712 if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
)
714 if (ctx
->data_half
== 0)
716 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
721 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
726 else if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
728 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
733 /* on a 4-bit port, a packet will be output during two consecutive cycles */
734 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
737 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
738 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
739 ctx
->data_index
+= 2;
748 static int etmv1_branch_address(etm_context_t
*ctx
)
756 /* quit analysis if less than two cycles are left in the trace
757 * because we can't extract the APO */
758 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
761 /* a BE could be output during an APO cycle, skip the current
762 * and continue with the new one */
763 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
765 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
768 /* address packet offset encoded in the next two cycles' pipestat bits */
769 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
770 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
772 /* count number of tracesync cycles between current pipe_index and data_index
773 * i.e. the number of tracesyncs that data_index already passed by
774 * to subtract them from the APO */
775 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++)
777 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
781 /* extract up to four 7-bit packets */
783 if ((retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0)) != 0)
785 ctx
->last_branch
&= ~(0x7f << shift
);
786 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
788 } while ((packet
& 0x80) && (shift
< 28));
790 /* one last packet holding 4 bits of the address, plus the branch reason code */
791 if ((shift
== 28) && (packet
& 0x80))
793 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
795 ctx
->last_branch
&= 0x0fffffff;
796 ctx
->last_branch
|= (packet
& 0x0f) << 28;
797 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
802 ctx
->last_branch_reason
= 0;
810 /* if a full address was output, we might have branched into Jazelle state */
811 if ((shift
== 32) && (packet
& 0x80))
813 ctx
->core_state
= ARMV4_5_STATE_JAZELLE
;
817 /* if we didn't branch into Jazelle state, the current processor state is
818 * encoded in bit 0 of the branch target address */
819 if (ctx
->last_branch
& 0x1)
821 ctx
->core_state
= ARMV4_5_STATE_THUMB
;
822 ctx
->last_branch
&= ~0x1;
826 ctx
->core_state
= ARMV4_5_STATE_ARM
;
827 ctx
->last_branch
&= ~0x3;
834 static int etmv1_data(etm_context_t
*ctx
, int size
, uint32_t *data
)
840 for (j
= 0; j
< size
; j
++)
842 if ((retval
= etmv1_next_packet(ctx
, &buf
[j
], 0)) != 0)
848 LOG_ERROR("TODO: add support for 64-bit values");
852 *data
= target_buffer_get_u32(ctx
->target
, buf
);
854 *data
= target_buffer_get_u16(ctx
->target
, buf
);
863 static int etmv1_analyze_trace(etm_context_t
*ctx
, struct command_context_s
*cmd_ctx
)
866 arm_instruction_t instruction
;
868 /* read the trace data if it wasn't read already */
869 if (ctx
->trace_depth
== 0)
870 ctx
->capture_driver
->read_trace(ctx
);
872 /* start at the beginning of the captured trace */
877 /* neither the PC nor the data pointer are valid */
881 while (ctx
->pipe_index
< ctx
->trace_depth
)
883 uint8_t pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
884 uint32_t next_pc
= ctx
->current_pc
;
885 uint32_t old_data_index
= ctx
->data_index
;
886 uint32_t old_data_half
= ctx
->data_half
;
887 uint32_t old_index
= ctx
->pipe_index
;
888 uint32_t last_instruction
= ctx
->last_instruction
;
890 int current_pc_ok
= ctx
->pc_ok
;
892 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
894 command_print(cmd_ctx
, "--- trigger ---");
897 /* instructions execute in IE/D or BE/D cycles */
898 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
899 ctx
->last_instruction
= ctx
->pipe_index
;
901 /* if we don't have a valid pc skip until we reach an indirect branch */
902 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
))
908 /* any indirect branch could have interrupted instruction flow
909 * - the branch reason code could indicate a trace discontinuity
910 * - a branch to the exception vectors indicates an exception
912 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
))
914 /* backup current data index, to be able to consume the branch address
915 * before examining data address and values
917 old_data_index
= ctx
->data_index
;
918 old_data_half
= ctx
->data_half
;
920 ctx
->last_instruction
= ctx
->pipe_index
;
922 if ((retval
= etmv1_branch_address(ctx
)) != 0)
924 /* negative return value from etmv1_branch_address means we ran out of packets,
925 * quit analysing the trace */
929 /* a positive return values means the current branch was abandoned,
930 * and a new branch was encountered in cycle ctx->pipe_index + retval;
932 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
933 ctx
->pipe_index
+= retval
;
937 /* skip over APO cycles */
938 ctx
->pipe_index
+= 2;
940 switch (ctx
->last_branch_reason
)
942 case 0x0: /* normal PC change */
943 next_pc
= ctx
->last_branch
;
945 case 0x1: /* tracing enabled */
946 command_print(cmd_ctx
, "--- tracing enabled at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
947 ctx
->current_pc
= ctx
->last_branch
;
951 case 0x2: /* trace restarted after FIFO overflow */
952 command_print(cmd_ctx
, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
953 ctx
->current_pc
= ctx
->last_branch
;
957 case 0x3: /* exit from debug state */
958 command_print(cmd_ctx
, "--- exit from debug state at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
959 ctx
->current_pc
= ctx
->last_branch
;
963 case 0x4: /* periodic synchronization point */
964 next_pc
= ctx
->last_branch
;
965 /* if we had no valid PC prior to this synchronization point,
966 * we have to move on with the next trace cycle
970 command_print(cmd_ctx
, "--- periodic synchronization point at 0x%8.8" PRIx32
" ---", next_pc
);
971 ctx
->current_pc
= next_pc
;
976 default: /* reserved */
977 LOG_ERROR("BUG: branch reason code 0x%" PRIx32
" is reserved", ctx
->last_branch_reason
);
981 /* if we got here the branch was a normal PC change
982 * (or a periodic synchronization point, which means the same for that matter)
983 * if we didn't accquire a complete PC continue with the next cycle
988 /* indirect branch to the exception vector means an exception occured */
989 if ((ctx
->last_branch
<= 0x20)
990 || ((ctx
->last_branch
>= 0xffff0000) && (ctx
->last_branch
<= 0xffff0020)))
992 if ((ctx
->last_branch
& 0xff) == 0x10)
994 command_print(cmd_ctx
, "data abort");
998 command_print(cmd_ctx
, "exception vector 0x%2.2" PRIx32
"", ctx
->last_branch
);
999 ctx
->current_pc
= ctx
->last_branch
;
1006 /* an instruction was executed (or not, depending on the condition flags)
1007 * retrieve it from the image for displaying */
1008 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
1009 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
1010 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4))))
1012 if ((retval
= etm_read_instruction(ctx
, &instruction
)) != ERROR_OK
)
1014 /* can't continue tracing with no image available */
1015 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
1019 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
1021 /* TODO: handle incomplete images
1022 * for now we just quit the analsysis*/
1027 cycles
= old_index
- last_instruction
;
1030 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
))
1032 uint32_t new_data_index
= ctx
->data_index
;
1033 uint32_t new_data_half
= ctx
->data_half
;
1035 /* in case of a branch with data, the branch target address was consumed before
1036 * we temporarily go back to the saved data index */
1037 if (pipestat
== STAT_BD
)
1039 ctx
->data_index
= old_data_index
;
1040 ctx
->data_half
= old_data_half
;
1043 if (ctx
->tracemode
& ETMV1_TRACE_ADDR
)
1049 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
1050 return ERROR_ETM_ANALYSIS_FAILED
;
1051 ctx
->last_ptr
&= ~(0x7f << shift
);
1052 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
1054 } while ((packet
& 0x80) && (shift
< 32));
1061 command_print(cmd_ctx
, "address: 0x%8.8" PRIx32
"", ctx
->last_ptr
);
1065 if (ctx
->tracemode
& ETMV1_TRACE_DATA
)
1067 if ((instruction
.type
== ARM_LDM
) || (instruction
.type
== ARM_STM
))
1070 for (i
= 0; i
< 16; i
++)
1072 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
1075 if (etmv1_data(ctx
, 4, &data
) != 0)
1076 return ERROR_ETM_ANALYSIS_FAILED
;
1077 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1081 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_STRH
))
1084 if (etmv1_data(ctx
, arm_access_size(&instruction
), &data
) != 0)
1085 return ERROR_ETM_ANALYSIS_FAILED
;
1086 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1090 /* restore data index after consuming BD address and data */
1091 if (pipestat
== STAT_BD
)
1093 ctx
->data_index
= new_data_index
;
1094 ctx
->data_half
= new_data_half
;
1099 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
1101 if (((instruction
.type
== ARM_B
) ||
1102 (instruction
.type
== ARM_BL
) ||
1103 (instruction
.type
== ARM_BLX
)) &&
1104 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff))
1106 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
1110 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
1113 else if (pipestat
== STAT_IN
)
1115 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
1118 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
))
1120 char cycles_text
[32] = "";
1122 /* if the trace was captured with cycle accurate tracing enabled,
1123 * output the number of cycles since the last executed instruction
1125 if (ctx
->tracemode
& ETMV1_CYCLE_ACCURATE
)
1127 snprintf(cycles_text
, 32, " (%i %s)",
1129 (cycles
== 1) ? "cycle" : "cycles");
1132 command_print(cmd_ctx
, "%s%s%s",
1134 (pipestat
== STAT_IN
) ? " (not executed)" : "",
1137 ctx
->current_pc
= next_pc
;
1139 /* packets for an instruction don't start on or before the preceding
1140 * functional pipestat (i.e. other than WT or TD)
1142 if (ctx
->data_index
<= ctx
->pipe_index
)
1144 ctx
->data_index
= ctx
->pipe_index
+ 1;
1149 ctx
->pipe_index
+= 1;
1155 static int handle_etm_tracemode_command_update(
1156 struct command_context_s
*cmd_ctx
,
1157 char **args
, etmv1_tracemode_t
*mode
)
1159 etmv1_tracemode_t tracemode
;
1161 /* what parts of data access are traced? */
1162 if (strcmp(args
[0], "none") == 0)
1163 tracemode
= ETMV1_TRACE_NONE
;
1164 else if (strcmp(args
[0], "data") == 0)
1165 tracemode
= ETMV1_TRACE_DATA
;
1166 else if (strcmp(args
[0], "address") == 0)
1167 tracemode
= ETMV1_TRACE_ADDR
;
1168 else if (strcmp(args
[0], "all") == 0)
1169 tracemode
= ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
;
1172 command_print(cmd_ctx
, "invalid option '%s'", args
[0]);
1173 return ERROR_INVALID_ARGUMENTS
;
1177 COMMAND_PARSE_NUMBER(u8
, args
[1], context_id
);
1181 tracemode
|= ETMV1_CONTEXTID_NONE
;
1184 tracemode
|= ETMV1_CONTEXTID_8
;
1187 tracemode
|= ETMV1_CONTEXTID_16
;
1190 tracemode
|= ETMV1_CONTEXTID_32
;
1193 command_print(cmd_ctx
, "invalid option '%s'", args
[1]);
1194 return ERROR_INVALID_ARGUMENTS
;
1197 if (strcmp(args
[2], "enable") == 0)
1198 tracemode
|= ETMV1_CYCLE_ACCURATE
;
1199 else if (strcmp(args
[2], "disable") == 0)
1203 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1204 return ERROR_INVALID_ARGUMENTS
;
1207 if (strcmp(args
[3], "enable") == 0)
1208 tracemode
|= ETMV1_BRANCH_OUTPUT
;
1209 else if (strcmp(args
[3], "disable") == 0)
1213 command_print(cmd_ctx
, "invalid option '%s'", args
[3]);
1214 return ERROR_INVALID_ARGUMENTS
;
1218 * - CPRT tracing (coprocessor register transfers)
1219 * - debug request (causes debug entry on trigger)
1220 * - stall on FIFOFULL (preventing tracedata lossage)
1227 static int handle_etm_tracemode_command(struct command_context_s
*cmd_ctx
,
1228 char *cmd
, char **args
, int argc
)
1230 target_t
*target
= get_current_target(cmd_ctx
);
1231 struct arm
*arm
= target_to_arm(target
);
1235 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1241 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1245 etmv1_tracemode_t tracemode
= etm
->tracemode
;
1252 handle_etm_tracemode_command_update(cmd_ctx
, args
, &tracemode
);
1255 command_print(cmd_ctx
, "usage: configure trace mode "
1256 "<none | data | address | all> "
1257 "<context id bits> <cycle accurate> <branch output>");
1262 * todo: fail if parameters were invalid for this hardware,
1263 * or couldn't be written; display actual hardware state...
1266 command_print(cmd_ctx
, "current tracemode configuration:");
1268 switch (tracemode
& ETMV1_TRACE_MASK
)
1270 case ETMV1_TRACE_NONE
:
1271 command_print(cmd_ctx
, "data tracing: none");
1273 case ETMV1_TRACE_DATA
:
1274 command_print(cmd_ctx
, "data tracing: data only");
1276 case ETMV1_TRACE_ADDR
:
1277 command_print(cmd_ctx
, "data tracing: address only");
1279 case ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
:
1280 command_print(cmd_ctx
, "data tracing: address and data");
1284 switch (tracemode
& ETMV1_CONTEXTID_MASK
)
1286 case ETMV1_CONTEXTID_NONE
:
1287 command_print(cmd_ctx
, "contextid tracing: none");
1289 case ETMV1_CONTEXTID_8
:
1290 command_print(cmd_ctx
, "contextid tracing: 8 bit");
1292 case ETMV1_CONTEXTID_16
:
1293 command_print(cmd_ctx
, "contextid tracing: 16 bit");
1295 case ETMV1_CONTEXTID_32
:
1296 command_print(cmd_ctx
, "contextid tracing: 32 bit");
1300 if (tracemode
& ETMV1_CYCLE_ACCURATE
)
1302 command_print(cmd_ctx
, "cycle-accurate tracing enabled");
1306 command_print(cmd_ctx
, "cycle-accurate tracing disabled");
1309 if (tracemode
& ETMV1_BRANCH_OUTPUT
)
1311 command_print(cmd_ctx
, "full branch address output enabled");
1315 command_print(cmd_ctx
, "full branch address output disabled");
1318 /* only update ETM_CTRL register if tracemode changed */
1319 if (etm
->tracemode
!= tracemode
)
1321 reg_t
*etm_ctrl_reg
;
1323 etm_ctrl_reg
= etm_reg_lookup(etm
, ETM_CTRL
);
1327 etm_get_reg(etm_ctrl_reg
);
1329 buf_set_u32(etm_ctrl_reg
->value
, 2, 2, tracemode
& ETMV1_TRACE_MASK
);
1330 buf_set_u32(etm_ctrl_reg
->value
, 14, 2, (tracemode
& ETMV1_CONTEXTID_MASK
) >> 4);
1331 buf_set_u32(etm_ctrl_reg
->value
, 12, 1, (tracemode
& ETMV1_CYCLE_ACCURATE
) >> 8);
1332 buf_set_u32(etm_ctrl_reg
->value
, 8, 1, (tracemode
& ETMV1_BRANCH_OUTPUT
) >> 9);
1333 etm_store_reg(etm_ctrl_reg
);
1335 etm
->tracemode
= tracemode
;
1337 /* invalidate old trace data */
1338 etm
->capture_status
= TRACE_IDLE
;
1339 if (etm
->trace_depth
> 0)
1341 free(etm
->trace_data
);
1342 etm
->trace_data
= NULL
;
1344 etm
->trace_depth
= 0;
1350 static int handle_etm_config_command(struct command_context_s
*cmd_ctx
,
1351 char *cmd
, char **args
, int argc
)
1355 etm_portmode_t portmode
= 0x0;
1356 struct etm
*etm_ctx
;
1360 return ERROR_COMMAND_SYNTAX_ERROR
;
1362 target
= get_target(args
[0]);
1365 LOG_ERROR("target '%s' not defined", args
[0]);
1369 arm
= target_to_arm(target
);
1371 command_print(cmd_ctx
, "target '%s' is '%s'; not an ARM",
1372 target
->cmd_name
, target_get_name(target
));
1377 COMMAND_PARSE_NUMBER(u8
, args
[1], port_width
);
1381 portmode
|= ETM_PORT_4BIT
;
1384 portmode
|= ETM_PORT_8BIT
;
1387 portmode
|= ETM_PORT_16BIT
;
1390 command_print(cmd_ctx
, "unsupported ETM port width '%s', must be 4, 8 or 16", args
[1]);
1394 if (strcmp("normal", args
[2]) == 0)
1396 portmode
|= ETM_PORT_NORMAL
;
1398 else if (strcmp("multiplexed", args
[2]) == 0)
1400 portmode
|= ETM_PORT_MUXED
;
1402 else if (strcmp("demultiplexed", args
[2]) == 0)
1404 portmode
|= ETM_PORT_DEMUXED
;
1408 command_print(cmd_ctx
, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args
[2]);
1412 if (strcmp("half", args
[3]) == 0)
1414 portmode
|= ETM_PORT_HALF_CLOCK
;
1416 else if (strcmp("full", args
[3]) == 0)
1418 portmode
|= ETM_PORT_FULL_CLOCK
;
1422 command_print(cmd_ctx
, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args
[3]);
1426 etm_ctx
= calloc(1, sizeof(etm_context_t
));
1428 LOG_DEBUG("out of memory");
1432 for (i
= 0; etm_capture_drivers
[i
]; i
++)
1434 if (strcmp(args
[4], etm_capture_drivers
[i
]->name
) == 0)
1437 if ((retval
= etm_capture_drivers
[i
]->register_commands(cmd_ctx
)) != ERROR_OK
)
1443 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1449 if (!etm_capture_drivers
[i
])
1451 /* no supported capture driver found, don't register an ETM */
1453 LOG_ERROR("trace capture driver '%s' not found", args
[4]);
1457 etm_ctx
->target
= target
;
1458 etm_ctx
->trigger_percent
= 50;
1459 etm_ctx
->trace_data
= NULL
;
1460 etm_ctx
->portmode
= portmode
;
1461 etm_ctx
->core_state
= ARMV4_5_STATE_ARM
;
1465 return etm_register_user_commands(cmd_ctx
);
1468 static int handle_etm_info_command(struct command_context_s
*cmd_ctx
,
1469 char *cmd
, char **args
, int argc
)
1474 reg_t
*etm_sys_config_reg
;
1477 target
= get_current_target(cmd_ctx
);
1478 arm
= target_to_arm(target
);
1481 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1488 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1492 command_print(cmd_ctx
, "ETM v%d.%d",
1493 etm
->bcd_vers
>> 4, etm
->bcd_vers
& 0xf);
1494 command_print(cmd_ctx
, "pairs of address comparators: %i",
1495 (int) (etm
->config
>> 0) & 0x0f);
1496 command_print(cmd_ctx
, "data comparators: %i",
1497 (int) (etm
->config
>> 4) & 0x0f);
1498 command_print(cmd_ctx
, "memory map decoders: %i",
1499 (int) (etm
->config
>> 8) & 0x1f);
1500 command_print(cmd_ctx
, "number of counters: %i",
1501 (int) (etm
->config
>> 13) & 0x07);
1502 command_print(cmd_ctx
, "sequencer %spresent",
1503 (int) (etm
->config
& (1 << 16)) ? "" : "not ");
1504 command_print(cmd_ctx
, "number of ext. inputs: %i",
1505 (int) (etm
->config
>> 17) & 0x07);
1506 command_print(cmd_ctx
, "number of ext. outputs: %i",
1507 (int) (etm
->config
>> 20) & 0x07);
1508 command_print(cmd_ctx
, "FIFO full %spresent",
1509 (int) (etm
->config
& (1 << 23)) ? "" : "not ");
1510 if (etm
->bcd_vers
< 0x20)
1511 command_print(cmd_ctx
, "protocol version: %i",
1512 (int) (etm
->config
>> 28) & 0x07);
1514 command_print(cmd_ctx
, "trace start/stop %spresent",
1515 (etm
->config
& (1 << 26)) ? "" : "not ");
1516 command_print(cmd_ctx
, "number of context comparators: %i",
1517 (int) (etm
->config
>> 24) & 0x03);
1520 /* SYS_CONFIG isn't present before ETMv1.2 */
1521 etm_sys_config_reg
= etm_reg_lookup(etm
, ETM_SYS_CONFIG
);
1522 if (!etm_sys_config_reg
)
1525 etm_get_reg(etm_sys_config_reg
);
1527 switch (buf_get_u32(etm_sys_config_reg
->value
, 0, 3))
1539 LOG_ERROR("Illegal max_port_size");
1542 command_print(cmd_ctx
, "max. port size: %i", max_port_size
);
1544 command_print(cmd_ctx
, "half-rate clocking %ssupported",
1545 (buf_get_u32(etm_sys_config_reg
->value
, 3, 1) == 1) ? "" : "not ");
1546 command_print(cmd_ctx
, "full-rate clocking %ssupported",
1547 (buf_get_u32(etm_sys_config_reg
->value
, 4, 1) == 1) ? "" : "not ");
1548 command_print(cmd_ctx
, "normal trace format %ssupported",
1549 (buf_get_u32(etm_sys_config_reg
->value
, 5, 1) == 1) ? "" : "not ");
1550 command_print(cmd_ctx
, "multiplex trace format %ssupported",
1551 (buf_get_u32(etm_sys_config_reg
->value
, 6, 1) == 1) ? "" : "not ");
1552 command_print(cmd_ctx
, "demultiplex trace format %ssupported",
1553 (buf_get_u32(etm_sys_config_reg
->value
, 7, 1) == 1) ? "" : "not ");
1554 command_print(cmd_ctx
, "FIFO full %ssupported",
1555 (buf_get_u32(etm_sys_config_reg
->value
, 8, 1) == 1) ? "" : "not ");
1560 static int handle_etm_status_command(struct command_context_s
*cmd_ctx
,
1561 char *cmd
, char **args
, int argc
)
1566 trace_status_t trace_status
;
1568 target
= get_current_target(cmd_ctx
);
1569 arm
= target_to_arm(target
);
1572 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1579 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1584 if (etm
->bcd_vers
>= 0x11) {
1587 reg
= etm_reg_lookup(etm
, ETM_STATUS
);
1590 if (etm_get_reg(reg
) == ERROR_OK
) {
1591 unsigned s
= buf_get_u32(reg
->value
, 0, reg
->size
);
1593 command_print(cmd_ctx
, "etm: %s%s%s%s",
1594 /* bit(1) == progbit */
1595 (etm
->bcd_vers
>= 0x12)
1597 ? "disabled" : "enabled")
1599 ((s
& (1 << 3)) && etm
->bcd_vers
>= 0x31)
1600 ? " triggered" : "",
1601 ((s
& (1 << 2)) && etm
->bcd_vers
>= 0x12)
1602 ? " start/stop" : "",
1603 ((s
& (1 << 0)) && etm
->bcd_vers
>= 0x11)
1604 ? " untraced-overflow" : "");
1605 } /* else ignore and try showing trace port status */
1608 /* Trace Port Driver status */
1609 trace_status
= etm
->capture_driver
->status(etm
);
1610 if (trace_status
== TRACE_IDLE
)
1612 command_print(cmd_ctx
, "%s: idle", etm
->capture_driver
->name
);
1616 static char *completed
= " completed";
1617 static char *running
= " is running";
1618 static char *overflowed
= ", overflowed";
1619 static char *triggered
= ", triggered";
1621 command_print(cmd_ctx
, "%s: trace collection%s%s%s",
1622 etm
->capture_driver
->name
,
1623 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1624 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1625 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1627 if (etm
->trace_depth
> 0)
1629 command_print(cmd_ctx
, "%i frames of trace data read",
1630 (int)(etm
->trace_depth
));
1637 static int handle_etm_image_command(struct command_context_s
*cmd_ctx
,
1638 char *cmd
, char **args
, int argc
)
1642 etm_context_t
*etm_ctx
;
1646 command_print(cmd_ctx
, "usage: etm image <file> [base address] [type]");
1650 target
= get_current_target(cmd_ctx
);
1651 arm
= target_to_arm(target
);
1654 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1661 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1667 image_close(etm_ctx
->image
);
1668 free(etm_ctx
->image
);
1669 command_print(cmd_ctx
, "previously loaded image found and closed");
1672 etm_ctx
->image
= malloc(sizeof(image_t
));
1673 etm_ctx
->image
->base_address_set
= 0;
1674 etm_ctx
->image
->start_address_set
= 0;
1676 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1679 etm_ctx
->image
->base_address_set
= 1;
1680 COMMAND_PARSE_NUMBER(int, args
[1], etm_ctx
->image
->base_address
);
1684 etm_ctx
->image
->base_address_set
= 0;
1687 if (image_open(etm_ctx
->image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
1689 free(etm_ctx
->image
);
1690 etm_ctx
->image
= NULL
;
1697 static int handle_etm_dump_command(struct command_context_s
*cmd_ctx
,
1698 char *cmd
, char **args
, int argc
)
1703 etm_context_t
*etm_ctx
;
1708 command_print(cmd_ctx
, "usage: etm dump <file>");
1712 target
= get_current_target(cmd_ctx
);
1713 arm
= target_to_arm(target
);
1716 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1723 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1727 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
)
1729 command_print(cmd_ctx
, "trace capture wasn't enabled, no trace data captured");
1733 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1735 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1736 command_print(cmd_ctx
, "trace capture not completed");
1740 /* read the trace data if it wasn't read already */
1741 if (etm_ctx
->trace_depth
== 0)
1742 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1744 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1749 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1750 fileio_write_u32(&file
, etm_ctx
->portmode
);
1751 fileio_write_u32(&file
, etm_ctx
->tracemode
);
1752 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1754 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1756 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1757 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1758 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1761 fileio_close(&file
);
1766 static int handle_etm_load_command(struct command_context_s
*cmd_ctx
,
1767 char *cmd
, char **args
, int argc
)
1772 etm_context_t
*etm_ctx
;
1777 command_print(cmd_ctx
, "usage: etm load <file>");
1781 target
= get_current_target(cmd_ctx
);
1782 arm
= target_to_arm(target
);
1785 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1792 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1796 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1798 command_print(cmd_ctx
, "trace capture running, stop first");
1802 if (fileio_open(&file
, args
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1809 command_print(cmd_ctx
, "size isn't a multiple of 4, no valid trace data");
1810 fileio_close(&file
);
1814 if (etm_ctx
->trace_depth
> 0)
1816 free(etm_ctx
->trace_data
);
1817 etm_ctx
->trace_data
= NULL
;
1822 fileio_read_u32(&file
, &tmp
); etm_ctx
->capture_status
= tmp
;
1823 fileio_read_u32(&file
, &tmp
); etm_ctx
->portmode
= tmp
;
1824 fileio_read_u32(&file
, &tmp
); etm_ctx
->tracemode
= tmp
;
1825 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1827 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
1828 if (etm_ctx
->trace_data
== NULL
)
1830 command_print(cmd_ctx
, "not enough memory to perform operation");
1831 fileio_close(&file
);
1835 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1837 uint32_t pipestat
, packet
, flags
;
1838 fileio_read_u32(&file
, &pipestat
);
1839 fileio_read_u32(&file
, &packet
);
1840 fileio_read_u32(&file
, &flags
);
1841 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1842 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1843 etm_ctx
->trace_data
[i
].flags
= flags
;
1846 fileio_close(&file
);
1851 static int handle_etm_trigger_percent_command(struct command_context_s
*cmd_ctx
,
1852 char *cmd
, char **args
, int argc
)
1856 etm_context_t
*etm_ctx
;
1858 target
= get_current_target(cmd_ctx
);
1859 arm
= target_to_arm(target
);
1862 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1869 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1876 COMMAND_PARSE_NUMBER(u32
, args
[0], new_value
);
1878 if ((new_value
< 2) || (new_value
> 100))
1880 command_print(cmd_ctx
, "valid settings are 2%% to 100%%");
1884 etm_ctx
->trigger_percent
= new_value
;
1888 command_print(cmd_ctx
, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx
->trigger_percent
)));
1893 static int handle_etm_start_command(struct command_context_s
*cmd_ctx
,
1894 char *cmd
, char **args
, int argc
)
1898 etm_context_t
*etm_ctx
;
1899 reg_t
*etm_ctrl_reg
;
1901 target
= get_current_target(cmd_ctx
);
1902 arm
= target_to_arm(target
);
1905 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1912 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1916 /* invalidate old tracing data */
1917 etm_ctx
->capture_status
= TRACE_IDLE
;
1918 if (etm_ctx
->trace_depth
> 0)
1920 free(etm_ctx
->trace_data
);
1921 etm_ctx
->trace_data
= NULL
;
1923 etm_ctx
->trace_depth
= 0;
1925 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1929 etm_get_reg(etm_ctrl_reg
);
1931 /* Clear programming bit (10), set port selection bit (11) */
1932 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1934 etm_store_reg(etm_ctrl_reg
);
1935 jtag_execute_queue();
1937 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1942 static int handle_etm_stop_command(struct command_context_s
*cmd_ctx
,
1943 char *cmd
, char **args
, int argc
)
1947 etm_context_t
*etm_ctx
;
1948 reg_t
*etm_ctrl_reg
;
1950 target
= get_current_target(cmd_ctx
);
1951 arm
= target_to_arm(target
);
1954 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
1961 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1965 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1969 etm_get_reg(etm_ctrl_reg
);
1971 /* Set programming bit (10), clear port selection bit (11) */
1972 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
1974 etm_store_reg(etm_ctrl_reg
);
1975 jtag_execute_queue();
1977 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
1982 static int handle_etm_analyze_command(struct command_context_s
*cmd_ctx
,
1983 char *cmd
, char **args
, int argc
)
1987 etm_context_t
*etm_ctx
;
1990 target
= get_current_target(cmd_ctx
);
1991 arm
= target_to_arm(target
);
1994 command_print(cmd_ctx
, "ETM: current target isn't an ARM");
2001 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
2005 if ((retval
= etmv1_analyze_trace(etm_ctx
, cmd_ctx
)) != ERROR_OK
)
2009 case ERROR_ETM_ANALYSIS_FAILED
:
2010 command_print(cmd_ctx
, "further analysis failed (corrupted trace data or just end of data");
2012 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE
:
2013 command_print(cmd_ctx
, "no instruction for current address available, analysis aborted");
2015 case ERROR_TRACE_IMAGE_UNAVAILABLE
:
2016 command_print(cmd_ctx
, "no image available for trace analysis");
2019 command_print(cmd_ctx
, "unknown error: %i", retval
);
2026 int etm_register_commands(struct command_context_s
*cmd_ctx
)
2028 etm_cmd
= register_command(cmd_ctx
, NULL
, "etm", NULL
, COMMAND_ANY
, "Embedded Trace Macrocell");
2030 register_command(cmd_ctx
, etm_cmd
, "config", handle_etm_config_command
,
2031 COMMAND_CONFIG
, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2036 static int etm_register_user_commands(struct command_context_s
*cmd_ctx
)
2038 register_command(cmd_ctx
, etm_cmd
, "tracemode", handle_etm_tracemode_command
,
2039 COMMAND_EXEC
, "configure/display trace mode: "
2040 "<none | data | address | all> "
2041 "<context_id_bits> <cycle_accurate> <branch_output>");
2043 register_command(cmd_ctx
, etm_cmd
, "info", handle_etm_info_command
,
2044 COMMAND_EXEC
, "display info about the current target's ETM");
2046 register_command(cmd_ctx
, etm_cmd
, "trigger_percent", handle_etm_trigger_percent_command
,
2047 COMMAND_EXEC
, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2048 register_command(cmd_ctx
, etm_cmd
, "status", handle_etm_status_command
,
2049 COMMAND_EXEC
, "display current target's ETM status");
2050 register_command(cmd_ctx
, etm_cmd
, "start", handle_etm_start_command
,
2051 COMMAND_EXEC
, "start ETM trace collection");
2052 register_command(cmd_ctx
, etm_cmd
, "stop", handle_etm_stop_command
,
2053 COMMAND_EXEC
, "stop ETM trace collection");
2055 register_command(cmd_ctx
, etm_cmd
, "analyze", handle_etm_analyze_command
,
2056 COMMAND_EXEC
, "anaylze collected ETM trace");
2058 register_command(cmd_ctx
, etm_cmd
, "image", handle_etm_image_command
,
2059 COMMAND_EXEC
, "load image from <file> [base address]");
2061 register_command(cmd_ctx
, etm_cmd
, "dump", handle_etm_dump_command
,
2062 COMMAND_EXEC
, "dump captured trace data <file>");
2063 register_command(cmd_ctx
, etm_cmd
, "load", handle_etm_load_command
,
2064 COMMAND_EXEC
, "load trace data for analysis <file>");
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