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arm: error propagation of arm_jtag_set_instr
[openocd.git] / src / target / etm.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm.h"
25 #include "etm.h"
26 #include "etb.h"
27 #include "image.h"
28 #include "arm_disassembler.h"
29 #include "register.h"
30 #include "etm_dummy.h"
31
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
34 #endif
35
36
37 /*
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
39 *
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
43 *
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
48 *
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
52 *
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
57 */
58
59 enum {
60 RO, /* read/only */
61 WO, /* write/only */
62 RW, /* read/write */
63 };
64
65 struct etm_reg_info {
66 uint8_t addr;
67 uint8_t size; /* low-N of 32 bits */
68 uint8_t mode; /* RO, WO, RW */
69 uint8_t bcd_vers; /* 1.0, 2.0, etc */
70 char *name;
71 };
72
73 /*
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
78 */
79
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
84 { ETM_ID, 32, RO, 0x20, "ETM_id", },
85 };
86
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
95
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
101
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
107
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
109
110 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
115 };
116
117 static const struct etm_reg_info etm_fifofull[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
121 };
122
123 static const struct etm_reg_info etm_addr_comp[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
130 ADDR_COMPARATOR(1),
131 ADDR_COMPARATOR(2),
132 ADDR_COMPARATOR(3),
133 ADDR_COMPARATOR(4),
134 ADDR_COMPARATOR(5),
135 ADDR_COMPARATOR(6),
136 ADDR_COMPARATOR(7),
137 ADDR_COMPARATOR(8),
138
139 ADDR_COMPARATOR(9),
140 ADDR_COMPARATOR(10),
141 ADDR_COMPARATOR(11),
142 ADDR_COMPARATOR(12),
143 ADDR_COMPARATOR(13),
144 ADDR_COMPARATOR(14),
145 ADDR_COMPARATOR(15),
146 ADDR_COMPARATOR(16),
147 #undef ADDR_COMPARATOR
148 };
149
150 static const struct etm_reg_info etm_data_comp[] = {
151 /* Data Value Comparators (NOTE: odd addresses are reserved) */
152 #define DATA_COMPARATOR(i) \
153 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
154 "ETM_data_" #i "_comparator_value", }, \
155 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
156 "ETM_data_" #i "_comparator_mask", }
157 DATA_COMPARATOR(1),
158 DATA_COMPARATOR(2),
159 DATA_COMPARATOR(3),
160 DATA_COMPARATOR(4),
161 DATA_COMPARATOR(5),
162 DATA_COMPARATOR(6),
163 DATA_COMPARATOR(7),
164 DATA_COMPARATOR(8),
165 #undef DATA_COMPARATOR
166 };
167
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
178 ETM_COUNTER(1),
179 ETM_COUNTER(2),
180 ETM_COUNTER(3),
181 ETM_COUNTER(4),
182 #undef ETM_COUNTER
183 };
184
185 static const struct etm_reg_info etm_sequencer[] = {
186 #define ETM_SEQ(i) \
187 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
188 "ETM_sequencer_event" #i, }
189 ETM_SEQ(0), /* 1->2 */
190 ETM_SEQ(1), /* 2->1 */
191 ETM_SEQ(2), /* 2->3 */
192 ETM_SEQ(3), /* 3->1 */
193 ETM_SEQ(4), /* 3->2 */
194 ETM_SEQ(5), /* 1->3 */
195 #undef ETM_SEQ
196 /* 0x66 reserved */
197 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
198 };
199
200 static const struct etm_reg_info etm_outputs[] = {
201 #define ETM_OUTPUT(i) \
202 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
203 "ETM_external_output" #i, }
204
205 ETM_OUTPUT(1),
206 ETM_OUTPUT(2),
207 ETM_OUTPUT(3),
208 ETM_OUTPUT(4),
209 #undef ETM_OUTPUT
210 };
211
212 #if 0
213 /* registers from 0x6c..0x7f were added after ETMv1.3 */
214
215 /* Context ID Comparators */
216 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
217 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
218 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
219 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
220 #endif
221
222 static int etm_get_reg(struct reg *reg);
223 static int etm_read_reg_w_check(struct reg *reg,
224 uint8_t* check_value, uint8_t* check_mask);
225 static int etm_register_user_commands(struct command_context *cmd_ctx);
226 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
227 static int etm_write_reg(struct reg *reg, uint32_t value);
228
229 static const struct reg_arch_type etm_scan6_type = {
230 .get = etm_get_reg,
231 .set = etm_set_reg_w_exec,
232 };
233
234 /* Look up register by ID ... most ETM instances only
235 * support a subset of the possible registers.
236 */
237 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
238 {
239 struct reg_cache *cache = etm_ctx->reg_cache;
240 unsigned i;
241
242 for (i = 0; i < cache->num_regs; i++) {
243 struct etm_reg *reg = cache->reg_list[i].arch_info;
244
245 if (reg->reg_info->addr == id)
246 return &cache->reg_list[i];
247 }
248
249 /* caller asking for nonexistent register is a bug! */
250 /* REVISIT say which of the N targets was involved */
251 LOG_ERROR("ETM: register 0x%02x not available", id);
252 return NULL;
253 }
254
255 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
256 struct reg_cache *cache, struct etm_reg *ereg,
257 const struct etm_reg_info *r, unsigned nreg)
258 {
259 struct reg *reg = cache->reg_list;
260
261 reg += cache->num_regs;
262 ereg += cache->num_regs;
263
264 /* add up to "nreg" registers from "r", if supported by this
265 * version of the ETM, to the specified cache.
266 */
267 for (; nreg--; r++) {
268
269 /* this ETM may be too old to have some registers */
270 if (r->bcd_vers > bcd_vers)
271 continue;
272
273 reg->name = r->name;
274 reg->size = r->size;
275 reg->value = &ereg->value;
276 reg->arch_info = ereg;
277 reg->type = &etm_scan6_type;
278 reg++;
279 cache->num_regs++;
280
281 ereg->reg_info = r;
282 ereg->jtag_info = jtag_info;
283 ereg++;
284 }
285 }
286
287 struct reg_cache *etm_build_reg_cache(struct target *target,
288 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
289 {
290 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
291 struct reg *reg_list = NULL;
292 struct etm_reg *arch_info = NULL;
293 unsigned bcd_vers, config;
294
295 /* the actual registers are kept in two arrays */
296 reg_list = calloc(128, sizeof(struct reg));
297 arch_info = calloc(128, sizeof(struct etm_reg));
298
299 /* fill in values for the reg cache */
300 reg_cache->name = "etm registers";
301 reg_cache->next = NULL;
302 reg_cache->reg_list = reg_list;
303 reg_cache->num_regs = 0;
304
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
307 */
308 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
309 etm_core, 1);
310
311 etm_get_reg(reg_list);
312 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
313 config = etm_ctx->config;
314
315 /* figure ETM version then add base registers */
316 if (config & (1 << 31)) {
317 bcd_vers = 0x20;
318 LOG_WARNING("ETMv2+ support is incomplete");
319
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
324 */
325 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
326 etm_core + 1, 1);
327 etm_get_reg(reg_list + 1);
328 etm_ctx->id = buf_get_u32(
329 (void *)&arch_info[1].value, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
331 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
332
333 } else {
334 switch (config >> 28) {
335 case 7:
336 case 5:
337 case 3:
338 bcd_vers = 0x13;
339 break;
340 case 4:
341 case 2:
342 bcd_vers = 0x12;
343 break;
344 case 1:
345 bcd_vers = 0x11;
346 break;
347 case 0:
348 bcd_vers = 0x10;
349 break;
350 default:
351 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
352 goto fail;
353 }
354 }
355 etm_ctx->bcd_vers = bcd_vers;
356 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
357
358 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
359 etm_basic, ARRAY_SIZE(etm_basic));
360
361 /* address and data comparators; counters; outputs */
362 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
363 etm_addr_comp, 4 * (0x0f & (config >> 0)));
364 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
365 etm_data_comp, 2 * (0x0f & (config >> 4)));
366 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
367 etm_counters, 4 * (0x07 & (config >> 13)));
368 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
369 etm_outputs, (0x07 & (config >> 20)));
370
371 /* FIFOFULL presence is optional
372 * REVISIT for ETMv1.2 and later, don't bother adding this
373 * unless ETM_SYS_CONFIG says it's also *supported* ...
374 */
375 if (config & (1 << 23))
376 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
377 etm_fifofull, ARRAY_SIZE(etm_fifofull));
378
379 /* sequencer is optional (for state-dependant triggering) */
380 if (config & (1 << 16))
381 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
382 etm_sequencer, ARRAY_SIZE(etm_sequencer));
383
384 /* REVISIT could realloc and likely save half the memory
385 * in the two chunks we allocated...
386 */
387
388 /* the ETM might have an ETB connected */
389 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
390 {
391 struct etb *etb = etm_ctx->capture_driver_priv;
392
393 if (!etb)
394 {
395 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
396 goto fail;
397 }
398
399 reg_cache->next = etb_build_reg_cache(etb);
400
401 etb->reg_cache = reg_cache->next;
402 }
403
404 etm_ctx->reg_cache = reg_cache;
405 return reg_cache;
406
407 fail:
408 free(reg_cache);
409 free(reg_list);
410 free(arch_info);
411 return NULL;
412 }
413
414 static int etm_read_reg(struct reg *reg)
415 {
416 return etm_read_reg_w_check(reg, NULL, NULL);
417 }
418
419 static int etm_store_reg(struct reg *reg)
420 {
421 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
422 }
423
424 int etm_setup(struct target *target)
425 {
426 int retval;
427 uint32_t etm_ctrl_value;
428 struct arm *arm = target_to_arm(target);
429 struct etm_context *etm_ctx = arm->etm;
430 struct reg *etm_ctrl_reg;
431
432 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
433 if (!etm_ctrl_reg)
434 return ERROR_OK;
435
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg);
438 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
439
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
442
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
445 */
446 etm_ctrl_value = (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
449 & ~ETM_CTRL_DBGRQ
450 & ~ETM_PORT_CLOCK_MASK)
451 | etm_ctx->control;
452
453 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
454 etm_store_reg(etm_ctrl_reg);
455
456 etm_ctx->control = etm_ctrl_value;
457
458 if ((retval = jtag_execute_queue()) != ERROR_OK)
459 return retval;
460
461 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
462 * verify that those width and mode settings are OK ...
463 */
464
465 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
466 {
467 LOG_ERROR("ETM capture driver initialization failed");
468 return retval;
469 }
470 return ERROR_OK;
471 }
472
473 static int etm_get_reg(struct reg *reg)
474 {
475 int retval;
476
477 if ((retval = etm_read_reg(reg)) != ERROR_OK)
478 {
479 LOG_ERROR("BUG: error scheduling etm register read");
480 return retval;
481 }
482
483 if ((retval = jtag_execute_queue()) != ERROR_OK)
484 {
485 LOG_ERROR("register read failed");
486 return retval;
487 }
488
489 return ERROR_OK;
490 }
491
492 static int etm_read_reg_w_check(struct reg *reg,
493 uint8_t* check_value, uint8_t* check_mask)
494 {
495 struct etm_reg *etm_reg = reg->arch_info;
496 const struct etm_reg_info *r = etm_reg->reg_info;
497 uint8_t reg_addr = r->addr & 0x7f;
498 struct scan_field fields[3];
499 int retval;
500
501 if (etm_reg->reg_info->mode == WO) {
502 LOG_ERROR("BUG: can't read write-only register %s", r->name);
503 return ERROR_INVALID_ARGUMENTS;
504 }
505
506 LOG_DEBUG("%s (%u)", r->name, reg_addr);
507
508 arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
509 retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
510 if (retval != ERROR_OK)
511 return retval;
512
513 fields[0].num_bits = 32;
514 fields[0].out_value = reg->value;
515 fields[0].in_value = NULL;
516 fields[0].check_value = NULL;
517 fields[0].check_mask = NULL;
518
519 fields[1].num_bits = 7;
520 uint8_t temp1;
521 fields[1].out_value = &temp1;
522 buf_set_u32(&temp1, 0, 7, reg_addr);
523 fields[1].in_value = NULL;
524 fields[1].check_value = NULL;
525 fields[1].check_mask = NULL;
526
527 fields[2].num_bits = 1;
528 uint8_t temp2;
529 fields[2].out_value = &temp2;
530 buf_set_u32(&temp2, 0, 1, 0);
531 fields[2].in_value = NULL;
532 fields[2].check_value = NULL;
533 fields[2].check_mask = NULL;
534
535 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
536
537 fields[0].in_value = reg->value;
538 fields[0].check_value = check_value;
539 fields[0].check_mask = check_mask;
540
541 jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
542
543 return ERROR_OK;
544 }
545
546 static int etm_set_reg(struct reg *reg, uint32_t value)
547 {
548 int retval;
549
550 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
551 {
552 LOG_ERROR("BUG: error scheduling etm register write");
553 return retval;
554 }
555
556 buf_set_u32(reg->value, 0, reg->size, value);
557 reg->valid = 1;
558 reg->dirty = 0;
559
560 return ERROR_OK;
561 }
562
563 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
564 {
565 int retval;
566
567 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
568
569 if ((retval = jtag_execute_queue()) != ERROR_OK)
570 {
571 LOG_ERROR("register write failed");
572 return retval;
573 }
574 return ERROR_OK;
575 }
576
577 static int etm_write_reg(struct reg *reg, uint32_t value)
578 {
579 struct etm_reg *etm_reg = reg->arch_info;
580 const struct etm_reg_info *r = etm_reg->reg_info;
581 uint8_t reg_addr = r->addr & 0x7f;
582 struct scan_field fields[3];
583 int retval;
584
585 if (etm_reg->reg_info->mode == RO) {
586 LOG_ERROR("BUG: can't write read--only register %s", r->name);
587 return ERROR_INVALID_ARGUMENTS;
588 }
589
590 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
591
592 arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
593 retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
594 if (retval != ERROR_OK)
595 return retval;
596
597 fields[0].num_bits = 32;
598 uint8_t tmp1[4];
599 fields[0].out_value = tmp1;
600 buf_set_u32(tmp1, 0, 32, value);
601 fields[0].in_value = NULL;
602
603 fields[1].num_bits = 7;
604 uint8_t tmp2;
605 fields[1].out_value = &tmp2;
606 buf_set_u32(&tmp2, 0, 7, reg_addr);
607 fields[1].in_value = NULL;
608
609 fields[2].num_bits = 1;
610 uint8_t tmp3;
611 fields[2].out_value = &tmp3;
612 buf_set_u32(&tmp3, 0, 1, 1);
613 fields[2].in_value = NULL;
614
615 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
616
617 return ERROR_OK;
618 }
619
620
621 /* ETM trace analysis functionality */
622
623 static struct etm_capture_driver *etm_capture_drivers[] =
624 {
625 &etb_capture_driver,
626 &etm_dummy_capture_driver,
627 #if BUILD_OOCD_TRACE == 1
628 &oocd_trace_capture_driver,
629 #endif
630 NULL
631 };
632
633 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
634 {
635 int i;
636 int section = -1;
637 size_t size_read;
638 uint32_t opcode;
639 int retval;
640
641 if (!ctx->image)
642 return ERROR_TRACE_IMAGE_UNAVAILABLE;
643
644 /* search for the section the current instruction belongs to */
645 for (i = 0; i < ctx->image->num_sections; i++)
646 {
647 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
648 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
649 {
650 section = i;
651 break;
652 }
653 }
654
655 if (section == -1)
656 {
657 /* current instruction couldn't be found in the image */
658 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
659 }
660
661 if (ctx->core_state == ARM_STATE_ARM)
662 {
663 uint8_t buf[4];
664 if ((retval = image_read_section(ctx->image, section,
665 ctx->current_pc - ctx->image->sections[section].base_address,
666 4, buf, &size_read)) != ERROR_OK)
667 {
668 LOG_ERROR("error while reading instruction: %i", retval);
669 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
670 }
671 opcode = target_buffer_get_u32(ctx->target, buf);
672 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
673 }
674 else if (ctx->core_state == ARM_STATE_THUMB)
675 {
676 uint8_t buf[2];
677 if ((retval = image_read_section(ctx->image, section,
678 ctx->current_pc - ctx->image->sections[section].base_address,
679 2, buf, &size_read)) != ERROR_OK)
680 {
681 LOG_ERROR("error while reading instruction: %i", retval);
682 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
683 }
684 opcode = target_buffer_get_u16(ctx->target, buf);
685 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
686 }
687 else if (ctx->core_state == ARM_STATE_JAZELLE)
688 {
689 LOG_ERROR("BUG: tracing of jazelle code not supported");
690 return ERROR_FAIL;
691 }
692 else
693 {
694 LOG_ERROR("BUG: unknown core state encountered");
695 return ERROR_FAIL;
696 }
697
698 return ERROR_OK;
699 }
700
701 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
702 {
703 while (ctx->data_index < ctx->trace_depth)
704 {
705 /* if the caller specified an address packet offset, skip until the
706 * we reach the n-th cycle marked with tracesync */
707 if (apo > 0)
708 {
709 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
710 apo--;
711
712 if (apo > 0)
713 {
714 ctx->data_index++;
715 ctx->data_half = 0;
716 }
717 continue;
718 }
719
720 /* no tracedata output during a TD cycle
721 * or in a trigger cycle */
722 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
723 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
724 {
725 ctx->data_index++;
726 ctx->data_half = 0;
727 continue;
728 }
729
730 /* FIXME there are more port widths than these... */
731 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
732 {
733 if (ctx->data_half == 0)
734 {
735 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
736 ctx->data_half = 1;
737 }
738 else
739 {
740 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
741 ctx->data_half = 0;
742 ctx->data_index++;
743 }
744 }
745 else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
746 {
747 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
748 ctx->data_index++;
749 }
750 else
751 {
752 /* on a 4-bit port, a packet will be output during two consecutive cycles */
753 if (ctx->data_index > (ctx->trace_depth - 2))
754 return -1;
755
756 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
757 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
758 ctx->data_index += 2;
759 }
760
761 return 0;
762 }
763
764 return -1;
765 }
766
767 static int etmv1_branch_address(struct etm_context *ctx)
768 {
769 int retval;
770 uint8_t packet;
771 int shift = 0;
772 int apo;
773 uint32_t i;
774
775 /* quit analysis if less than two cycles are left in the trace
776 * because we can't extract the APO */
777 if (ctx->data_index > (ctx->trace_depth - 2))
778 return -1;
779
780 /* a BE could be output during an APO cycle, skip the current
781 * and continue with the new one */
782 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
783 return 1;
784 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
785 return 2;
786
787 /* address packet offset encoded in the next two cycles' pipestat bits */
788 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
789 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
790
791 /* count number of tracesync cycles between current pipe_index and data_index
792 * i.e. the number of tracesyncs that data_index already passed by
793 * to subtract them from the APO */
794 for (i = ctx->pipe_index; i < ctx->data_index; i++)
795 {
796 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
797 apo--;
798 }
799
800 /* extract up to four 7-bit packets */
801 do {
802 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
803 return -1;
804 ctx->last_branch &= ~(0x7f << shift);
805 ctx->last_branch |= (packet & 0x7f) << shift;
806 shift += 7;
807 } while ((packet & 0x80) && (shift < 28));
808
809 /* one last packet holding 4 bits of the address, plus the branch reason code */
810 if ((shift == 28) && (packet & 0x80))
811 {
812 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
813 return -1;
814 ctx->last_branch &= 0x0fffffff;
815 ctx->last_branch |= (packet & 0x0f) << 28;
816 ctx->last_branch_reason = (packet & 0x70) >> 4;
817 shift += 4;
818 }
819 else
820 {
821 ctx->last_branch_reason = 0;
822 }
823
824 if (shift == 32)
825 {
826 ctx->pc_ok = 1;
827 }
828
829 /* if a full address was output, we might have branched into Jazelle state */
830 if ((shift == 32) && (packet & 0x80))
831 {
832 ctx->core_state = ARM_STATE_JAZELLE;
833 }
834 else
835 {
836 /* if we didn't branch into Jazelle state, the current processor state is
837 * encoded in bit 0 of the branch target address */
838 if (ctx->last_branch & 0x1)
839 {
840 ctx->core_state = ARM_STATE_THUMB;
841 ctx->last_branch &= ~0x1;
842 }
843 else
844 {
845 ctx->core_state = ARM_STATE_ARM;
846 ctx->last_branch &= ~0x3;
847 }
848 }
849
850 return 0;
851 }
852
853 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
854 {
855 int j;
856 uint8_t buf[4];
857 int retval;
858
859 for (j = 0; j < size; j++)
860 {
861 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
862 return -1;
863 }
864
865 if (size == 8)
866 {
867 LOG_ERROR("TODO: add support for 64-bit values");
868 return -1;
869 }
870 else if (size == 4)
871 *data = target_buffer_get_u32(ctx->target, buf);
872 else if (size == 2)
873 *data = target_buffer_get_u16(ctx->target, buf);
874 else if (size == 1)
875 *data = buf[0];
876 else
877 return -1;
878
879 return 0;
880 }
881
882 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
883 {
884 int retval;
885 struct arm_instruction instruction;
886
887 /* read the trace data if it wasn't read already */
888 if (ctx->trace_depth == 0)
889 ctx->capture_driver->read_trace(ctx);
890
891 if (ctx->trace_depth == 0) {
892 command_print(cmd_ctx, "Trace is empty.");
893 return ERROR_OK;
894 }
895
896 /* start at the beginning of the captured trace */
897 ctx->pipe_index = 0;
898 ctx->data_index = 0;
899 ctx->data_half = 0;
900
901 /* neither the PC nor the data pointer are valid */
902 ctx->pc_ok = 0;
903 ctx->ptr_ok = 0;
904
905 while (ctx->pipe_index < ctx->trace_depth)
906 {
907 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
908 uint32_t next_pc = ctx->current_pc;
909 uint32_t old_data_index = ctx->data_index;
910 uint32_t old_data_half = ctx->data_half;
911 uint32_t old_index = ctx->pipe_index;
912 uint32_t last_instruction = ctx->last_instruction;
913 uint32_t cycles = 0;
914 int current_pc_ok = ctx->pc_ok;
915
916 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
917 {
918 command_print(cmd_ctx, "--- trigger ---");
919 }
920
921 /* instructions execute in IE/D or BE/D cycles */
922 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
923 ctx->last_instruction = ctx->pipe_index;
924
925 /* if we don't have a valid pc skip until we reach an indirect branch */
926 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
927 {
928 ctx->pipe_index++;
929 continue;
930 }
931
932 /* any indirect branch could have interrupted instruction flow
933 * - the branch reason code could indicate a trace discontinuity
934 * - a branch to the exception vectors indicates an exception
935 */
936 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
937 {
938 /* backup current data index, to be able to consume the branch address
939 * before examining data address and values
940 */
941 old_data_index = ctx->data_index;
942 old_data_half = ctx->data_half;
943
944 ctx->last_instruction = ctx->pipe_index;
945
946 if ((retval = etmv1_branch_address(ctx)) != 0)
947 {
948 /* negative return value from etmv1_branch_address means we ran out of packets,
949 * quit analysing the trace */
950 if (retval < 0)
951 break;
952
953 /* a positive return values means the current branch was abandoned,
954 * and a new branch was encountered in cycle ctx->pipe_index + retval;
955 */
956 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
957 ctx->pipe_index += retval;
958 continue;
959 }
960
961 /* skip over APO cycles */
962 ctx->pipe_index += 2;
963
964 switch (ctx->last_branch_reason)
965 {
966 case 0x0: /* normal PC change */
967 next_pc = ctx->last_branch;
968 break;
969 case 0x1: /* tracing enabled */
970 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
971 ctx->current_pc = ctx->last_branch;
972 ctx->pipe_index++;
973 continue;
974 break;
975 case 0x2: /* trace restarted after FIFO overflow */
976 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
977 ctx->current_pc = ctx->last_branch;
978 ctx->pipe_index++;
979 continue;
980 break;
981 case 0x3: /* exit from debug state */
982 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
983 ctx->current_pc = ctx->last_branch;
984 ctx->pipe_index++;
985 continue;
986 break;
987 case 0x4: /* periodic synchronization point */
988 next_pc = ctx->last_branch;
989 /* if we had no valid PC prior to this synchronization point,
990 * we have to move on with the next trace cycle
991 */
992 if (!current_pc_ok)
993 {
994 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
995 ctx->current_pc = next_pc;
996 ctx->pipe_index++;
997 continue;
998 }
999 break;
1000 default: /* reserved */
1001 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
1002 return ERROR_FAIL;
1003 }
1004
1005 /* if we got here the branch was a normal PC change
1006 * (or a periodic synchronization point, which means the same for that matter)
1007 * if we didn't accquire a complete PC continue with the next cycle
1008 */
1009 if (!ctx->pc_ok)
1010 continue;
1011
1012 /* indirect branch to the exception vector means an exception occured */
1013 if ((ctx->last_branch <= 0x20)
1014 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1015 {
1016 if ((ctx->last_branch & 0xff) == 0x10)
1017 {
1018 command_print(cmd_ctx, "data abort");
1019 }
1020 else
1021 {
1022 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1023 ctx->current_pc = ctx->last_branch;
1024 ctx->pipe_index++;
1025 continue;
1026 }
1027 }
1028 }
1029
1030 /* an instruction was executed (or not, depending on the condition flags)
1031 * retrieve it from the image for displaying */
1032 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1033 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1034 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1035 {
1036 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1037 {
1038 /* can't continue tracing with no image available */
1039 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1040 {
1041 return retval;
1042 }
1043 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1044 {
1045 /* TODO: handle incomplete images
1046 * for now we just quit the analsysis*/
1047 return retval;
1048 }
1049 }
1050
1051 cycles = old_index - last_instruction;
1052 }
1053
1054 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1055 {
1056 uint32_t new_data_index = ctx->data_index;
1057 uint32_t new_data_half = ctx->data_half;
1058
1059 /* in case of a branch with data, the branch target address was consumed before
1060 * we temporarily go back to the saved data index */
1061 if (pipestat == STAT_BD)
1062 {
1063 ctx->data_index = old_data_index;
1064 ctx->data_half = old_data_half;
1065 }
1066
1067 if (ctx->control & ETM_CTRL_TRACE_ADDR)
1068 {
1069 uint8_t packet;
1070 int shift = 0;
1071
1072 do {
1073 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1074 return ERROR_ETM_ANALYSIS_FAILED;
1075 ctx->last_ptr &= ~(0x7f << shift);
1076 ctx->last_ptr |= (packet & 0x7f) << shift;
1077 shift += 7;
1078 } while ((packet & 0x80) && (shift < 32));
1079
1080 if (shift >= 32)
1081 ctx->ptr_ok = 1;
1082
1083 if (ctx->ptr_ok)
1084 {
1085 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1086 }
1087 }
1088
1089 if (ctx->control & ETM_CTRL_TRACE_DATA)
1090 {
1091 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1092 {
1093 int i;
1094 for (i = 0; i < 16; i++)
1095 {
1096 if (instruction.info.load_store_multiple.register_list & (1 << i))
1097 {
1098 uint32_t data;
1099 if (etmv1_data(ctx, 4, &data) != 0)
1100 return ERROR_ETM_ANALYSIS_FAILED;
1101 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1102 }
1103 }
1104 }
1105 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1106 {
1107 uint32_t data;
1108 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1109 return ERROR_ETM_ANALYSIS_FAILED;
1110 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1111 }
1112 }
1113
1114 /* restore data index after consuming BD address and data */
1115 if (pipestat == STAT_BD)
1116 {
1117 ctx->data_index = new_data_index;
1118 ctx->data_half = new_data_half;
1119 }
1120 }
1121
1122 /* adjust PC */
1123 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1124 {
1125 if (((instruction.type == ARM_B) ||
1126 (instruction.type == ARM_BL) ||
1127 (instruction.type == ARM_BLX)) &&
1128 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1129 {
1130 next_pc = instruction.info.b_bl_bx_blx.target_address;
1131 }
1132 else
1133 {
1134 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1135 }
1136 }
1137 else if (pipestat == STAT_IN)
1138 {
1139 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1140 }
1141
1142 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1143 {
1144 char cycles_text[32] = "";
1145
1146 /* if the trace was captured with cycle accurate tracing enabled,
1147 * output the number of cycles since the last executed instruction
1148 */
1149 if (ctx->control & ETM_CTRL_CYCLE_ACCURATE)
1150 {
1151 snprintf(cycles_text, 32, " (%i %s)",
1152 (int)cycles,
1153 (cycles == 1) ? "cycle" : "cycles");
1154 }
1155
1156 command_print(cmd_ctx, "%s%s%s",
1157 instruction.text,
1158 (pipestat == STAT_IN) ? " (not executed)" : "",
1159 cycles_text);
1160
1161 ctx->current_pc = next_pc;
1162
1163 /* packets for an instruction don't start on or before the preceding
1164 * functional pipestat (i.e. other than WT or TD)
1165 */
1166 if (ctx->data_index <= ctx->pipe_index)
1167 {
1168 ctx->data_index = ctx->pipe_index + 1;
1169 ctx->data_half = 0;
1170 }
1171 }
1172
1173 ctx->pipe_index += 1;
1174 }
1175
1176 return ERROR_OK;
1177 }
1178
1179 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1180 uint32_t *mode)
1181 {
1182 uint32_t tracemode;
1183
1184 /* what parts of data access are traced? */
1185 if (strcmp(CMD_ARGV[0], "none") == 0)
1186 tracemode = 0;
1187 else if (strcmp(CMD_ARGV[0], "data") == 0)
1188 tracemode = ETM_CTRL_TRACE_DATA;
1189 else if (strcmp(CMD_ARGV[0], "address") == 0)
1190 tracemode = ETM_CTRL_TRACE_ADDR;
1191 else if (strcmp(CMD_ARGV[0], "all") == 0)
1192 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1193 else
1194 {
1195 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1196 return ERROR_INVALID_ARGUMENTS;
1197 }
1198
1199 uint8_t context_id;
1200 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1201 switch (context_id)
1202 {
1203 case 0:
1204 tracemode |= ETM_CTRL_CONTEXTID_NONE;
1205 break;
1206 case 8:
1207 tracemode |= ETM_CTRL_CONTEXTID_8;
1208 break;
1209 case 16:
1210 tracemode |= ETM_CTRL_CONTEXTID_16;
1211 break;
1212 case 32:
1213 tracemode |= ETM_CTRL_CONTEXTID_32;
1214 break;
1215 default:
1216 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1217 return ERROR_INVALID_ARGUMENTS;
1218 }
1219
1220 bool etmv1_cycle_accurate;
1221 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1222 if (etmv1_cycle_accurate)
1223 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1224
1225 bool etmv1_branch_output;
1226 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1227 if (etmv1_branch_output)
1228 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1229
1230 /* IGNORED:
1231 * - CPRT tracing (coprocessor register transfers)
1232 * - debug request (causes debug entry on trigger)
1233 * - stall on FIFOFULL (preventing tracedata lossage)
1234 */
1235 *mode = tracemode;
1236
1237 return ERROR_OK;
1238 }
1239
1240 COMMAND_HANDLER(handle_etm_tracemode_command)
1241 {
1242 struct target *target = get_current_target(CMD_CTX);
1243 struct arm *arm = target_to_arm(target);
1244 struct etm_context *etm;
1245
1246 if (!is_arm(arm)) {
1247 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1248 return ERROR_FAIL;
1249 }
1250
1251 etm = arm->etm;
1252 if (!etm) {
1253 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1254 return ERROR_FAIL;
1255 }
1256
1257 uint32_t tracemode = etm->control;
1258
1259 switch (CMD_ARGC)
1260 {
1261 case 0:
1262 break;
1263 case 4:
1264 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1265 &tracemode);
1266 break;
1267 default:
1268 command_print(CMD_CTX, "usage: tracemode "
1269 "('none'|'data'|'address'|'all') "
1270 "context_id_bits "
1271 "('enable'|'disable') "
1272 "('enable'|'disable')"
1273 );
1274 return ERROR_FAIL;
1275 }
1276
1277 /**
1278 * todo: fail if parameters were invalid for this hardware,
1279 * or couldn't be written; display actual hardware state...
1280 */
1281
1282 command_print(CMD_CTX, "current tracemode configuration:");
1283
1284 switch (tracemode & ETM_CTRL_TRACE_MASK)
1285 {
1286 default:
1287 command_print(CMD_CTX, "data tracing: none");
1288 break;
1289 case ETM_CTRL_TRACE_DATA:
1290 command_print(CMD_CTX, "data tracing: data only");
1291 break;
1292 case ETM_CTRL_TRACE_ADDR:
1293 command_print(CMD_CTX, "data tracing: address only");
1294 break;
1295 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1296 command_print(CMD_CTX, "data tracing: address and data");
1297 break;
1298 }
1299
1300 switch (tracemode & ETM_CTRL_CONTEXTID_MASK)
1301 {
1302 case ETM_CTRL_CONTEXTID_NONE:
1303 command_print(CMD_CTX, "contextid tracing: none");
1304 break;
1305 case ETM_CTRL_CONTEXTID_8:
1306 command_print(CMD_CTX, "contextid tracing: 8 bit");
1307 break;
1308 case ETM_CTRL_CONTEXTID_16:
1309 command_print(CMD_CTX, "contextid tracing: 16 bit");
1310 break;
1311 case ETM_CTRL_CONTEXTID_32:
1312 command_print(CMD_CTX, "contextid tracing: 32 bit");
1313 break;
1314 }
1315
1316 if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1317 {
1318 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1319 }
1320 else
1321 {
1322 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1323 }
1324
1325 if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1326 {
1327 command_print(CMD_CTX, "full branch address output enabled");
1328 }
1329 else
1330 {
1331 command_print(CMD_CTX, "full branch address output disabled");
1332 }
1333
1334 #define TRACEMODE_MASK ( \
1335 ETM_CTRL_CONTEXTID_MASK \
1336 | ETM_CTRL_BRANCH_OUTPUT \
1337 | ETM_CTRL_CYCLE_ACCURATE \
1338 | ETM_CTRL_TRACE_MASK \
1339 )
1340
1341 /* only update ETM_CTRL register if tracemode changed */
1342 if ((etm->control & TRACEMODE_MASK) != tracemode)
1343 {
1344 struct reg *etm_ctrl_reg;
1345
1346 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1347 if (!etm_ctrl_reg)
1348 return ERROR_FAIL;
1349
1350 etm->control &= ~TRACEMODE_MASK;
1351 etm->control |= tracemode & TRACEMODE_MASK;
1352
1353 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1354 etm_store_reg(etm_ctrl_reg);
1355
1356 /* invalidate old trace data */
1357 etm->capture_status = TRACE_IDLE;
1358 if (etm->trace_depth > 0)
1359 {
1360 free(etm->trace_data);
1361 etm->trace_data = NULL;
1362 }
1363 etm->trace_depth = 0;
1364 }
1365
1366 #undef TRACEMODE_MASK
1367
1368 return ERROR_OK;
1369 }
1370
1371 COMMAND_HANDLER(handle_etm_config_command)
1372 {
1373 struct target *target;
1374 struct arm *arm;
1375 uint32_t portmode = 0x0;
1376 struct etm_context *etm_ctx;
1377 int i;
1378
1379 if (CMD_ARGC != 5)
1380 return ERROR_COMMAND_SYNTAX_ERROR;
1381
1382 target = get_target(CMD_ARGV[0]);
1383 if (!target)
1384 {
1385 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1386 return ERROR_FAIL;
1387 }
1388
1389 arm = target_to_arm(target);
1390 if (!is_arm(arm)) {
1391 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1392 target_name(target),
1393 target_type_name(target));
1394 return ERROR_FAIL;
1395 }
1396
1397 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1398 * version we'll be using!! -- so we can't know how to validate
1399 * params yet. "etm config" should likely be *AFTER* hookup...
1400 *
1401 * - Many more widths might be supported ... and we can easily
1402 * check whether our setting "took".
1403 *
1404 * - The "clock" and "mode" bits are interpreted differently.
1405 * See ARM IHI 0014O table 2-17 for the old behavior, and
1406 * table 2-18 for the new. With ETB it's best to specify
1407 * "normal full" ...
1408 */
1409 uint8_t port_width;
1410 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1411 switch (port_width)
1412 {
1413 /* before ETMv3.0 */
1414 case 4:
1415 portmode |= ETM_PORT_4BIT;
1416 break;
1417 case 8:
1418 portmode |= ETM_PORT_8BIT;
1419 break;
1420 case 16:
1421 portmode |= ETM_PORT_16BIT;
1422 break;
1423 /* ETMv3.0 and later*/
1424 case 24:
1425 portmode |= ETM_PORT_24BIT;
1426 break;
1427 case 32:
1428 portmode |= ETM_PORT_32BIT;
1429 break;
1430 case 48:
1431 portmode |= ETM_PORT_48BIT;
1432 break;
1433 case 64:
1434 portmode |= ETM_PORT_64BIT;
1435 break;
1436 case 1:
1437 portmode |= ETM_PORT_1BIT;
1438 break;
1439 case 2:
1440 portmode |= ETM_PORT_2BIT;
1441 break;
1442 default:
1443 command_print(CMD_CTX,
1444 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1445 return ERROR_FAIL;
1446 }
1447
1448 if (strcmp("normal", CMD_ARGV[2]) == 0)
1449 {
1450 portmode |= ETM_PORT_NORMAL;
1451 }
1452 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1453 {
1454 portmode |= ETM_PORT_MUXED;
1455 }
1456 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1457 {
1458 portmode |= ETM_PORT_DEMUXED;
1459 }
1460 else
1461 {
1462 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1463 return ERROR_FAIL;
1464 }
1465
1466 if (strcmp("half", CMD_ARGV[3]) == 0)
1467 {
1468 portmode |= ETM_PORT_HALF_CLOCK;
1469 }
1470 else if (strcmp("full", CMD_ARGV[3]) == 0)
1471 {
1472 portmode |= ETM_PORT_FULL_CLOCK;
1473 }
1474 else
1475 {
1476 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1477 return ERROR_FAIL;
1478 }
1479
1480 etm_ctx = calloc(1, sizeof(struct etm_context));
1481 if (!etm_ctx) {
1482 LOG_DEBUG("out of memory");
1483 return ERROR_FAIL;
1484 }
1485
1486 for (i = 0; etm_capture_drivers[i]; i++)
1487 {
1488 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1489 {
1490 int retval = register_commands(CMD_CTX, NULL,
1491 etm_capture_drivers[i]->commands);
1492 if (ERROR_OK != retval)
1493 {
1494 free(etm_ctx);
1495 return retval;
1496 }
1497
1498 etm_ctx->capture_driver = etm_capture_drivers[i];
1499
1500 break;
1501 }
1502 }
1503
1504 if (!etm_capture_drivers[i])
1505 {
1506 /* no supported capture driver found, don't register an ETM */
1507 free(etm_ctx);
1508 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1509 return ERROR_FAIL;
1510 }
1511
1512 etm_ctx->target = target;
1513 etm_ctx->trace_data = NULL;
1514 etm_ctx->control = portmode;
1515 etm_ctx->core_state = ARM_STATE_ARM;
1516
1517 arm->etm = etm_ctx;
1518
1519 return etm_register_user_commands(CMD_CTX);
1520 }
1521
1522 COMMAND_HANDLER(handle_etm_info_command)
1523 {
1524 struct target *target;
1525 struct arm *arm;
1526 struct etm_context *etm;
1527 struct reg *etm_sys_config_reg;
1528 int max_port_size;
1529 uint32_t config;
1530
1531 target = get_current_target(CMD_CTX);
1532 arm = target_to_arm(target);
1533 if (!is_arm(arm))
1534 {
1535 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1536 return ERROR_FAIL;
1537 }
1538
1539 etm = arm->etm;
1540 if (!etm)
1541 {
1542 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1543 return ERROR_FAIL;
1544 }
1545
1546 command_print(CMD_CTX, "ETM v%d.%d",
1547 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1548 command_print(CMD_CTX, "pairs of address comparators: %i",
1549 (int) (etm->config >> 0) & 0x0f);
1550 command_print(CMD_CTX, "data comparators: %i",
1551 (int) (etm->config >> 4) & 0x0f);
1552 command_print(CMD_CTX, "memory map decoders: %i",
1553 (int) (etm->config >> 8) & 0x1f);
1554 command_print(CMD_CTX, "number of counters: %i",
1555 (int) (etm->config >> 13) & 0x07);
1556 command_print(CMD_CTX, "sequencer %spresent",
1557 (int) (etm->config & (1 << 16)) ? "" : "not ");
1558 command_print(CMD_CTX, "number of ext. inputs: %i",
1559 (int) (etm->config >> 17) & 0x07);
1560 command_print(CMD_CTX, "number of ext. outputs: %i",
1561 (int) (etm->config >> 20) & 0x07);
1562 command_print(CMD_CTX, "FIFO full %spresent",
1563 (int) (etm->config & (1 << 23)) ? "" : "not ");
1564 if (etm->bcd_vers < 0x20)
1565 command_print(CMD_CTX, "protocol version: %i",
1566 (int) (etm->config >> 28) & 0x07);
1567 else {
1568 command_print(CMD_CTX,
1569 "coprocessor and memory access %ssupported",
1570 (etm->config & (1 << 26)) ? "" : "not ");
1571 command_print(CMD_CTX, "trace start/stop %spresent",
1572 (etm->config & (1 << 26)) ? "" : "not ");
1573 command_print(CMD_CTX, "number of context comparators: %i",
1574 (int) (etm->config >> 24) & 0x03);
1575 }
1576
1577 /* SYS_CONFIG isn't present before ETMv1.2 */
1578 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1579 if (!etm_sys_config_reg)
1580 return ERROR_OK;
1581
1582 etm_get_reg(etm_sys_config_reg);
1583 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1584
1585 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1586
1587 max_port_size = config & 0x7;
1588 if (etm->bcd_vers >= 0x30)
1589 max_port_size |= (config >> 6) & 0x08;
1590 switch (max_port_size)
1591 {
1592 /* before ETMv3.0 */
1593 case 0:
1594 max_port_size = 4;
1595 break;
1596 case 1:
1597 max_port_size = 8;
1598 break;
1599 case 2:
1600 max_port_size = 16;
1601 break;
1602 /* ETMv3.0 and later*/
1603 case 3:
1604 max_port_size = 24;
1605 break;
1606 case 4:
1607 max_port_size = 32;
1608 break;
1609 case 5:
1610 max_port_size = 48;
1611 break;
1612 case 6:
1613 max_port_size = 64;
1614 break;
1615 case 8:
1616 max_port_size = 1;
1617 break;
1618 case 9:
1619 max_port_size = 2;
1620 break;
1621 default:
1622 LOG_ERROR("Illegal max_port_size");
1623 return ERROR_FAIL;
1624 }
1625 command_print(CMD_CTX, "max. port size: %i", max_port_size);
1626
1627 if (etm->bcd_vers < 0x30) {
1628 command_print(CMD_CTX, "half-rate clocking %ssupported",
1629 (config & (1 << 3)) ? "" : "not ");
1630 command_print(CMD_CTX, "full-rate clocking %ssupported",
1631 (config & (1 << 4)) ? "" : "not ");
1632 command_print(CMD_CTX, "normal trace format %ssupported",
1633 (config & (1 << 5)) ? "" : "not ");
1634 command_print(CMD_CTX, "multiplex trace format %ssupported",
1635 (config & (1 << 6)) ? "" : "not ");
1636 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1637 (config & (1 << 7)) ? "" : "not ");
1638 } else {
1639 /* REVISIT show which size and format are selected ... */
1640 command_print(CMD_CTX, "current port size %ssupported",
1641 (config & (1 << 10)) ? "" : "not ");
1642 command_print(CMD_CTX, "current trace format %ssupported",
1643 (config & (1 << 11)) ? "" : "not ");
1644 }
1645 if (etm->bcd_vers >= 0x21)
1646 command_print(CMD_CTX, "fetch comparisons %ssupported",
1647 (config & (1 << 17)) ? "not " : "");
1648 command_print(CMD_CTX, "FIFO full %ssupported",
1649 (config & (1 << 8)) ? "" : "not ");
1650
1651 return ERROR_OK;
1652 }
1653
1654 COMMAND_HANDLER(handle_etm_status_command)
1655 {
1656 struct target *target;
1657 struct arm *arm;
1658 struct etm_context *etm;
1659 trace_status_t trace_status;
1660
1661 target = get_current_target(CMD_CTX);
1662 arm = target_to_arm(target);
1663 if (!is_arm(arm))
1664 {
1665 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1666 return ERROR_FAIL;
1667 }
1668
1669 etm = arm->etm;
1670 if (!etm)
1671 {
1672 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1673 return ERROR_FAIL;
1674 }
1675
1676 /* ETM status */
1677 if (etm->bcd_vers >= 0x11) {
1678 struct reg *reg;
1679
1680 reg = etm_reg_lookup(etm, ETM_STATUS);
1681 if (!reg)
1682 return ERROR_FAIL;
1683 if (etm_get_reg(reg) == ERROR_OK) {
1684 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1685
1686 command_print(CMD_CTX, "etm: %s%s%s%s",
1687 /* bit(1) == progbit */
1688 (etm->bcd_vers >= 0x12)
1689 ? ((s & (1 << 1))
1690 ? "disabled" : "enabled")
1691 : "?",
1692 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1693 ? " triggered" : "",
1694 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1695 ? " start/stop" : "",
1696 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1697 ? " untraced-overflow" : "");
1698 } /* else ignore and try showing trace port status */
1699 }
1700
1701 /* Trace Port Driver status */
1702 trace_status = etm->capture_driver->status(etm);
1703 if (trace_status == TRACE_IDLE)
1704 {
1705 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1706 }
1707 else
1708 {
1709 static char *completed = " completed";
1710 static char *running = " is running";
1711 static char *overflowed = ", overflowed";
1712 static char *triggered = ", triggered";
1713
1714 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1715 etm->capture_driver->name,
1716 (trace_status & TRACE_RUNNING) ? running : completed,
1717 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1718 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1719
1720 if (etm->trace_depth > 0)
1721 {
1722 command_print(CMD_CTX, "%i frames of trace data read",
1723 (int)(etm->trace_depth));
1724 }
1725 }
1726
1727 return ERROR_OK;
1728 }
1729
1730 COMMAND_HANDLER(handle_etm_image_command)
1731 {
1732 struct target *target;
1733 struct arm *arm;
1734 struct etm_context *etm_ctx;
1735
1736 if (CMD_ARGC < 1)
1737 {
1738 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1739 return ERROR_FAIL;
1740 }
1741
1742 target = get_current_target(CMD_CTX);
1743 arm = target_to_arm(target);
1744 if (!is_arm(arm))
1745 {
1746 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1747 return ERROR_FAIL;
1748 }
1749
1750 etm_ctx = arm->etm;
1751 if (!etm_ctx)
1752 {
1753 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1754 return ERROR_FAIL;
1755 }
1756
1757 if (etm_ctx->image)
1758 {
1759 image_close(etm_ctx->image);
1760 free(etm_ctx->image);
1761 command_print(CMD_CTX, "previously loaded image found and closed");
1762 }
1763
1764 etm_ctx->image = malloc(sizeof(struct image));
1765 etm_ctx->image->base_address_set = 0;
1766 etm_ctx->image->start_address_set = 0;
1767
1768 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1769 if (CMD_ARGC >= 2)
1770 {
1771 etm_ctx->image->base_address_set = 1;
1772 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address);
1773 }
1774 else
1775 {
1776 etm_ctx->image->base_address_set = 0;
1777 }
1778
1779 if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1780 {
1781 free(etm_ctx->image);
1782 etm_ctx->image = NULL;
1783 return ERROR_FAIL;
1784 }
1785
1786 return ERROR_OK;
1787 }
1788
1789 COMMAND_HANDLER(handle_etm_dump_command)
1790 {
1791 struct fileio file;
1792 struct target *target;
1793 struct arm *arm;
1794 struct etm_context *etm_ctx;
1795 uint32_t i;
1796
1797 if (CMD_ARGC != 1)
1798 {
1799 command_print(CMD_CTX, "usage: etm dump <file>");
1800 return ERROR_FAIL;
1801 }
1802
1803 target = get_current_target(CMD_CTX);
1804 arm = target_to_arm(target);
1805 if (!is_arm(arm))
1806 {
1807 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1808 return ERROR_FAIL;
1809 }
1810
1811 etm_ctx = arm->etm;
1812 if (!etm_ctx)
1813 {
1814 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1815 return ERROR_FAIL;
1816 }
1817
1818 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1819 {
1820 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1821 return ERROR_OK;
1822 }
1823
1824 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1825 {
1826 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1827 command_print(CMD_CTX, "trace capture not completed");
1828 return ERROR_FAIL;
1829 }
1830
1831 /* read the trace data if it wasn't read already */
1832 if (etm_ctx->trace_depth == 0)
1833 etm_ctx->capture_driver->read_trace(etm_ctx);
1834
1835 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1836 {
1837 return ERROR_FAIL;
1838 }
1839
1840 fileio_write_u32(&file, etm_ctx->capture_status);
1841 fileio_write_u32(&file, etm_ctx->control);
1842 fileio_write_u32(&file, etm_ctx->trace_depth);
1843
1844 for (i = 0; i < etm_ctx->trace_depth; i++)
1845 {
1846 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1847 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1848 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1849 }
1850
1851 fileio_close(&file);
1852
1853 return ERROR_OK;
1854 }
1855
1856 COMMAND_HANDLER(handle_etm_load_command)
1857 {
1858 struct fileio file;
1859 struct target *target;
1860 struct arm *arm;
1861 struct etm_context *etm_ctx;
1862 uint32_t i;
1863
1864 if (CMD_ARGC != 1)
1865 {
1866 command_print(CMD_CTX, "usage: etm load <file>");
1867 return ERROR_FAIL;
1868 }
1869
1870 target = get_current_target(CMD_CTX);
1871 arm = target_to_arm(target);
1872 if (!is_arm(arm))
1873 {
1874 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1875 return ERROR_FAIL;
1876 }
1877
1878 etm_ctx = arm->etm;
1879 if (!etm_ctx)
1880 {
1881 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1882 return ERROR_FAIL;
1883 }
1884
1885 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1886 {
1887 command_print(CMD_CTX, "trace capture running, stop first");
1888 return ERROR_FAIL;
1889 }
1890
1891 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1892 {
1893 return ERROR_FAIL;
1894 }
1895
1896 if (file.size % 4)
1897 {
1898 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1899 fileio_close(&file);
1900 return ERROR_FAIL;
1901 }
1902
1903 if (etm_ctx->trace_depth > 0)
1904 {
1905 free(etm_ctx->trace_data);
1906 etm_ctx->trace_data = NULL;
1907 }
1908
1909 {
1910 uint32_t tmp;
1911 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1912 fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
1913 fileio_read_u32(&file, &etm_ctx->trace_depth);
1914 }
1915 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1916 if (etm_ctx->trace_data == NULL)
1917 {
1918 command_print(CMD_CTX, "not enough memory to perform operation");
1919 fileio_close(&file);
1920 return ERROR_FAIL;
1921 }
1922
1923 for (i = 0; i < etm_ctx->trace_depth; i++)
1924 {
1925 uint32_t pipestat, packet, flags;
1926 fileio_read_u32(&file, &pipestat);
1927 fileio_read_u32(&file, &packet);
1928 fileio_read_u32(&file, &flags);
1929 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1930 etm_ctx->trace_data[i].packet = packet & 0xffff;
1931 etm_ctx->trace_data[i].flags = flags;
1932 }
1933
1934 fileio_close(&file);
1935
1936 return ERROR_OK;
1937 }
1938
1939 COMMAND_HANDLER(handle_etm_start_command)
1940 {
1941 struct target *target;
1942 struct arm *arm;
1943 struct etm_context *etm_ctx;
1944 struct reg *etm_ctrl_reg;
1945
1946 target = get_current_target(CMD_CTX);
1947 arm = target_to_arm(target);
1948 if (!is_arm(arm))
1949 {
1950 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1951 return ERROR_FAIL;
1952 }
1953
1954 etm_ctx = arm->etm;
1955 if (!etm_ctx)
1956 {
1957 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1958 return ERROR_FAIL;
1959 }
1960
1961 /* invalidate old tracing data */
1962 etm_ctx->capture_status = TRACE_IDLE;
1963 if (etm_ctx->trace_depth > 0)
1964 {
1965 free(etm_ctx->trace_data);
1966 etm_ctx->trace_data = NULL;
1967 }
1968 etm_ctx->trace_depth = 0;
1969
1970 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1971 if (!etm_ctrl_reg)
1972 return ERROR_FAIL;
1973
1974 etm_get_reg(etm_ctrl_reg);
1975
1976 /* Clear programming bit (10), set port selection bit (11) */
1977 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1978
1979 etm_store_reg(etm_ctrl_reg);
1980 jtag_execute_queue();
1981
1982 etm_ctx->capture_driver->start_capture(etm_ctx);
1983
1984 return ERROR_OK;
1985 }
1986
1987 COMMAND_HANDLER(handle_etm_stop_command)
1988 {
1989 struct target *target;
1990 struct arm *arm;
1991 struct etm_context *etm_ctx;
1992 struct reg *etm_ctrl_reg;
1993
1994 target = get_current_target(CMD_CTX);
1995 arm = target_to_arm(target);
1996 if (!is_arm(arm))
1997 {
1998 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1999 return ERROR_FAIL;
2000 }
2001
2002 etm_ctx = arm->etm;
2003 if (!etm_ctx)
2004 {
2005 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2006 return ERROR_FAIL;
2007 }
2008
2009 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2010 if (!etm_ctrl_reg)
2011 return ERROR_FAIL;
2012
2013 etm_get_reg(etm_ctrl_reg);
2014
2015 /* Set programming bit (10), clear port selection bit (11) */
2016 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2017
2018 etm_store_reg(etm_ctrl_reg);
2019 jtag_execute_queue();
2020
2021 etm_ctx->capture_driver->stop_capture(etm_ctx);
2022
2023 return ERROR_OK;
2024 }
2025
2026 COMMAND_HANDLER(handle_etm_trigger_debug_command)
2027 {
2028 struct target *target;
2029 struct arm *arm;
2030 struct etm_context *etm;
2031
2032 target = get_current_target(CMD_CTX);
2033 arm = target_to_arm(target);
2034 if (!is_arm(arm))
2035 {
2036 command_print(CMD_CTX, "ETM: %s isn't an ARM",
2037 target_name(target));
2038 return ERROR_FAIL;
2039 }
2040
2041 etm = arm->etm;
2042 if (!etm)
2043 {
2044 command_print(CMD_CTX, "ETM: no ETM configured for %s",
2045 target_name(target));
2046 return ERROR_FAIL;
2047 }
2048
2049 if (CMD_ARGC == 1) {
2050 struct reg *etm_ctrl_reg;
2051 bool dbgrq;
2052
2053 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
2054 if (!etm_ctrl_reg)
2055 return ERROR_FAIL;
2056
2057 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
2058 if (dbgrq)
2059 etm->control |= ETM_CTRL_DBGRQ;
2060 else
2061 etm->control &= ~ETM_CTRL_DBGRQ;
2062
2063 /* etm->control will be written to hardware
2064 * the next time an "etm start" is issued.
2065 */
2066 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
2067 }
2068
2069 command_print(CMD_CTX, "ETM: %s debug halt",
2070 (etm->control & ETM_CTRL_DBGRQ)
2071 ? "triggers"
2072 : "does not trigger");
2073 return ERROR_OK;
2074 }
2075
2076 COMMAND_HANDLER(handle_etm_analyze_command)
2077 {
2078 struct target *target;
2079 struct arm *arm;
2080 struct etm_context *etm_ctx;
2081 int retval;
2082
2083 target = get_current_target(CMD_CTX);
2084 arm = target_to_arm(target);
2085 if (!is_arm(arm))
2086 {
2087 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2088 return ERROR_FAIL;
2089 }
2090
2091 etm_ctx = arm->etm;
2092 if (!etm_ctx)
2093 {
2094 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2095 return ERROR_FAIL;
2096 }
2097
2098 if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2099 {
2100 switch (retval)
2101 {
2102 case ERROR_ETM_ANALYSIS_FAILED:
2103 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2104 break;
2105 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2106 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2107 break;
2108 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2109 command_print(CMD_CTX, "no image available for trace analysis");
2110 break;
2111 default:
2112 command_print(CMD_CTX, "unknown error: %i", retval);
2113 }
2114 }
2115
2116 return retval;
2117 }
2118
2119 static const struct command_registration etm_config_command_handlers[] = {
2120 {
2121 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2122 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2123 *
2124 * Also, these parameters don't match ETM v3+ modules...
2125 */
2126 .name = "config",
2127 .handler = handle_etm_config_command,
2128 .mode = COMMAND_CONFIG,
2129 .help = "Set up ETM output port.",
2130 .usage = "target port_width port_mode clocking capture_driver",
2131 },
2132 COMMAND_REGISTRATION_DONE
2133 };
2134 const struct command_registration etm_command_handlers[] = {
2135 {
2136 .name = "etm",
2137 .mode = COMMAND_ANY,
2138 .help = "Emebdded Trace Macrocell command group",
2139 .chain = etm_config_command_handlers,
2140 },
2141 COMMAND_REGISTRATION_DONE
2142 };
2143
2144 static const struct command_registration etm_exec_command_handlers[] = {
2145 {
2146 .name = "tracemode",
2147 .handler = handle_etm_tracemode_command,
2148 .mode = COMMAND_EXEC,
2149 .help = "configure/display trace mode",
2150 .usage = "('none'|'data'|'address'|'all') "
2151 "context_id_bits "
2152 "['enable'|'disable'] "
2153 "['enable'|'disable']",
2154 },
2155 {
2156 .name = "info",
2157 .handler = handle_etm_info_command,
2158 .mode = COMMAND_EXEC,
2159 .help = "display info about the current target's ETM",
2160 },
2161 {
2162 .name = "status",
2163 .handler = handle_etm_status_command,
2164 .mode = COMMAND_EXEC,
2165 .help = "display current target's ETM status",
2166 },
2167 {
2168 .name = "start",
2169 .handler = handle_etm_start_command,
2170 .mode = COMMAND_EXEC,
2171 .help = "start ETM trace collection",
2172 },
2173 {
2174 .name = "stop",
2175 .handler = handle_etm_stop_command,
2176 .mode = COMMAND_EXEC,
2177 .help = "stop ETM trace collection",
2178 },
2179 {
2180 .name = "trigger_debug",
2181 .handler = handle_etm_trigger_debug_command,
2182 .mode = COMMAND_EXEC,
2183 .help = "enable/disable debug entry on trigger",
2184 .usage = "['enable'|'disable']",
2185 },
2186 {
2187 .name = "analyze",
2188 .handler = handle_etm_analyze_command,
2189 .mode = COMMAND_EXEC,
2190 .help = "analyze collected ETM trace",
2191 },
2192 {
2193 .name = "image",
2194 .handler = handle_etm_image_command,
2195 .mode = COMMAND_EXEC,
2196 .help = "load image from file with optional offset",
2197 .usage = "filename [offset]",
2198 },
2199 {
2200 .name = "dump",
2201 .handler = handle_etm_dump_command,
2202 .mode = COMMAND_EXEC,
2203 .help = "dump captured trace data to file",
2204 .usage = "filename",
2205 },
2206 {
2207 .name = "load",
2208 .handler = handle_etm_load_command,
2209 .mode = COMMAND_EXEC,
2210 .help = "load trace data for analysis <file>",
2211 },
2212 COMMAND_REGISTRATION_DONE
2213 };
2214
2215 static int etm_register_user_commands(struct command_context *cmd_ctx)
2216 {
2217 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2218 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2219 }
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