1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "arm7_9_common.h"
28 #include "arm_disassembler.h"
32 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
34 * ETM modules collect instruction and/or data trace information, compress
35 * it, and transfer it to a debugging host through either a (buffered) trace
36 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
38 * There are several generations of these modules. Original versions have
39 * JTAG access through a dedicated scan chain. Recent versions have added
40 * access via coprocessor instructions, memory addressing, and the ARM Debug
41 * Interface v5 (ADIv5); and phased out direct JTAG access.
43 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
44 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
45 * implying non-JTAG connectivity options.
47 * Relevant documentation includes:
48 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
49 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
50 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
53 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
63 uint8_t size
; /* low-N of 32 bits */
64 uint8_t mode
; /* RO, WO, RW */
65 uint8_t bcd_vers
; /* 1.0, 2.0, etc */
70 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
71 * Newer versions of ETM make some W/O registers R/W, and
72 * provide definitions for some previously-unused bits.
75 /* basic registers that are always there given the right ETM version */
76 static const struct etm_reg_info etm_core
[] = {
77 /* NOTE: we "know" ETM_CONFIG is listed first */
78 { ETM_CONFIG
, 32, RO
, 0x10, "ETM_CONFIG", },
80 /* ETM Trace Registers */
81 { ETM_CTRL
, 32, RW
, 0x10, "ETM_CTRL", },
82 { ETM_TRIG_EVENT
, 17, WO
, 0x10, "ETM_TRIG_EVENT", },
83 { ETM_ASIC_CTRL
, 8, WO
, 0x10, "ETM_ASIC_CTRL", },
84 { ETM_STATUS
, 3, RO
, 0x11, "ETM_STATUS", },
85 { ETM_SYS_CONFIG
, 9, RO
, 0x12, "ETM_SYS_CONFIG", },
87 /* TraceEnable configuration */
88 { ETM_TRACE_RESOURCE_CTRL
, 32, WO
, 0x12, "ETM_TRACE_RESOURCE_CTRL", },
89 { ETM_TRACE_EN_CTRL2
, 16, WO
, 0x12, "ETM_TRACE_EN_CTRL2", },
90 { ETM_TRACE_EN_EVENT
, 17, WO
, 0x10, "ETM_TRACE_EN_EVENT", },
91 { ETM_TRACE_EN_CTRL1
, 26, WO
, 0x10, "ETM_TRACE_EN_CTRL1", },
93 /* ViewData configuration (data trace) */
94 { ETM_VIEWDATA_EVENT
, 17, WO
, 0x10, "ETM_VIEWDATA_EVENT", },
95 { ETM_VIEWDATA_CTRL1
, 32, WO
, 0x10, "ETM_VIEWDATA_CTRL1", },
96 { ETM_VIEWDATA_CTRL2
, 32, WO
, 0x10, "ETM_VIEWDATA_CTRL2", },
97 { ETM_VIEWDATA_CTRL3
, 17, WO
, 0x10, "ETM_VIEWDATA_CTRL3", },
99 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
101 { 0x78, 12, WO
, 0x20, "ETM_SYNC_FREQ", },
102 { 0x79, 32, RO
, 0x20, "ETM_ID", },
105 static const struct etm_reg_info etm_fifofull
[] = {
106 /* FIFOFULL configuration */
107 { ETM_FIFOFULL_REGION
, 25, WO
, 0x10, "ETM_FIFOFULL_REGION", },
108 { ETM_FIFOFULL_LEVEL
, 8, WO
, 0x10, "ETM_FIFOFULL_LEVEL", },
111 static const struct etm_reg_info etm_addr_comp
[] = {
112 /* Address comparator register pairs */
113 #define ADDR_COMPARATOR(i) \
114 { ETM_ADDR_COMPARATOR_VALUE + (i), 32, WO, 0x10, \
115 "ETM_ADDR_COMPARATOR_VALUE" #i, }, \
116 { ETM_ADDR_ACCESS_TYPE + (i), 7, WO, 0x10, \
117 "ETM_ADDR_ACCESS_TYPE" #i, }
135 #undef ADDR_COMPARATOR
138 static const struct etm_reg_info etm_data_comp
[] = {
139 /* Data Value Comparators (NOTE: odd addresses are reserved) */
140 #define DATA_COMPARATOR(i) \
141 { ETM_DATA_COMPARATOR_VALUE + 2*(i), 32, WO, 0x10, \
142 "ETM_DATA_COMPARATOR_VALUE" #i, }, \
143 { ETM_DATA_COMPARATOR_MASK + 2*(i), 32, WO, 0x10, \
144 "ETM_DATA_COMPARATOR_MASK" #i, }
153 #undef DATA_COMPARATOR
156 static const struct etm_reg_info etm_counters
[] = {
158 { ETM_COUNTER_RELOAD_VALUE + (i), 16, WO, 0x10, \
159 "ETM_COUNTER_RELOAD_VALUE" #i, }, \
160 { ETM_COUNTER_ENABLE + (i), 18, WO, 0x10, \
161 "ETM_COUNTER_ENABLE" #i, }, \
162 { ETM_COUNTER_RELOAD_EVENT + (i), 17, WO, 0x10, \
163 "ETM_COUNTER_RELOAD_EVENT" #i, }, \
164 { ETM_COUNTER_VALUE + (i), 16, RO, 0x10, \
165 "ETM_COUNTER_VALUE" #i, }
173 static const struct etm_reg_info etm_sequencer
[] = {
175 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
176 "ETM_SEQUENCER_EVENT" #i, }
185 { ETM_SEQUENCER_STATE
, 2, RO
, 0x10, "ETM_SEQUENCER_STATE", },
188 static const struct etm_reg_info etm_outputs
[] = {
190 { ETM_EXTERNAL_OUTPUT + (i), 17, WO, 0x10, \
191 "ETM_EXTERNAL_OUTPUT" #i, }
201 /* registers from 0x6c..0x7f were added after ETMv1.3 */
203 /* Context ID Comparators */
204 { 0x6c, 32, RO
, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
205 { 0x6d, 32, RO
, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
206 { 0x6e, 32, RO
, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
207 { 0x6f, 32, RO
, 0x20, "ETM_CONTEXTID_COMPARATOR_MASK", }
210 static int etm_reg_arch_type
= -1;
212 static int etm_get_reg(reg_t
*reg
);
213 static int etm_read_reg_w_check(reg_t
*reg
,
214 uint8_t* check_value
, uint8_t* check_mask
);
215 static int etm_register_user_commands(struct command_context_s
*cmd_ctx
);
216 static int etm_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
);
217 static int etm_write_reg(reg_t
*reg
, uint32_t value
);
219 static command_t
*etm_cmd
;
222 /* Look up register by ID ... most ETM instances only
223 * support a subset of the possible registers.
225 static reg_t
*etm_reg_lookup(etm_context_t
*etm_ctx
, unsigned id
)
227 reg_cache_t
*cache
= etm_ctx
->reg_cache
;
230 for (i
= 0; i
< cache
->num_regs
; i
++) {
231 struct etm_reg_s
*reg
= cache
->reg_list
[i
].arch_info
;
233 if (reg
->reg_info
->addr
== id
)
234 return &cache
->reg_list
[i
];
237 /* caller asking for nonexistent register is a bug! */
238 /* REVISIT say which of the N targets was involved */
239 LOG_ERROR("ETM: register 0x%02x not available", id
);
243 static void etm_reg_add(unsigned bcd_vers
, arm_jtag_t
*jtag_info
,
244 reg_cache_t
*cache
, etm_reg_t
*ereg
,
245 const struct etm_reg_info
*r
, unsigned nreg
)
247 reg_t
*reg
= cache
->reg_list
;
249 reg
+= cache
->num_regs
;
250 ereg
+= cache
->num_regs
;
252 /* add up to "nreg" registers from "r", if supported by this
253 * version of the ETM, to the specified cache.
255 for (; nreg
--; r
++) {
257 /* this ETM may be too old to have some registers */
258 if (r
->bcd_vers
> bcd_vers
)
263 reg
->value
= &ereg
->value
;
264 reg
->arch_info
= ereg
;
265 reg
->arch_type
= etm_reg_arch_type
;
270 ereg
->jtag_info
= jtag_info
;
275 reg_cache_t
*etm_build_reg_cache(target_t
*target
,
276 arm_jtag_t
*jtag_info
, etm_context_t
*etm_ctx
)
278 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
279 reg_t
*reg_list
= NULL
;
280 etm_reg_t
*arch_info
= NULL
;
281 unsigned bcd_vers
, config
;
283 /* register a register arch-type for etm registers only once */
284 if (etm_reg_arch_type
== -1)
285 etm_reg_arch_type
= register_reg_arch_type(etm_get_reg
,
288 /* the actual registers are kept in two arrays */
289 reg_list
= calloc(128, sizeof(reg_t
));
290 arch_info
= calloc(128, sizeof(etm_reg_t
));
292 /* fill in values for the reg cache */
293 reg_cache
->name
= "etm registers";
294 reg_cache
->next
= NULL
;
295 reg_cache
->reg_list
= reg_list
;
296 reg_cache
->num_regs
= 0;
298 /* add ETM_CONFIG, then parse its values to see
299 * which other registers exist in this ETM
301 etm_reg_add(0x10, jtag_info
, reg_cache
, arch_info
,
304 etm_get_reg(reg_list
);
305 etm_ctx
->config
= buf_get_u32((void *)&arch_info
->value
, 0, 32);
306 config
= etm_ctx
->config
;
308 /* figure ETM version then add base registers */
309 if (config
& (1 << 31)) {
311 LOG_WARNING("ETMv2+ support is incomplete");
313 /* REVISIT read ID register, distinguish ETMv3.3 etc;
314 * don't presume trace start/stop support is present;
315 * and include any context ID comparator registers.
318 switch (config
>> 28) {
335 LOG_WARNING("Bad ETMv1 protocol %d", config
>> 28);
342 etm_ctx
->bcd_vers
= bcd_vers
;
343 LOG_INFO("ETM v%d.%d", bcd_vers
>> 4, bcd_vers
& 0xf);
345 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
346 etm_core
+ 1, ARRAY_SIZE(etm_core
) - 1);
348 /* address and data comparators; counters; outputs */
349 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
350 etm_addr_comp
, 4 * (0x0f & (config
>> 0)));
351 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
352 etm_data_comp
, 2 * (0x0f & (config
>> 4)));
353 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
354 etm_counters
, 4 * (0x07 & (config
>> 13)));
355 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
356 etm_outputs
, (0x07 & (config
>> 20)));
358 /* FIFOFULL presence is optional
359 * REVISIT for ETMv1.2 and later, don't bother adding this
360 * unless ETM_SYS_CONFIG says it's also *supported* ...
362 if (config
& (1 << 23))
363 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
364 etm_fifofull
, ARRAY_SIZE(etm_fifofull
));
366 /* sequencer is optional (for state-dependant triggering) */
367 if (config
& (1 << 16))
368 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
369 etm_sequencer
, ARRAY_SIZE(etm_sequencer
));
371 /* REVISIT could realloc and likely save half the memory
372 * in the two chunks we allocated...
375 /* the ETM might have an ETB connected */
376 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0)
378 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
382 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
389 reg_cache
->next
= etb_build_reg_cache(etb
);
391 etb
->reg_cache
= reg_cache
->next
;
398 static int etm_read_reg(reg_t
*reg
)
400 return etm_read_reg_w_check(reg
, NULL
, NULL
);
403 static int etm_store_reg(reg_t
*reg
)
405 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
408 int etm_setup(target_t
*target
)
411 uint32_t etm_ctrl_value
;
412 armv4_5_common_t
*armv4_5
= target
->arch_info
;
413 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
414 etm_context_t
*etm_ctx
= arm7_9
->etm_ctx
;
417 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
421 /* initialize some ETM control register settings */
422 etm_get_reg(etm_ctrl_reg
);
423 etm_ctrl_value
= buf_get_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
);
425 /* clear the ETM powerdown bit (0) */
426 etm_ctrl_value
&= ~0x1;
428 /* configure port width (6:4), mode (17:16) and clocking (13) */
429 etm_ctrl_value
= (etm_ctrl_value
&
430 ~ETM_PORT_WIDTH_MASK
& ~ETM_PORT_MODE_MASK
& ~ETM_PORT_CLOCK_MASK
)
433 buf_set_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
, etm_ctrl_value
);
434 etm_store_reg(etm_ctrl_reg
);
436 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
439 if ((retval
= etm_ctx
->capture_driver
->init(etm_ctx
)) != ERROR_OK
)
441 LOG_ERROR("ETM capture driver initialization failed");
447 static int etm_get_reg(reg_t
*reg
)
451 if ((retval
= etm_read_reg(reg
)) != ERROR_OK
)
453 LOG_ERROR("BUG: error scheduling etm register read");
457 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
459 LOG_ERROR("register read failed");
466 static int etm_read_reg_w_check(reg_t
*reg
,
467 uint8_t* check_value
, uint8_t* check_mask
)
469 etm_reg_t
*etm_reg
= reg
->arch_info
;
470 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
471 uint8_t reg_addr
= r
->addr
& 0x7f;
472 scan_field_t fields
[3];
474 if (etm_reg
->reg_info
->mode
== WO
) {
475 LOG_ERROR("BUG: can't read write-only register %s", r
->name
);
476 return ERROR_INVALID_ARGUMENTS
;
479 LOG_DEBUG("%s (%u)", r
->name
, reg_addr
);
481 jtag_set_end_state(TAP_IDLE
);
482 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
483 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
485 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
486 fields
[0].num_bits
= 32;
487 fields
[0].out_value
= reg
->value
;
488 fields
[0].in_value
= NULL
;
489 fields
[0].check_value
= NULL
;
490 fields
[0].check_mask
= NULL
;
492 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
493 fields
[1].num_bits
= 7;
494 fields
[1].out_value
= malloc(1);
495 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
496 fields
[1].in_value
= NULL
;
497 fields
[1].check_value
= NULL
;
498 fields
[1].check_mask
= NULL
;
500 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
501 fields
[2].num_bits
= 1;
502 fields
[2].out_value
= malloc(1);
503 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
504 fields
[2].in_value
= NULL
;
505 fields
[2].check_value
= NULL
;
506 fields
[2].check_mask
= NULL
;
508 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
510 fields
[0].in_value
= reg
->value
;
511 fields
[0].check_value
= check_value
;
512 fields
[0].check_mask
= check_mask
;
514 jtag_add_dr_scan_check(3, fields
, jtag_get_end_state());
516 free(fields
[1].out_value
);
517 free(fields
[2].out_value
);
522 static int etm_set_reg(reg_t
*reg
, uint32_t value
)
526 if ((retval
= etm_write_reg(reg
, value
)) != ERROR_OK
)
528 LOG_ERROR("BUG: error scheduling etm register write");
532 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
539 static int etm_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
)
543 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
545 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
547 LOG_ERROR("register write failed");
553 static int etm_write_reg(reg_t
*reg
, uint32_t value
)
555 etm_reg_t
*etm_reg
= reg
->arch_info
;
556 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
557 uint8_t reg_addr
= r
->addr
& 0x7f;
558 scan_field_t fields
[3];
560 if (etm_reg
->reg_info
->mode
== RO
) {
561 LOG_ERROR("BUG: can't write read--only register %s", r
->name
);
562 return ERROR_INVALID_ARGUMENTS
;
565 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32
"", r
->name
, reg_addr
, value
);
567 jtag_set_end_state(TAP_IDLE
);
568 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
569 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
571 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
572 fields
[0].num_bits
= 32;
574 fields
[0].out_value
= tmp1
;
575 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
576 fields
[0].in_value
= NULL
;
578 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
579 fields
[1].num_bits
= 7;
581 fields
[1].out_value
= &tmp2
;
582 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
583 fields
[1].in_value
= NULL
;
585 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
586 fields
[2].num_bits
= 1;
588 fields
[2].out_value
= &tmp3
;
589 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
590 fields
[2].in_value
= NULL
;
592 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
598 /* ETM trace analysis functionality
601 extern etm_capture_driver_t etm_dummy_capture_driver
;
602 #if BUILD_OOCD_TRACE == 1
603 extern etm_capture_driver_t oocd_trace_capture_driver
;
606 static etm_capture_driver_t
*etm_capture_drivers
[] =
609 &etm_dummy_capture_driver
,
610 #if BUILD_OOCD_TRACE == 1
611 &oocd_trace_capture_driver
,
616 static int etm_read_instruction(etm_context_t
*ctx
, arm_instruction_t
*instruction
)
625 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
627 /* search for the section the current instruction belongs to */
628 for (i
= 0; i
< ctx
->image
->num_sections
; i
++)
630 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
631 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
> ctx
->current_pc
))
640 /* current instruction couldn't be found in the image */
641 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
644 if (ctx
->core_state
== ARMV4_5_STATE_ARM
)
647 if ((retval
= image_read_section(ctx
->image
, section
,
648 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
649 4, buf
, &size_read
)) != ERROR_OK
)
651 LOG_ERROR("error while reading instruction: %i", retval
);
652 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
654 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
655 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
657 else if (ctx
->core_state
== ARMV4_5_STATE_THUMB
)
660 if ((retval
= image_read_section(ctx
->image
, section
,
661 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
662 2, buf
, &size_read
)) != ERROR_OK
)
664 LOG_ERROR("error while reading instruction: %i", retval
);
665 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
667 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
668 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
670 else if (ctx
->core_state
== ARMV4_5_STATE_JAZELLE
)
672 LOG_ERROR("BUG: tracing of jazelle code not supported");
677 LOG_ERROR("BUG: unknown core state encountered");
684 static int etmv1_next_packet(etm_context_t
*ctx
, uint8_t *packet
, int apo
)
686 while (ctx
->data_index
< ctx
->trace_depth
)
688 /* if the caller specified an address packet offset, skip until the
689 * we reach the n-th cycle marked with tracesync */
692 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
703 /* no tracedata output during a TD cycle
704 * or in a trigger cycle */
705 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
706 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
))
713 if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
)
715 if (ctx
->data_half
== 0)
717 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
722 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
727 else if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
729 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
734 /* on a 4-bit port, a packet will be output during two consecutive cycles */
735 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
738 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
739 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
740 ctx
->data_index
+= 2;
749 static int etmv1_branch_address(etm_context_t
*ctx
)
757 /* quit analysis if less than two cycles are left in the trace
758 * because we can't extract the APO */
759 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
762 /* a BE could be output during an APO cycle, skip the current
763 * and continue with the new one */
764 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
766 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
769 /* address packet offset encoded in the next two cycles' pipestat bits */
770 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
771 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
773 /* count number of tracesync cycles between current pipe_index and data_index
774 * i.e. the number of tracesyncs that data_index already passed by
775 * to subtract them from the APO */
776 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++)
778 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
782 /* extract up to four 7-bit packets */
784 if ((retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0)) != 0)
786 ctx
->last_branch
&= ~(0x7f << shift
);
787 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
789 } while ((packet
& 0x80) && (shift
< 28));
791 /* one last packet holding 4 bits of the address, plus the branch reason code */
792 if ((shift
== 28) && (packet
& 0x80))
794 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
796 ctx
->last_branch
&= 0x0fffffff;
797 ctx
->last_branch
|= (packet
& 0x0f) << 28;
798 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
803 ctx
->last_branch_reason
= 0;
811 /* if a full address was output, we might have branched into Jazelle state */
812 if ((shift
== 32) && (packet
& 0x80))
814 ctx
->core_state
= ARMV4_5_STATE_JAZELLE
;
818 /* if we didn't branch into Jazelle state, the current processor state is
819 * encoded in bit 0 of the branch target address */
820 if (ctx
->last_branch
& 0x1)
822 ctx
->core_state
= ARMV4_5_STATE_THUMB
;
823 ctx
->last_branch
&= ~0x1;
827 ctx
->core_state
= ARMV4_5_STATE_ARM
;
828 ctx
->last_branch
&= ~0x3;
835 static int etmv1_data(etm_context_t
*ctx
, int size
, uint32_t *data
)
841 for (j
= 0; j
< size
; j
++)
843 if ((retval
= etmv1_next_packet(ctx
, &buf
[j
], 0)) != 0)
849 LOG_ERROR("TODO: add support for 64-bit values");
853 *data
= target_buffer_get_u32(ctx
->target
, buf
);
855 *data
= target_buffer_get_u16(ctx
->target
, buf
);
864 static int etmv1_analyze_trace(etm_context_t
*ctx
, struct command_context_s
*cmd_ctx
)
867 arm_instruction_t instruction
;
869 /* read the trace data if it wasn't read already */
870 if (ctx
->trace_depth
== 0)
871 ctx
->capture_driver
->read_trace(ctx
);
873 /* start at the beginning of the captured trace */
878 /* neither the PC nor the data pointer are valid */
882 while (ctx
->pipe_index
< ctx
->trace_depth
)
884 uint8_t pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
885 uint32_t next_pc
= ctx
->current_pc
;
886 uint32_t old_data_index
= ctx
->data_index
;
887 uint32_t old_data_half
= ctx
->data_half
;
888 uint32_t old_index
= ctx
->pipe_index
;
889 uint32_t last_instruction
= ctx
->last_instruction
;
891 int current_pc_ok
= ctx
->pc_ok
;
893 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
895 command_print(cmd_ctx
, "--- trigger ---");
898 /* instructions execute in IE/D or BE/D cycles */
899 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
900 ctx
->last_instruction
= ctx
->pipe_index
;
902 /* if we don't have a valid pc skip until we reach an indirect branch */
903 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
))
909 /* any indirect branch could have interrupted instruction flow
910 * - the branch reason code could indicate a trace discontinuity
911 * - a branch to the exception vectors indicates an exception
913 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
))
915 /* backup current data index, to be able to consume the branch address
916 * before examining data address and values
918 old_data_index
= ctx
->data_index
;
919 old_data_half
= ctx
->data_half
;
921 ctx
->last_instruction
= ctx
->pipe_index
;
923 if ((retval
= etmv1_branch_address(ctx
)) != 0)
925 /* negative return value from etmv1_branch_address means we ran out of packets,
926 * quit analysing the trace */
930 /* a positive return values means the current branch was abandoned,
931 * and a new branch was encountered in cycle ctx->pipe_index + retval;
933 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
934 ctx
->pipe_index
+= retval
;
938 /* skip over APO cycles */
939 ctx
->pipe_index
+= 2;
941 switch (ctx
->last_branch_reason
)
943 case 0x0: /* normal PC change */
944 next_pc
= ctx
->last_branch
;
946 case 0x1: /* tracing enabled */
947 command_print(cmd_ctx
, "--- tracing enabled at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
948 ctx
->current_pc
= ctx
->last_branch
;
952 case 0x2: /* trace restarted after FIFO overflow */
953 command_print(cmd_ctx
, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
954 ctx
->current_pc
= ctx
->last_branch
;
958 case 0x3: /* exit from debug state */
959 command_print(cmd_ctx
, "--- exit from debug state at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
960 ctx
->current_pc
= ctx
->last_branch
;
964 case 0x4: /* periodic synchronization point */
965 next_pc
= ctx
->last_branch
;
966 /* if we had no valid PC prior to this synchronization point,
967 * we have to move on with the next trace cycle
971 command_print(cmd_ctx
, "--- periodic synchronization point at 0x%8.8" PRIx32
" ---", next_pc
);
972 ctx
->current_pc
= next_pc
;
977 default: /* reserved */
978 LOG_ERROR("BUG: branch reason code 0x%" PRIx32
" is reserved", ctx
->last_branch_reason
);
983 /* if we got here the branch was a normal PC change
984 * (or a periodic synchronization point, which means the same for that matter)
985 * if we didn't accquire a complete PC continue with the next cycle
990 /* indirect branch to the exception vector means an exception occured */
991 if ((ctx
->last_branch
<= 0x20)
992 || ((ctx
->last_branch
>= 0xffff0000) && (ctx
->last_branch
<= 0xffff0020)))
994 if ((ctx
->last_branch
& 0xff) == 0x10)
996 command_print(cmd_ctx
, "data abort");
1000 command_print(cmd_ctx
, "exception vector 0x%2.2" PRIx32
"", ctx
->last_branch
);
1001 ctx
->current_pc
= ctx
->last_branch
;
1008 /* an instruction was executed (or not, depending on the condition flags)
1009 * retrieve it from the image for displaying */
1010 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
1011 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
1012 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4))))
1014 if ((retval
= etm_read_instruction(ctx
, &instruction
)) != ERROR_OK
)
1016 /* can't continue tracing with no image available */
1017 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
1021 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
1023 /* TODO: handle incomplete images
1024 * for now we just quit the analsysis*/
1029 cycles
= old_index
- last_instruction
;
1032 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
))
1034 uint32_t new_data_index
= ctx
->data_index
;
1035 uint32_t new_data_half
= ctx
->data_half
;
1037 /* in case of a branch with data, the branch target address was consumed before
1038 * we temporarily go back to the saved data index */
1039 if (pipestat
== STAT_BD
)
1041 ctx
->data_index
= old_data_index
;
1042 ctx
->data_half
= old_data_half
;
1045 if (ctx
->tracemode
& ETMV1_TRACE_ADDR
)
1051 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
1052 return ERROR_ETM_ANALYSIS_FAILED
;
1053 ctx
->last_ptr
&= ~(0x7f << shift
);
1054 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
1056 } while ((packet
& 0x80) && (shift
< 32));
1063 command_print(cmd_ctx
, "address: 0x%8.8" PRIx32
"", ctx
->last_ptr
);
1067 if (ctx
->tracemode
& ETMV1_TRACE_DATA
)
1069 if ((instruction
.type
== ARM_LDM
) || (instruction
.type
== ARM_STM
))
1072 for (i
= 0; i
< 16; i
++)
1074 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
1077 if (etmv1_data(ctx
, 4, &data
) != 0)
1078 return ERROR_ETM_ANALYSIS_FAILED
;
1079 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1083 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_STRH
))
1086 if (etmv1_data(ctx
, arm_access_size(&instruction
), &data
) != 0)
1087 return ERROR_ETM_ANALYSIS_FAILED
;
1088 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1092 /* restore data index after consuming BD address and data */
1093 if (pipestat
== STAT_BD
)
1095 ctx
->data_index
= new_data_index
;
1096 ctx
->data_half
= new_data_half
;
1101 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
1103 if (((instruction
.type
== ARM_B
) ||
1104 (instruction
.type
== ARM_BL
) ||
1105 (instruction
.type
== ARM_BLX
)) &&
1106 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff))
1108 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
1112 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
1115 else if (pipestat
== STAT_IN
)
1117 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
1120 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
))
1122 char cycles_text
[32] = "";
1124 /* if the trace was captured with cycle accurate tracing enabled,
1125 * output the number of cycles since the last executed instruction
1127 if (ctx
->tracemode
& ETMV1_CYCLE_ACCURATE
)
1129 snprintf(cycles_text
, 32, " (%i %s)",
1131 (cycles
== 1) ? "cycle" : "cycles");
1134 command_print(cmd_ctx
, "%s%s%s",
1136 (pipestat
== STAT_IN
) ? " (not executed)" : "",
1139 ctx
->current_pc
= next_pc
;
1141 /* packets for an instruction don't start on or before the preceding
1142 * functional pipestat (i.e. other than WT or TD)
1144 if (ctx
->data_index
<= ctx
->pipe_index
)
1146 ctx
->data_index
= ctx
->pipe_index
+ 1;
1151 ctx
->pipe_index
+= 1;
1157 static int handle_etm_tracemode_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1160 armv4_5_common_t
*armv4_5
;
1161 arm7_9_common_t
*arm7_9
;
1162 etmv1_tracemode_t tracemode
;
1164 target
= get_current_target(cmd_ctx
);
1166 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1168 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1172 if (!arm7_9
->etm_ctx
)
1174 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1178 tracemode
= arm7_9
->etm_ctx
->tracemode
;
1182 if (strcmp(args
[0], "none") == 0)
1184 tracemode
= ETMV1_TRACE_NONE
;
1186 else if (strcmp(args
[0], "data") == 0)
1188 tracemode
= ETMV1_TRACE_DATA
;
1190 else if (strcmp(args
[0], "address") == 0)
1192 tracemode
= ETMV1_TRACE_ADDR
;
1194 else if (strcmp(args
[0], "all") == 0)
1196 tracemode
= ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
;
1200 command_print(cmd_ctx
, "invalid option '%s'", args
[0]);
1204 switch (strtol(args
[1], NULL
, 0))
1207 tracemode
|= ETMV1_CONTEXTID_NONE
;
1210 tracemode
|= ETMV1_CONTEXTID_8
;
1213 tracemode
|= ETMV1_CONTEXTID_16
;
1216 tracemode
|= ETMV1_CONTEXTID_32
;
1219 command_print(cmd_ctx
, "invalid option '%s'", args
[1]);
1223 if (strcmp(args
[2], "enable") == 0)
1225 tracemode
|= ETMV1_CYCLE_ACCURATE
;
1227 else if (strcmp(args
[2], "disable") == 0)
1233 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1237 if (strcmp(args
[3], "enable") == 0)
1239 tracemode
|= ETMV1_BRANCH_OUTPUT
;
1241 else if (strcmp(args
[3], "disable") == 0)
1247 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1253 command_print(cmd_ctx
, "usage: configure trace mode <none | data | address | all> <context id bits> <cycle accurate> <branch output>");
1257 command_print(cmd_ctx
, "current tracemode configuration:");
1259 switch (tracemode
& ETMV1_TRACE_MASK
)
1261 case ETMV1_TRACE_NONE
:
1262 command_print(cmd_ctx
, "data tracing: none");
1264 case ETMV1_TRACE_DATA
:
1265 command_print(cmd_ctx
, "data tracing: data only");
1267 case ETMV1_TRACE_ADDR
:
1268 command_print(cmd_ctx
, "data tracing: address only");
1270 case ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
:
1271 command_print(cmd_ctx
, "data tracing: address and data");
1275 switch (tracemode
& ETMV1_CONTEXTID_MASK
)
1277 case ETMV1_CONTEXTID_NONE
:
1278 command_print(cmd_ctx
, "contextid tracing: none");
1280 case ETMV1_CONTEXTID_8
:
1281 command_print(cmd_ctx
, "contextid tracing: 8 bit");
1283 case ETMV1_CONTEXTID_16
:
1284 command_print(cmd_ctx
, "contextid tracing: 16 bit");
1286 case ETMV1_CONTEXTID_32
:
1287 command_print(cmd_ctx
, "contextid tracing: 32 bit");
1291 if (tracemode
& ETMV1_CYCLE_ACCURATE
)
1293 command_print(cmd_ctx
, "cycle-accurate tracing enabled");
1297 command_print(cmd_ctx
, "cycle-accurate tracing disabled");
1300 if (tracemode
& ETMV1_BRANCH_OUTPUT
)
1302 command_print(cmd_ctx
, "full branch address output enabled");
1306 command_print(cmd_ctx
, "full branch address output disabled");
1309 /* only update ETM_CTRL register if tracemode changed */
1310 if (arm7_9
->etm_ctx
->tracemode
!= tracemode
)
1312 reg_t
*etm_ctrl_reg
;
1314 etm_ctrl_reg
= etm_reg_lookup(arm7_9
->etm_ctx
, ETM_CTRL
);
1318 etm_get_reg(etm_ctrl_reg
);
1320 buf_set_u32(etm_ctrl_reg
->value
, 2, 2, tracemode
& ETMV1_TRACE_MASK
);
1321 buf_set_u32(etm_ctrl_reg
->value
, 14, 2, (tracemode
& ETMV1_CONTEXTID_MASK
) >> 4);
1322 buf_set_u32(etm_ctrl_reg
->value
, 12, 1, (tracemode
& ETMV1_CYCLE_ACCURATE
) >> 8);
1323 buf_set_u32(etm_ctrl_reg
->value
, 8, 1, (tracemode
& ETMV1_BRANCH_OUTPUT
) >> 9);
1324 etm_store_reg(etm_ctrl_reg
);
1326 arm7_9
->etm_ctx
->tracemode
= tracemode
;
1328 /* invalidate old trace data */
1329 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1330 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1332 free(arm7_9
->etm_ctx
->trace_data
);
1333 arm7_9
->etm_ctx
->trace_data
= NULL
;
1335 arm7_9
->etm_ctx
->trace_depth
= 0;
1341 static int handle_etm_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1344 armv4_5_common_t
*armv4_5
;
1345 arm7_9_common_t
*arm7_9
;
1346 etm_portmode_t portmode
= 0x0;
1347 etm_context_t
*etm_ctx
= malloc(sizeof(etm_context_t
));
1353 return ERROR_COMMAND_SYNTAX_ERROR
;
1356 target
= get_target(args
[0]);
1359 LOG_ERROR("target '%s' not defined", args
[0]);
1364 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1366 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1371 switch (strtoul(args
[1], NULL
, 0))
1374 portmode
|= ETM_PORT_4BIT
;
1377 portmode
|= ETM_PORT_8BIT
;
1380 portmode
|= ETM_PORT_16BIT
;
1383 command_print(cmd_ctx
, "unsupported ETM port width '%s', must be 4, 8 or 16", args
[1]);
1388 if (strcmp("normal", args
[2]) == 0)
1390 portmode
|= ETM_PORT_NORMAL
;
1392 else if (strcmp("multiplexed", args
[2]) == 0)
1394 portmode
|= ETM_PORT_MUXED
;
1396 else if (strcmp("demultiplexed", args
[2]) == 0)
1398 portmode
|= ETM_PORT_DEMUXED
;
1402 command_print(cmd_ctx
, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args
[2]);
1407 if (strcmp("half", args
[3]) == 0)
1409 portmode
|= ETM_PORT_HALF_CLOCK
;
1411 else if (strcmp("full", args
[3]) == 0)
1413 portmode
|= ETM_PORT_FULL_CLOCK
;
1417 command_print(cmd_ctx
, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args
[3]);
1422 for (i
= 0; etm_capture_drivers
[i
]; i
++)
1424 if (strcmp(args
[4], etm_capture_drivers
[i
]->name
) == 0)
1427 if ((retval
= etm_capture_drivers
[i
]->register_commands(cmd_ctx
)) != ERROR_OK
)
1433 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1439 if (!etm_capture_drivers
[i
])
1441 /* no supported capture driver found, don't register an ETM */
1443 LOG_ERROR("trace capture driver '%s' not found", args
[4]);
1447 etm_ctx
->target
= target
;
1448 etm_ctx
->trigger_percent
= 50;
1449 etm_ctx
->trace_data
= NULL
;
1450 etm_ctx
->trace_depth
= 0;
1451 etm_ctx
->portmode
= portmode
;
1452 etm_ctx
->tracemode
= 0x0;
1453 etm_ctx
->core_state
= ARMV4_5_STATE_ARM
;
1454 etm_ctx
->image
= NULL
;
1455 etm_ctx
->pipe_index
= 0;
1456 etm_ctx
->data_index
= 0;
1457 etm_ctx
->current_pc
= 0x0;
1459 etm_ctx
->last_branch
= 0x0;
1460 etm_ctx
->last_branch_reason
= 0x0;
1461 etm_ctx
->last_ptr
= 0x0;
1462 etm_ctx
->ptr_ok
= 0x0;
1463 etm_ctx
->last_instruction
= 0;
1465 arm7_9
->etm_ctx
= etm_ctx
;
1467 return etm_register_user_commands(cmd_ctx
);
1470 static int handle_etm_info_command(struct command_context_s
*cmd_ctx
,
1471 char *cmd
, char **args
, int argc
)
1474 armv4_5_common_t
*armv4_5
;
1475 arm7_9_common_t
*arm7_9
;
1477 reg_t
*etm_sys_config_reg
;
1481 target
= get_current_target(cmd_ctx
);
1483 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1485 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1489 etm
= arm7_9
->etm_ctx
;
1492 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1496 command_print(cmd_ctx
, "ETM v%d.%d",
1497 etm
->bcd_vers
>> 4, etm
->bcd_vers
& 0xf);
1498 command_print(cmd_ctx
, "pairs of address comparators: %i",
1499 (etm
->config
>> 0) & 0x0f);
1500 command_print(cmd_ctx
, "data comparators: %i",
1501 (etm
->config
>> 4) & 0x0f);
1502 command_print(cmd_ctx
, "memory map decoders: %i",
1503 (etm
->config
>> 8) & 0x1f);
1504 command_print(cmd_ctx
, "number of counters: %i",
1505 (etm
->config
>> 13) & 0x07);
1506 command_print(cmd_ctx
, "sequencer %spresent",
1507 (etm
->config
& (1 << 16)) ? "" : "not ");
1508 command_print(cmd_ctx
, "number of ext. inputs: %i",
1509 (etm
->config
>> 17) & 0x07);
1510 command_print(cmd_ctx
, "number of ext. outputs: %i",
1511 (etm
->config
>> 20) & 0x07);
1512 command_print(cmd_ctx
, "FIFO full %spresent",
1513 (etm
->config
& (1 << 23)) ? "" : "not ");
1514 if (etm
->bcd_vers
< 0x20)
1515 command_print(cmd_ctx
, "protocol version: %i",
1516 (etm
->config
>> 28) & 0x07);
1518 command_print(cmd_ctx
, "trace start/stop %spresent",
1519 (etm
->config
& (1 << 26)) ? "" : "not ");
1520 command_print(cmd_ctx
, "number of context comparators: %i",
1521 (etm
->config
>> 24) & 0x03);
1524 /* SYS_CONFIG isn't present before ETMv1.2 */
1525 etm_sys_config_reg
= etm_reg_lookup(etm
, ETM_SYS_CONFIG
);
1526 if (!etm_sys_config_reg
)
1529 etm_get_reg(etm_sys_config_reg
);
1531 switch (buf_get_u32(etm_sys_config_reg
->value
, 0, 3))
1543 LOG_ERROR("Illegal max_port_size");
1546 command_print(cmd_ctx
, "max. port size: %i", max_port_size
);
1548 command_print(cmd_ctx
, "half-rate clocking %ssupported",
1549 (buf_get_u32(etm_sys_config_reg
->value
, 3, 1) == 1) ? "" : "not ");
1550 command_print(cmd_ctx
, "full-rate clocking %ssupported",
1551 (buf_get_u32(etm_sys_config_reg
->value
, 4, 1) == 1) ? "" : "not ");
1552 command_print(cmd_ctx
, "normal trace format %ssupported",
1553 (buf_get_u32(etm_sys_config_reg
->value
, 5, 1) == 1) ? "" : "not ");
1554 command_print(cmd_ctx
, "multiplex trace format %ssupported",
1555 (buf_get_u32(etm_sys_config_reg
->value
, 6, 1) == 1) ? "" : "not ");
1556 command_print(cmd_ctx
, "demultiplex trace format %ssupported",
1557 (buf_get_u32(etm_sys_config_reg
->value
, 7, 1) == 1) ? "" : "not ");
1558 command_print(cmd_ctx
, "FIFO full %ssupported",
1559 (buf_get_u32(etm_sys_config_reg
->value
, 8, 1) == 1) ? "" : "not ");
1564 static int handle_etm_status_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1567 armv4_5_common_t
*armv4_5
;
1568 arm7_9_common_t
*arm7_9
;
1569 trace_status_t trace_status
;
1571 target
= get_current_target(cmd_ctx
);
1573 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1575 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1579 if (!arm7_9
->etm_ctx
)
1581 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1585 trace_status
= arm7_9
->etm_ctx
->capture_driver
->status(arm7_9
->etm_ctx
);
1587 if (trace_status
== TRACE_IDLE
)
1589 command_print(cmd_ctx
, "tracing is idle");
1593 static char *completed
= " completed";
1594 static char *running
= " is running";
1595 static char *overflowed
= ", trace overflowed";
1596 static char *triggered
= ", trace triggered";
1598 command_print(cmd_ctx
, "trace collection%s%s%s",
1599 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1600 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1601 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1603 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1605 command_print(cmd_ctx
, "%i frames of trace data read", (int)(arm7_9
->etm_ctx
->trace_depth
));
1612 static int handle_etm_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1615 armv4_5_common_t
*armv4_5
;
1616 arm7_9_common_t
*arm7_9
;
1617 etm_context_t
*etm_ctx
;
1621 command_print(cmd_ctx
, "usage: etm image <file> [base address] [type]");
1625 target
= get_current_target(cmd_ctx
);
1627 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1629 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1633 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1635 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1641 image_close(etm_ctx
->image
);
1642 free(etm_ctx
->image
);
1643 command_print(cmd_ctx
, "previously loaded image found and closed");
1646 etm_ctx
->image
= malloc(sizeof(image_t
));
1647 etm_ctx
->image
->base_address_set
= 0;
1648 etm_ctx
->image
->start_address_set
= 0;
1650 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1653 etm_ctx
->image
->base_address_set
= 1;
1654 etm_ctx
->image
->base_address
= strtoul(args
[1], NULL
, 0);
1658 etm_ctx
->image
->base_address_set
= 0;
1661 if (image_open(etm_ctx
->image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
1663 free(etm_ctx
->image
);
1664 etm_ctx
->image
= NULL
;
1671 static int handle_etm_dump_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1675 armv4_5_common_t
*armv4_5
;
1676 arm7_9_common_t
*arm7_9
;
1677 etm_context_t
*etm_ctx
;
1682 command_print(cmd_ctx
, "usage: etm dump <file>");
1686 target
= get_current_target(cmd_ctx
);
1688 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1690 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1694 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1696 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1700 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
)
1702 command_print(cmd_ctx
, "trace capture wasn't enabled, no trace data captured");
1706 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1708 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1709 command_print(cmd_ctx
, "trace capture not completed");
1713 /* read the trace data if it wasn't read already */
1714 if (etm_ctx
->trace_depth
== 0)
1715 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1717 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1722 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1723 fileio_write_u32(&file
, etm_ctx
->portmode
);
1724 fileio_write_u32(&file
, etm_ctx
->tracemode
);
1725 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1727 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1729 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1730 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1731 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1734 fileio_close(&file
);
1739 static int handle_etm_load_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1743 armv4_5_common_t
*armv4_5
;
1744 arm7_9_common_t
*arm7_9
;
1745 etm_context_t
*etm_ctx
;
1750 command_print(cmd_ctx
, "usage: etm load <file>");
1754 target
= get_current_target(cmd_ctx
);
1756 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1758 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1762 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1764 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1768 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1770 command_print(cmd_ctx
, "trace capture running, stop first");
1774 if (fileio_open(&file
, args
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1781 command_print(cmd_ctx
, "size isn't a multiple of 4, no valid trace data");
1782 fileio_close(&file
);
1786 if (etm_ctx
->trace_depth
> 0)
1788 free(etm_ctx
->trace_data
);
1789 etm_ctx
->trace_data
= NULL
;
1794 fileio_read_u32(&file
, &tmp
); etm_ctx
->capture_status
= tmp
;
1795 fileio_read_u32(&file
, &tmp
); etm_ctx
->portmode
= tmp
;
1796 fileio_read_u32(&file
, &tmp
); etm_ctx
->tracemode
= tmp
;
1797 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1799 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
1800 if (etm_ctx
->trace_data
== NULL
)
1802 command_print(cmd_ctx
, "not enough memory to perform operation");
1803 fileio_close(&file
);
1807 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1809 uint32_t pipestat
, packet
, flags
;
1810 fileio_read_u32(&file
, &pipestat
);
1811 fileio_read_u32(&file
, &packet
);
1812 fileio_read_u32(&file
, &flags
);
1813 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1814 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1815 etm_ctx
->trace_data
[i
].flags
= flags
;
1818 fileio_close(&file
);
1823 static int handle_etm_trigger_percent_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1826 armv4_5_common_t
*armv4_5
;
1827 arm7_9_common_t
*arm7_9
;
1828 etm_context_t
*etm_ctx
;
1830 target
= get_current_target(cmd_ctx
);
1832 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1834 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1838 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1840 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1846 uint32_t new_value
= strtoul(args
[0], NULL
, 0);
1848 if ((new_value
< 2) || (new_value
> 100))
1850 command_print(cmd_ctx
, "valid settings are 2%% to 100%%");
1854 etm_ctx
->trigger_percent
= new_value
;
1858 command_print(cmd_ctx
, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx
->trigger_percent
)));
1863 static int handle_etm_start_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1866 armv4_5_common_t
*armv4_5
;
1867 arm7_9_common_t
*arm7_9
;
1868 etm_context_t
*etm_ctx
;
1869 reg_t
*etm_ctrl_reg
;
1871 target
= get_current_target(cmd_ctx
);
1873 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1875 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1879 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1881 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1885 /* invalidate old tracing data */
1886 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1887 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1889 free(arm7_9
->etm_ctx
->trace_data
);
1890 arm7_9
->etm_ctx
->trace_data
= NULL
;
1892 arm7_9
->etm_ctx
->trace_depth
= 0;
1894 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1898 etm_get_reg(etm_ctrl_reg
);
1900 /* Clear programming bit (10), set port selection bit (11) */
1901 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1903 etm_store_reg(etm_ctrl_reg
);
1904 jtag_execute_queue();
1906 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1911 static int handle_etm_stop_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1914 armv4_5_common_t
*armv4_5
;
1915 arm7_9_common_t
*arm7_9
;
1916 etm_context_t
*etm_ctx
;
1917 reg_t
*etm_ctrl_reg
;
1919 target
= get_current_target(cmd_ctx
);
1921 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1923 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1927 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1929 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1933 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1937 etm_get_reg(etm_ctrl_reg
);
1939 /* Set programming bit (10), clear port selection bit (11) */
1940 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
1942 etm_store_reg(etm_ctrl_reg
);
1943 jtag_execute_queue();
1945 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
1950 static int handle_etm_analyze_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1953 armv4_5_common_t
*armv4_5
;
1954 arm7_9_common_t
*arm7_9
;
1955 etm_context_t
*etm_ctx
;
1958 target
= get_current_target(cmd_ctx
);
1960 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1962 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1966 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1968 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1972 if ((retval
= etmv1_analyze_trace(etm_ctx
, cmd_ctx
)) != ERROR_OK
)
1976 case ERROR_ETM_ANALYSIS_FAILED
:
1977 command_print(cmd_ctx
, "further analysis failed (corrupted trace data or just end of data");
1979 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE
:
1980 command_print(cmd_ctx
, "no instruction for current address available, analysis aborted");
1982 case ERROR_TRACE_IMAGE_UNAVAILABLE
:
1983 command_print(cmd_ctx
, "no image available for trace analysis");
1986 command_print(cmd_ctx
, "unknown error: %i", retval
);
1993 int etm_register_commands(struct command_context_s
*cmd_ctx
)
1995 etm_cmd
= register_command(cmd_ctx
, NULL
, "etm", NULL
, COMMAND_ANY
, "Embedded Trace Macrocell");
1997 register_command(cmd_ctx
, etm_cmd
, "config", handle_etm_config_command
,
1998 COMMAND_CONFIG
, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2003 static int etm_register_user_commands(struct command_context_s
*cmd_ctx
)
2005 register_command(cmd_ctx
, etm_cmd
, "tracemode", handle_etm_tracemode_command
,
2006 COMMAND_EXEC
, "configure/display trace mode: "
2007 "<none | data | address | all> "
2008 "<context_id_bits> <cycle_accurate> <branch_output>");
2010 register_command(cmd_ctx
, etm_cmd
, "info", handle_etm_info_command
,
2011 COMMAND_EXEC
, "display info about the current target's ETM");
2013 register_command(cmd_ctx
, etm_cmd
, "trigger_percent", handle_etm_trigger_percent_command
,
2014 COMMAND_EXEC
, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2015 register_command(cmd_ctx
, etm_cmd
, "status", handle_etm_status_command
,
2016 COMMAND_EXEC
, "display current target's ETM status");
2017 register_command(cmd_ctx
, etm_cmd
, "start", handle_etm_start_command
,
2018 COMMAND_EXEC
, "start ETM trace collection");
2019 register_command(cmd_ctx
, etm_cmd
, "stop", handle_etm_stop_command
,
2020 COMMAND_EXEC
, "stop ETM trace collection");
2022 register_command(cmd_ctx
, etm_cmd
, "analyze", handle_etm_analyze_command
,
2023 COMMAND_EXEC
, "anaylze collected ETM trace");
2025 register_command(cmd_ctx
, etm_cmd
, "image", handle_etm_image_command
,
2026 COMMAND_EXEC
, "load image from <file> [base address]");
2028 register_command(cmd_ctx
, etm_cmd
, "dump", handle_etm_dump_command
,
2029 COMMAND_EXEC
, "dump captured trace data <file>");
2030 register_command(cmd_ctx
, etm_cmd
, "load", handle_etm_load_command
,
2031 COMMAND_EXEC
, "load trace data for analysis <file>");
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)