1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
28 #include "arm_disassembler.h"
30 #include "etm_dummy.h"
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
67 uint8_t size
; /* low-N of 32 bits */
68 uint8_t mode
; /* RO, WO, RW */
69 uint8_t bcd_vers
; /* 1.0, 2.0, etc */
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core
[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG
, 32, RO
, 0x10, "ETM_config", },
84 { ETM_ID
, 32, RO
, 0x20, "ETM_id", },
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic
[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL
, 32, RW
, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT
, 17, WO
, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL
, 8, WO
, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS
, 3, RO
, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG
, 9, RO
, 0x12, "ETM_sys_config", },
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL
, 32, WO
, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2
, 16, WO
, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT
, 17, WO
, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1
, 26, WO
, 0x10, "ETM_trace_en_ctrl1", },
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT
, 17, WO
, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1
, 32, WO
, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2
, 32, WO
, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3
, 17, WO
, 0x10, "ETM_viewdata_ctrl3", },
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
110 { 0x78, 12, WO
, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO
, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO
, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO
, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO
, 0x34, "ETM_behavior_control", },
117 static const struct etm_reg_info etm_fifofull
[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION
, 25, WO
, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL
, 8, WO
, 0x10, "ETM_fifofull_level", },
123 static const struct etm_reg_info etm_addr_comp
[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
147 #undef ADDR_COMPARATOR
150 static const struct etm_reg_info etm_data_comp
[] = {
151 /* Data Value Comparators (NOTE: odd addresses are reserved) */
152 #define DATA_COMPARATOR(i) \
153 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
154 "ETM_data_" #i "_comparator_value", }, \
155 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
156 "ETM_data_" #i "_comparator_mask", }
165 #undef DATA_COMPARATOR
168 static const struct etm_reg_info etm_counters
[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
185 static const struct etm_reg_info etm_sequencer
[] = {
187 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
188 "ETM_sequencer_event" #i, }
189 ETM_SEQ(0), /* 1->2 */
190 ETM_SEQ(1), /* 2->1 */
191 ETM_SEQ(2), /* 2->3 */
192 ETM_SEQ(3), /* 3->1 */
193 ETM_SEQ(4), /* 3->2 */
194 ETM_SEQ(5), /* 1->3 */
197 { ETM_SEQUENCER_STATE
, 2, RO
, 0x10, "ETM_sequencer_state", },
200 static const struct etm_reg_info etm_outputs
[] = {
201 #define ETM_OUTPUT(i) \
202 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
203 "ETM_external_output" #i, }
213 /* registers from 0x6c..0x7f were added after ETMv1.3 */
215 /* Context ID Comparators */
216 { 0x6c, 32, RO
, 0x20, "ETM_contextid_comparator_value1", }
217 { 0x6d, 32, RO
, 0x20, "ETM_contextid_comparator_value2", }
218 { 0x6e, 32, RO
, 0x20, "ETM_contextid_comparator_value3", }
219 { 0x6f, 32, RO
, 0x20, "ETM_contextid_comparator_mask", }
222 static int etm_get_reg(struct reg
*reg
);
223 static int etm_read_reg_w_check(struct reg
*reg
,
224 uint8_t* check_value
, uint8_t* check_mask
);
225 static int etm_register_user_commands(struct command_context
*cmd_ctx
);
226 static int etm_set_reg_w_exec(struct reg
*reg
, uint8_t *buf
);
227 static int etm_write_reg(struct reg
*reg
, uint32_t value
);
229 static const struct reg_arch_type etm_scan6_type
= {
231 .set
= etm_set_reg_w_exec
,
234 /* Look up register by ID ... most ETM instances only
235 * support a subset of the possible registers.
237 static struct reg
*etm_reg_lookup(struct etm_context
*etm_ctx
, unsigned id
)
239 struct reg_cache
*cache
= etm_ctx
->reg_cache
;
242 for (i
= 0; i
< cache
->num_regs
; i
++) {
243 struct etm_reg
*reg
= cache
->reg_list
[i
].arch_info
;
245 if (reg
->reg_info
->addr
== id
)
246 return &cache
->reg_list
[i
];
249 /* caller asking for nonexistent register is a bug! */
250 /* REVISIT say which of the N targets was involved */
251 LOG_ERROR("ETM: register 0x%02x not available", id
);
255 static void etm_reg_add(unsigned bcd_vers
, struct arm_jtag
*jtag_info
,
256 struct reg_cache
*cache
, struct etm_reg
*ereg
,
257 const struct etm_reg_info
*r
, unsigned nreg
)
259 struct reg
*reg
= cache
->reg_list
;
261 reg
+= cache
->num_regs
;
262 ereg
+= cache
->num_regs
;
264 /* add up to "nreg" registers from "r", if supported by this
265 * version of the ETM, to the specified cache.
267 for (; nreg
--; r
++) {
269 /* this ETM may be too old to have some registers */
270 if (r
->bcd_vers
> bcd_vers
)
275 reg
->value
= &ereg
->value
;
276 reg
->arch_info
= ereg
;
277 reg
->type
= &etm_scan6_type
;
282 ereg
->jtag_info
= jtag_info
;
287 struct reg_cache
*etm_build_reg_cache(struct target
*target
,
288 struct arm_jtag
*jtag_info
, struct etm_context
*etm_ctx
)
290 struct reg_cache
*reg_cache
= malloc(sizeof(struct reg_cache
));
291 struct reg
*reg_list
= NULL
;
292 struct etm_reg
*arch_info
= NULL
;
293 unsigned bcd_vers
, config
;
295 /* the actual registers are kept in two arrays */
296 reg_list
= calloc(128, sizeof(struct reg
));
297 arch_info
= calloc(128, sizeof(struct etm_reg
));
299 /* fill in values for the reg cache */
300 reg_cache
->name
= "etm registers";
301 reg_cache
->next
= NULL
;
302 reg_cache
->reg_list
= reg_list
;
303 reg_cache
->num_regs
= 0;
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
308 etm_reg_add(0x10, jtag_info
, reg_cache
, arch_info
,
311 etm_get_reg(reg_list
);
312 etm_ctx
->config
= buf_get_u32((void *)&arch_info
->value
, 0, 32);
313 config
= etm_ctx
->config
;
315 /* figure ETM version then add base registers */
316 if (config
& (1 << 31)) {
317 LOG_WARNING("ETMv2+ support is incomplete");
319 /* REVISIT more registers may exist; they may now be
320 * readable; more register bits have defined meanings;
321 * don't presume trace start/stop support is present;
322 * and include any context ID comparator registers.
324 etm_reg_add(0x20, jtag_info
, reg_cache
, arch_info
,
326 etm_get_reg(reg_list
+ 1);
327 etm_ctx
->id
= buf_get_u32(
328 (void *)&arch_info
[1].value
, 0, 32);
329 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx
->id
);
330 bcd_vers
= 0x10 + (((etm_ctx
->id
) >> 4) & 0xff);
333 switch (config
>> 28) {
350 LOG_WARNING("Bad ETMv1 protocol %d", config
>> 28);
354 etm_ctx
->bcd_vers
= bcd_vers
;
355 LOG_INFO("ETM v%d.%d", bcd_vers
>> 4, bcd_vers
& 0xf);
357 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
358 etm_basic
, ARRAY_SIZE(etm_basic
));
360 /* address and data comparators; counters; outputs */
361 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
362 etm_addr_comp
, 4 * (0x0f & (config
>> 0)));
363 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
364 etm_data_comp
, 2 * (0x0f & (config
>> 4)));
365 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
366 etm_counters
, 4 * (0x07 & (config
>> 13)));
367 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
368 etm_outputs
, (0x07 & (config
>> 20)));
370 /* FIFOFULL presence is optional
371 * REVISIT for ETMv1.2 and later, don't bother adding this
372 * unless ETM_SYS_CONFIG says it's also *supported* ...
374 if (config
& (1 << 23))
375 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
376 etm_fifofull
, ARRAY_SIZE(etm_fifofull
));
378 /* sequencer is optional (for state-dependant triggering) */
379 if (config
& (1 << 16))
380 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
381 etm_sequencer
, ARRAY_SIZE(etm_sequencer
));
383 /* REVISIT could realloc and likely save half the memory
384 * in the two chunks we allocated...
387 /* the ETM might have an ETB connected */
388 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0)
390 struct etb
*etb
= etm_ctx
->capture_driver_priv
;
394 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
398 reg_cache
->next
= etb_build_reg_cache(etb
);
400 etb
->reg_cache
= reg_cache
->next
;
403 etm_ctx
->reg_cache
= reg_cache
;
413 static int etm_read_reg(struct reg
*reg
)
415 return etm_read_reg_w_check(reg
, NULL
, NULL
);
418 static int etm_store_reg(struct reg
*reg
)
420 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
423 int etm_setup(struct target
*target
)
426 uint32_t etm_ctrl_value
;
427 struct arm
*arm
= target_to_arm(target
);
428 struct etm_context
*etm_ctx
= arm
->etm
;
429 struct reg
*etm_ctrl_reg
;
431 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
435 /* initialize some ETM control register settings */
436 etm_get_reg(etm_ctrl_reg
);
437 etm_ctrl_value
= buf_get_u32(etm_ctrl_reg
->value
, 0, 32);
439 /* clear the ETM powerdown bit (0) */
440 etm_ctrl_value
&= ~ETM_CTRL_POWERDOWN
;
442 /* configure port width (21,6:4), mode (13,17:16) and
443 * for older modules clocking (13)
445 etm_ctrl_value
= (etm_ctrl_value
446 & ~ETM_PORT_WIDTH_MASK
447 & ~ETM_PORT_MODE_MASK
449 & ~ETM_PORT_CLOCK_MASK
)
452 buf_set_u32(etm_ctrl_reg
->value
, 0, 32, etm_ctrl_value
);
453 etm_store_reg(etm_ctrl_reg
);
455 etm_ctx
->control
= etm_ctrl_value
;
457 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
460 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
461 * verify that those width and mode settings are OK ...
464 if ((retval
= etm_ctx
->capture_driver
->init(etm_ctx
)) != ERROR_OK
)
466 LOG_ERROR("ETM capture driver initialization failed");
472 static int etm_get_reg(struct reg
*reg
)
476 if ((retval
= etm_read_reg(reg
)) != ERROR_OK
)
478 LOG_ERROR("BUG: error scheduling etm register read");
482 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
484 LOG_ERROR("register read failed");
491 static int etm_read_reg_w_check(struct reg
*reg
,
492 uint8_t* check_value
, uint8_t* check_mask
)
494 struct etm_reg
*etm_reg
= reg
->arch_info
;
495 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
496 uint8_t reg_addr
= r
->addr
& 0x7f;
497 struct scan_field fields
[3];
500 if (etm_reg
->reg_info
->mode
== WO
) {
501 LOG_ERROR("BUG: can't read write-only register %s", r
->name
);
502 return ERROR_COMMAND_SYNTAX_ERROR
;
505 LOG_DEBUG("%s (%u)", r
->name
, reg_addr
);
507 retval
= arm_jtag_scann(etm_reg
->jtag_info
, 0x6, TAP_IDLE
);
508 if (retval
!= ERROR_OK
)
510 retval
= arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
511 if (retval
!= ERROR_OK
)
514 fields
[0].num_bits
= 32;
515 fields
[0].out_value
= reg
->value
;
516 fields
[0].in_value
= NULL
;
517 fields
[0].check_value
= NULL
;
518 fields
[0].check_mask
= NULL
;
520 fields
[1].num_bits
= 7;
522 fields
[1].out_value
= &temp1
;
523 buf_set_u32(&temp1
, 0, 7, reg_addr
);
524 fields
[1].in_value
= NULL
;
525 fields
[1].check_value
= NULL
;
526 fields
[1].check_mask
= NULL
;
528 fields
[2].num_bits
= 1;
530 fields
[2].out_value
= &temp2
;
531 buf_set_u32(&temp2
, 0, 1, 0);
532 fields
[2].in_value
= NULL
;
533 fields
[2].check_value
= NULL
;
534 fields
[2].check_mask
= NULL
;
536 jtag_add_dr_scan(etm_reg
->jtag_info
->tap
, 3, fields
, TAP_IDLE
);
538 fields
[0].in_value
= reg
->value
;
539 fields
[0].check_value
= check_value
;
540 fields
[0].check_mask
= check_mask
;
542 jtag_add_dr_scan_check(etm_reg
->jtag_info
->tap
, 3, fields
, TAP_IDLE
);
547 static int etm_set_reg(struct reg
*reg
, uint32_t value
)
551 if ((retval
= etm_write_reg(reg
, value
)) != ERROR_OK
)
553 LOG_ERROR("BUG: error scheduling etm register write");
557 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
564 static int etm_set_reg_w_exec(struct reg
*reg
, uint8_t *buf
)
568 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
570 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
572 LOG_ERROR("register write failed");
578 static int etm_write_reg(struct reg
*reg
, uint32_t value
)
580 struct etm_reg
*etm_reg
= reg
->arch_info
;
581 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
582 uint8_t reg_addr
= r
->addr
& 0x7f;
583 struct scan_field fields
[3];
586 if (etm_reg
->reg_info
->mode
== RO
) {
587 LOG_ERROR("BUG: can't write read--only register %s", r
->name
);
588 return ERROR_COMMAND_SYNTAX_ERROR
;
591 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32
"", r
->name
, reg_addr
, value
);
593 retval
= arm_jtag_scann(etm_reg
->jtag_info
, 0x6, TAP_IDLE
);
594 if (retval
!= ERROR_OK
)
596 retval
= arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
597 if (retval
!= ERROR_OK
)
600 fields
[0].num_bits
= 32;
602 fields
[0].out_value
= tmp1
;
603 buf_set_u32(tmp1
, 0, 32, value
);
604 fields
[0].in_value
= NULL
;
606 fields
[1].num_bits
= 7;
608 fields
[1].out_value
= &tmp2
;
609 buf_set_u32(&tmp2
, 0, 7, reg_addr
);
610 fields
[1].in_value
= NULL
;
612 fields
[2].num_bits
= 1;
614 fields
[2].out_value
= &tmp3
;
615 buf_set_u32(&tmp3
, 0, 1, 1);
616 fields
[2].in_value
= NULL
;
618 jtag_add_dr_scan(etm_reg
->jtag_info
->tap
, 3, fields
, TAP_IDLE
);
624 /* ETM trace analysis functionality */
626 static struct etm_capture_driver
*etm_capture_drivers
[] =
629 &etm_dummy_capture_driver
,
630 #if BUILD_OOCD_TRACE == 1
631 &oocd_trace_capture_driver
,
636 static int etm_read_instruction(struct etm_context
*ctx
, struct arm_instruction
*instruction
)
645 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
647 /* search for the section the current instruction belongs to */
648 for (i
= 0; i
< ctx
->image
->num_sections
; i
++)
650 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
651 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
> ctx
->current_pc
))
660 /* current instruction couldn't be found in the image */
661 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
664 if (ctx
->core_state
== ARM_STATE_ARM
)
667 if ((retval
= image_read_section(ctx
->image
, section
,
668 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
669 4, buf
, &size_read
)) != ERROR_OK
)
671 LOG_ERROR("error while reading instruction");
672 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
674 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
675 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
677 else if (ctx
->core_state
== ARM_STATE_THUMB
)
680 if ((retval
= image_read_section(ctx
->image
, section
,
681 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
682 2, buf
, &size_read
)) != ERROR_OK
)
684 LOG_ERROR("error while reading instruction");
685 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
687 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
688 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
690 else if (ctx
->core_state
== ARM_STATE_JAZELLE
)
692 LOG_ERROR("BUG: tracing of jazelle code not supported");
697 LOG_ERROR("BUG: unknown core state encountered");
704 static int etmv1_next_packet(struct etm_context
*ctx
, uint8_t *packet
, int apo
)
706 while (ctx
->data_index
< ctx
->trace_depth
)
708 /* if the caller specified an address packet offset, skip until the
709 * we reach the n-th cycle marked with tracesync */
712 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
723 /* no tracedata output during a TD cycle
724 * or in a trigger cycle */
725 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
726 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
))
733 /* FIXME there are more port widths than these... */
734 if ((ctx
->control
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
)
736 if (ctx
->data_half
== 0)
738 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
743 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
748 else if ((ctx
->control
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
750 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
755 /* on a 4-bit port, a packet will be output during two consecutive cycles */
756 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
759 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
760 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
761 ctx
->data_index
+= 2;
770 static int etmv1_branch_address(struct etm_context
*ctx
)
778 /* quit analysis if less than two cycles are left in the trace
779 * because we can't extract the APO */
780 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
783 /* a BE could be output during an APO cycle, skip the current
784 * and continue with the new one */
785 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
787 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
790 /* address packet offset encoded in the next two cycles' pipestat bits */
791 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
792 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
794 /* count number of tracesync cycles between current pipe_index and data_index
795 * i.e. the number of tracesyncs that data_index already passed by
796 * to subtract them from the APO */
797 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++)
799 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
803 /* extract up to four 7-bit packets */
805 if ((retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0)) != 0)
807 ctx
->last_branch
&= ~(0x7f << shift
);
808 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
810 } while ((packet
& 0x80) && (shift
< 28));
812 /* one last packet holding 4 bits of the address, plus the branch reason code */
813 if ((shift
== 28) && (packet
& 0x80))
815 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
817 ctx
->last_branch
&= 0x0fffffff;
818 ctx
->last_branch
|= (packet
& 0x0f) << 28;
819 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
824 ctx
->last_branch_reason
= 0;
832 /* if a full address was output, we might have branched into Jazelle state */
833 if ((shift
== 32) && (packet
& 0x80))
835 ctx
->core_state
= ARM_STATE_JAZELLE
;
839 /* if we didn't branch into Jazelle state, the current processor state is
840 * encoded in bit 0 of the branch target address */
841 if (ctx
->last_branch
& 0x1)
843 ctx
->core_state
= ARM_STATE_THUMB
;
844 ctx
->last_branch
&= ~0x1;
848 ctx
->core_state
= ARM_STATE_ARM
;
849 ctx
->last_branch
&= ~0x3;
856 static int etmv1_data(struct etm_context
*ctx
, int size
, uint32_t *data
)
862 for (j
= 0; j
< size
; j
++)
864 if ((retval
= etmv1_next_packet(ctx
, &buf
[j
], 0)) != 0)
870 LOG_ERROR("TODO: add support for 64-bit values");
874 *data
= target_buffer_get_u32(ctx
->target
, buf
);
876 *data
= target_buffer_get_u16(ctx
->target
, buf
);
885 static int etmv1_analyze_trace(struct etm_context
*ctx
, struct command_context
*cmd_ctx
)
888 struct arm_instruction instruction
;
890 /* read the trace data if it wasn't read already */
891 if (ctx
->trace_depth
== 0)
892 ctx
->capture_driver
->read_trace(ctx
);
894 if (ctx
->trace_depth
== 0) {
895 command_print(cmd_ctx
, "Trace is empty.");
899 /* start at the beginning of the captured trace */
904 /* neither the PC nor the data pointer are valid */
908 while (ctx
->pipe_index
< ctx
->trace_depth
)
910 uint8_t pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
911 uint32_t next_pc
= ctx
->current_pc
;
912 uint32_t old_data_index
= ctx
->data_index
;
913 uint32_t old_data_half
= ctx
->data_half
;
914 uint32_t old_index
= ctx
->pipe_index
;
915 uint32_t last_instruction
= ctx
->last_instruction
;
917 int current_pc_ok
= ctx
->pc_ok
;
919 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
921 command_print(cmd_ctx
, "--- trigger ---");
924 /* instructions execute in IE/D or BE/D cycles */
925 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
926 ctx
->last_instruction
= ctx
->pipe_index
;
928 /* if we don't have a valid pc skip until we reach an indirect branch */
929 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
))
935 /* any indirect branch could have interrupted instruction flow
936 * - the branch reason code could indicate a trace discontinuity
937 * - a branch to the exception vectors indicates an exception
939 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
))
941 /* backup current data index, to be able to consume the branch address
942 * before examining data address and values
944 old_data_index
= ctx
->data_index
;
945 old_data_half
= ctx
->data_half
;
947 ctx
->last_instruction
= ctx
->pipe_index
;
949 if ((retval
= etmv1_branch_address(ctx
)) != 0)
951 /* negative return value from etmv1_branch_address means we ran out of packets,
952 * quit analysing the trace */
956 /* a positive return values means the current branch was abandoned,
957 * and a new branch was encountered in cycle ctx->pipe_index + retval;
959 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
960 ctx
->pipe_index
+= retval
;
964 /* skip over APO cycles */
965 ctx
->pipe_index
+= 2;
967 switch (ctx
->last_branch_reason
)
969 case 0x0: /* normal PC change */
970 next_pc
= ctx
->last_branch
;
972 case 0x1: /* tracing enabled */
973 command_print(cmd_ctx
, "--- tracing enabled at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
974 ctx
->current_pc
= ctx
->last_branch
;
978 case 0x2: /* trace restarted after FIFO overflow */
979 command_print(cmd_ctx
, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
980 ctx
->current_pc
= ctx
->last_branch
;
984 case 0x3: /* exit from debug state */
985 command_print(cmd_ctx
, "--- exit from debug state at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
986 ctx
->current_pc
= ctx
->last_branch
;
990 case 0x4: /* periodic synchronization point */
991 next_pc
= ctx
->last_branch
;
992 /* if we had no valid PC prior to this synchronization point,
993 * we have to move on with the next trace cycle
997 command_print(cmd_ctx
, "--- periodic synchronization point at 0x%8.8" PRIx32
" ---", next_pc
);
998 ctx
->current_pc
= next_pc
;
1003 default: /* reserved */
1004 LOG_ERROR("BUG: branch reason code 0x%" PRIx32
" is reserved", ctx
->last_branch_reason
);
1008 /* if we got here the branch was a normal PC change
1009 * (or a periodic synchronization point, which means the same for that matter)
1010 * if we didn't accquire a complete PC continue with the next cycle
1015 /* indirect branch to the exception vector means an exception occured */
1016 if ((ctx
->last_branch
<= 0x20)
1017 || ((ctx
->last_branch
>= 0xffff0000) && (ctx
->last_branch
<= 0xffff0020)))
1019 if ((ctx
->last_branch
& 0xff) == 0x10)
1021 command_print(cmd_ctx
, "data abort");
1025 command_print(cmd_ctx
, "exception vector 0x%2.2" PRIx32
"", ctx
->last_branch
);
1026 ctx
->current_pc
= ctx
->last_branch
;
1033 /* an instruction was executed (or not, depending on the condition flags)
1034 * retrieve it from the image for displaying */
1035 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
1036 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
1037 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4))))
1039 if ((retval
= etm_read_instruction(ctx
, &instruction
)) != ERROR_OK
)
1041 /* can't continue tracing with no image available */
1042 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
1046 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
1048 /* TODO: handle incomplete images
1049 * for now we just quit the analsysis*/
1054 cycles
= old_index
- last_instruction
;
1057 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
))
1059 uint32_t new_data_index
= ctx
->data_index
;
1060 uint32_t new_data_half
= ctx
->data_half
;
1062 /* in case of a branch with data, the branch target address was consumed before
1063 * we temporarily go back to the saved data index */
1064 if (pipestat
== STAT_BD
)
1066 ctx
->data_index
= old_data_index
;
1067 ctx
->data_half
= old_data_half
;
1070 if (ctx
->control
& ETM_CTRL_TRACE_ADDR
)
1076 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
1077 return ERROR_ETM_ANALYSIS_FAILED
;
1078 ctx
->last_ptr
&= ~(0x7f << shift
);
1079 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
1081 } while ((packet
& 0x80) && (shift
< 32));
1088 command_print(cmd_ctx
, "address: 0x%8.8" PRIx32
"", ctx
->last_ptr
);
1092 if (ctx
->control
& ETM_CTRL_TRACE_DATA
)
1094 if ((instruction
.type
== ARM_LDM
) || (instruction
.type
== ARM_STM
))
1097 for (i
= 0; i
< 16; i
++)
1099 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
1102 if (etmv1_data(ctx
, 4, &data
) != 0)
1103 return ERROR_ETM_ANALYSIS_FAILED
;
1104 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1108 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_STRH
))
1111 if (etmv1_data(ctx
, arm_access_size(&instruction
), &data
) != 0)
1112 return ERROR_ETM_ANALYSIS_FAILED
;
1113 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1117 /* restore data index after consuming BD address and data */
1118 if (pipestat
== STAT_BD
)
1120 ctx
->data_index
= new_data_index
;
1121 ctx
->data_half
= new_data_half
;
1126 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
1128 if (((instruction
.type
== ARM_B
) ||
1129 (instruction
.type
== ARM_BL
) ||
1130 (instruction
.type
== ARM_BLX
)) &&
1131 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff))
1133 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
1137 next_pc
+= (ctx
->core_state
== ARM_STATE_ARM
) ? 4 : 2;
1140 else if (pipestat
== STAT_IN
)
1142 next_pc
+= (ctx
->core_state
== ARM_STATE_ARM
) ? 4 : 2;
1145 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
))
1147 char cycles_text
[32] = "";
1149 /* if the trace was captured with cycle accurate tracing enabled,
1150 * output the number of cycles since the last executed instruction
1152 if (ctx
->control
& ETM_CTRL_CYCLE_ACCURATE
)
1154 snprintf(cycles_text
, 32, " (%i %s)",
1156 (cycles
== 1) ? "cycle" : "cycles");
1159 command_print(cmd_ctx
, "%s%s%s",
1161 (pipestat
== STAT_IN
) ? " (not executed)" : "",
1164 ctx
->current_pc
= next_pc
;
1166 /* packets for an instruction don't start on or before the preceding
1167 * functional pipestat (i.e. other than WT or TD)
1169 if (ctx
->data_index
<= ctx
->pipe_index
)
1171 ctx
->data_index
= ctx
->pipe_index
+ 1;
1176 ctx
->pipe_index
+= 1;
1182 static COMMAND_HELPER(handle_etm_tracemode_command_update
,
1187 /* what parts of data access are traced? */
1188 if (strcmp(CMD_ARGV
[0], "none") == 0)
1190 else if (strcmp(CMD_ARGV
[0], "data") == 0)
1191 tracemode
= ETM_CTRL_TRACE_DATA
;
1192 else if (strcmp(CMD_ARGV
[0], "address") == 0)
1193 tracemode
= ETM_CTRL_TRACE_ADDR
;
1194 else if (strcmp(CMD_ARGV
[0], "all") == 0)
1195 tracemode
= ETM_CTRL_TRACE_DATA
| ETM_CTRL_TRACE_ADDR
;
1198 command_print(CMD_CTX
, "invalid option '%s'", CMD_ARGV
[0]);
1199 return ERROR_COMMAND_SYNTAX_ERROR
;
1203 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[1], context_id
);
1207 tracemode
|= ETM_CTRL_CONTEXTID_NONE
;
1210 tracemode
|= ETM_CTRL_CONTEXTID_8
;
1213 tracemode
|= ETM_CTRL_CONTEXTID_16
;
1216 tracemode
|= ETM_CTRL_CONTEXTID_32
;
1219 command_print(CMD_CTX
, "invalid option '%s'", CMD_ARGV
[1]);
1220 return ERROR_COMMAND_SYNTAX_ERROR
;
1223 bool etmv1_cycle_accurate
;
1224 COMMAND_PARSE_ENABLE(CMD_ARGV
[2], etmv1_cycle_accurate
);
1225 if (etmv1_cycle_accurate
)
1226 tracemode
|= ETM_CTRL_CYCLE_ACCURATE
;
1228 bool etmv1_branch_output
;
1229 COMMAND_PARSE_ENABLE(CMD_ARGV
[3], etmv1_branch_output
);
1230 if (etmv1_branch_output
)
1231 tracemode
|= ETM_CTRL_BRANCH_OUTPUT
;
1234 * - CPRT tracing (coprocessor register transfers)
1235 * - debug request (causes debug entry on trigger)
1236 * - stall on FIFOFULL (preventing tracedata lossage)
1243 COMMAND_HANDLER(handle_etm_tracemode_command
)
1245 struct target
*target
= get_current_target(CMD_CTX
);
1246 struct arm
*arm
= target_to_arm(target
);
1247 struct etm_context
*etm
;
1250 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1256 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1260 uint32_t tracemode
= etm
->control
;
1267 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update
,
1271 return ERROR_COMMAND_SYNTAX_ERROR
;
1275 * todo: fail if parameters were invalid for this hardware,
1276 * or couldn't be written; display actual hardware state...
1279 command_print(CMD_CTX
, "current tracemode configuration:");
1281 switch (tracemode
& ETM_CTRL_TRACE_MASK
)
1284 command_print(CMD_CTX
, "data tracing: none");
1286 case ETM_CTRL_TRACE_DATA
:
1287 command_print(CMD_CTX
, "data tracing: data only");
1289 case ETM_CTRL_TRACE_ADDR
:
1290 command_print(CMD_CTX
, "data tracing: address only");
1292 case ETM_CTRL_TRACE_DATA
| ETM_CTRL_TRACE_ADDR
:
1293 command_print(CMD_CTX
, "data tracing: address and data");
1297 switch (tracemode
& ETM_CTRL_CONTEXTID_MASK
)
1299 case ETM_CTRL_CONTEXTID_NONE
:
1300 command_print(CMD_CTX
, "contextid tracing: none");
1302 case ETM_CTRL_CONTEXTID_8
:
1303 command_print(CMD_CTX
, "contextid tracing: 8 bit");
1305 case ETM_CTRL_CONTEXTID_16
:
1306 command_print(CMD_CTX
, "contextid tracing: 16 bit");
1308 case ETM_CTRL_CONTEXTID_32
:
1309 command_print(CMD_CTX
, "contextid tracing: 32 bit");
1313 if (tracemode
& ETM_CTRL_CYCLE_ACCURATE
)
1315 command_print(CMD_CTX
, "cycle-accurate tracing enabled");
1319 command_print(CMD_CTX
, "cycle-accurate tracing disabled");
1322 if (tracemode
& ETM_CTRL_BRANCH_OUTPUT
)
1324 command_print(CMD_CTX
, "full branch address output enabled");
1328 command_print(CMD_CTX
, "full branch address output disabled");
1331 #define TRACEMODE_MASK ( \
1332 ETM_CTRL_CONTEXTID_MASK \
1333 | ETM_CTRL_BRANCH_OUTPUT \
1334 | ETM_CTRL_CYCLE_ACCURATE \
1335 | ETM_CTRL_TRACE_MASK \
1338 /* only update ETM_CTRL register if tracemode changed */
1339 if ((etm
->control
& TRACEMODE_MASK
) != tracemode
)
1341 struct reg
*etm_ctrl_reg
;
1343 etm_ctrl_reg
= etm_reg_lookup(etm
, ETM_CTRL
);
1347 etm
->control
&= ~TRACEMODE_MASK
;
1348 etm
->control
|= tracemode
& TRACEMODE_MASK
;
1350 buf_set_u32(etm_ctrl_reg
->value
, 0, 32, etm
->control
);
1351 etm_store_reg(etm_ctrl_reg
);
1353 /* invalidate old trace data */
1354 etm
->capture_status
= TRACE_IDLE
;
1355 if (etm
->trace_depth
> 0)
1357 free(etm
->trace_data
);
1358 etm
->trace_data
= NULL
;
1360 etm
->trace_depth
= 0;
1363 #undef TRACEMODE_MASK
1368 COMMAND_HANDLER(handle_etm_config_command
)
1370 struct target
*target
;
1372 uint32_t portmode
= 0x0;
1373 struct etm_context
*etm_ctx
;
1377 return ERROR_COMMAND_SYNTAX_ERROR
;
1379 target
= get_target(CMD_ARGV
[0]);
1382 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
1386 arm
= target_to_arm(target
);
1388 command_print(CMD_CTX
, "target '%s' is '%s'; not an ARM",
1389 target_name(target
),
1390 target_type_name(target
));
1394 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1395 * version we'll be using!! -- so we can't know how to validate
1396 * params yet. "etm config" should likely be *AFTER* hookup...
1398 * - Many more widths might be supported ... and we can easily
1399 * check whether our setting "took".
1401 * - The "clock" and "mode" bits are interpreted differently.
1402 * See ARM IHI 0014O table 2-17 for the old behavior, and
1403 * table 2-18 for the new. With ETB it's best to specify
1407 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[1], port_width
);
1410 /* before ETMv3.0 */
1412 portmode
|= ETM_PORT_4BIT
;
1415 portmode
|= ETM_PORT_8BIT
;
1418 portmode
|= ETM_PORT_16BIT
;
1420 /* ETMv3.0 and later*/
1422 portmode
|= ETM_PORT_24BIT
;
1425 portmode
|= ETM_PORT_32BIT
;
1428 portmode
|= ETM_PORT_48BIT
;
1431 portmode
|= ETM_PORT_64BIT
;
1434 portmode
|= ETM_PORT_1BIT
;
1437 portmode
|= ETM_PORT_2BIT
;
1440 command_print(CMD_CTX
,
1441 "unsupported ETM port width '%s'", CMD_ARGV
[1]);
1445 if (strcmp("normal", CMD_ARGV
[2]) == 0)
1447 portmode
|= ETM_PORT_NORMAL
;
1449 else if (strcmp("multiplexed", CMD_ARGV
[2]) == 0)
1451 portmode
|= ETM_PORT_MUXED
;
1453 else if (strcmp("demultiplexed", CMD_ARGV
[2]) == 0)
1455 portmode
|= ETM_PORT_DEMUXED
;
1459 command_print(CMD_CTX
, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV
[2]);
1463 if (strcmp("half", CMD_ARGV
[3]) == 0)
1465 portmode
|= ETM_PORT_HALF_CLOCK
;
1467 else if (strcmp("full", CMD_ARGV
[3]) == 0)
1469 portmode
|= ETM_PORT_FULL_CLOCK
;
1473 command_print(CMD_CTX
, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV
[3]);
1477 etm_ctx
= calloc(1, sizeof(struct etm_context
));
1479 LOG_DEBUG("out of memory");
1483 for (i
= 0; etm_capture_drivers
[i
]; i
++)
1485 if (strcmp(CMD_ARGV
[4], etm_capture_drivers
[i
]->name
) == 0)
1487 int retval
= register_commands(CMD_CTX
, NULL
,
1488 etm_capture_drivers
[i
]->commands
);
1489 if (ERROR_OK
!= retval
)
1495 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1501 if (!etm_capture_drivers
[i
])
1503 /* no supported capture driver found, don't register an ETM */
1505 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV
[4]);
1509 etm_ctx
->target
= target
;
1510 etm_ctx
->trace_data
= NULL
;
1511 etm_ctx
->control
= portmode
;
1512 etm_ctx
->core_state
= ARM_STATE_ARM
;
1516 return etm_register_user_commands(CMD_CTX
);
1519 COMMAND_HANDLER(handle_etm_info_command
)
1521 struct target
*target
;
1523 struct etm_context
*etm
;
1524 struct reg
*etm_sys_config_reg
;
1528 target
= get_current_target(CMD_CTX
);
1529 arm
= target_to_arm(target
);
1532 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1539 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1543 command_print(CMD_CTX
, "ETM v%d.%d",
1544 etm
->bcd_vers
>> 4, etm
->bcd_vers
& 0xf);
1545 command_print(CMD_CTX
, "pairs of address comparators: %i",
1546 (int) (etm
->config
>> 0) & 0x0f);
1547 command_print(CMD_CTX
, "data comparators: %i",
1548 (int) (etm
->config
>> 4) & 0x0f);
1549 command_print(CMD_CTX
, "memory map decoders: %i",
1550 (int) (etm
->config
>> 8) & 0x1f);
1551 command_print(CMD_CTX
, "number of counters: %i",
1552 (int) (etm
->config
>> 13) & 0x07);
1553 command_print(CMD_CTX
, "sequencer %spresent",
1554 (int) (etm
->config
& (1 << 16)) ? "" : "not ");
1555 command_print(CMD_CTX
, "number of ext. inputs: %i",
1556 (int) (etm
->config
>> 17) & 0x07);
1557 command_print(CMD_CTX
, "number of ext. outputs: %i",
1558 (int) (etm
->config
>> 20) & 0x07);
1559 command_print(CMD_CTX
, "FIFO full %spresent",
1560 (int) (etm
->config
& (1 << 23)) ? "" : "not ");
1561 if (etm
->bcd_vers
< 0x20)
1562 command_print(CMD_CTX
, "protocol version: %i",
1563 (int) (etm
->config
>> 28) & 0x07);
1565 command_print(CMD_CTX
,
1566 "coprocessor and memory access %ssupported",
1567 (etm
->config
& (1 << 26)) ? "" : "not ");
1568 command_print(CMD_CTX
, "trace start/stop %spresent",
1569 (etm
->config
& (1 << 26)) ? "" : "not ");
1570 command_print(CMD_CTX
, "number of context comparators: %i",
1571 (int) (etm
->config
>> 24) & 0x03);
1574 /* SYS_CONFIG isn't present before ETMv1.2 */
1575 etm_sys_config_reg
= etm_reg_lookup(etm
, ETM_SYS_CONFIG
);
1576 if (!etm_sys_config_reg
)
1579 etm_get_reg(etm_sys_config_reg
);
1580 config
= buf_get_u32(etm_sys_config_reg
->value
, 0, 32);
1582 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config
);
1584 max_port_size
= config
& 0x7;
1585 if (etm
->bcd_vers
>= 0x30)
1586 max_port_size
|= (config
>> 6) & 0x08;
1587 switch (max_port_size
)
1589 /* before ETMv3.0 */
1599 /* ETMv3.0 and later*/
1619 LOG_ERROR("Illegal max_port_size");
1622 command_print(CMD_CTX
, "max. port size: %i", max_port_size
);
1624 if (etm
->bcd_vers
< 0x30) {
1625 command_print(CMD_CTX
, "half-rate clocking %ssupported",
1626 (config
& (1 << 3)) ? "" : "not ");
1627 command_print(CMD_CTX
, "full-rate clocking %ssupported",
1628 (config
& (1 << 4)) ? "" : "not ");
1629 command_print(CMD_CTX
, "normal trace format %ssupported",
1630 (config
& (1 << 5)) ? "" : "not ");
1631 command_print(CMD_CTX
, "multiplex trace format %ssupported",
1632 (config
& (1 << 6)) ? "" : "not ");
1633 command_print(CMD_CTX
, "demultiplex trace format %ssupported",
1634 (config
& (1 << 7)) ? "" : "not ");
1636 /* REVISIT show which size and format are selected ... */
1637 command_print(CMD_CTX
, "current port size %ssupported",
1638 (config
& (1 << 10)) ? "" : "not ");
1639 command_print(CMD_CTX
, "current trace format %ssupported",
1640 (config
& (1 << 11)) ? "" : "not ");
1642 if (etm
->bcd_vers
>= 0x21)
1643 command_print(CMD_CTX
, "fetch comparisons %ssupported",
1644 (config
& (1 << 17)) ? "not " : "");
1645 command_print(CMD_CTX
, "FIFO full %ssupported",
1646 (config
& (1 << 8)) ? "" : "not ");
1651 COMMAND_HANDLER(handle_etm_status_command
)
1653 struct target
*target
;
1655 struct etm_context
*etm
;
1656 trace_status_t trace_status
;
1658 target
= get_current_target(CMD_CTX
);
1659 arm
= target_to_arm(target
);
1662 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1669 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1674 if (etm
->bcd_vers
>= 0x11) {
1677 reg
= etm_reg_lookup(etm
, ETM_STATUS
);
1680 if (etm_get_reg(reg
) == ERROR_OK
) {
1681 unsigned s
= buf_get_u32(reg
->value
, 0, reg
->size
);
1683 command_print(CMD_CTX
, "etm: %s%s%s%s",
1684 /* bit(1) == progbit */
1685 (etm
->bcd_vers
>= 0x12)
1687 ? "disabled" : "enabled")
1689 ((s
& (1 << 3)) && etm
->bcd_vers
>= 0x31)
1690 ? " triggered" : "",
1691 ((s
& (1 << 2)) && etm
->bcd_vers
>= 0x12)
1692 ? " start/stop" : "",
1693 ((s
& (1 << 0)) && etm
->bcd_vers
>= 0x11)
1694 ? " untraced-overflow" : "");
1695 } /* else ignore and try showing trace port status */
1698 /* Trace Port Driver status */
1699 trace_status
= etm
->capture_driver
->status(etm
);
1700 if (trace_status
== TRACE_IDLE
)
1702 command_print(CMD_CTX
, "%s: idle", etm
->capture_driver
->name
);
1706 static char *completed
= " completed";
1707 static char *running
= " is running";
1708 static char *overflowed
= ", overflowed";
1709 static char *triggered
= ", triggered";
1711 command_print(CMD_CTX
, "%s: trace collection%s%s%s",
1712 etm
->capture_driver
->name
,
1713 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1714 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1715 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1717 if (etm
->trace_depth
> 0)
1719 command_print(CMD_CTX
, "%i frames of trace data read",
1720 (int)(etm
->trace_depth
));
1727 COMMAND_HANDLER(handle_etm_image_command
)
1729 struct target
*target
;
1731 struct etm_context
*etm_ctx
;
1735 return ERROR_COMMAND_SYNTAX_ERROR
;
1738 target
= get_current_target(CMD_CTX
);
1739 arm
= target_to_arm(target
);
1742 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1749 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1755 image_close(etm_ctx
->image
);
1756 free(etm_ctx
->image
);
1757 command_print(CMD_CTX
, "previously loaded image found and closed");
1760 etm_ctx
->image
= malloc(sizeof(struct image
));
1761 etm_ctx
->image
->base_address_set
= 0;
1762 etm_ctx
->image
->start_address_set
= 0;
1764 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1767 etm_ctx
->image
->base_address_set
= 1;
1768 COMMAND_PARSE_NUMBER(llong
, CMD_ARGV
[1], etm_ctx
->image
->base_address
);
1772 etm_ctx
->image
->base_address_set
= 0;
1775 if (image_open(etm_ctx
->image
, CMD_ARGV
[0], (CMD_ARGC
>= 3) ? CMD_ARGV
[2] : NULL
) != ERROR_OK
)
1777 free(etm_ctx
->image
);
1778 etm_ctx
->image
= NULL
;
1785 COMMAND_HANDLER(handle_etm_dump_command
)
1788 struct target
*target
;
1790 struct etm_context
*etm_ctx
;
1795 return ERROR_COMMAND_SYNTAX_ERROR
;
1798 target
= get_current_target(CMD_CTX
);
1799 arm
= target_to_arm(target
);
1802 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1809 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1813 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
)
1815 command_print(CMD_CTX
, "trace capture wasn't enabled, no trace data captured");
1819 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1821 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1822 command_print(CMD_CTX
, "trace capture not completed");
1826 /* read the trace data if it wasn't read already */
1827 if (etm_ctx
->trace_depth
== 0)
1828 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1830 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1835 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1836 fileio_write_u32(&file
, etm_ctx
->control
);
1837 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1839 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1841 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1842 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1843 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1846 fileio_close(&file
);
1851 COMMAND_HANDLER(handle_etm_load_command
)
1854 struct target
*target
;
1856 struct etm_context
*etm_ctx
;
1861 return ERROR_COMMAND_SYNTAX_ERROR
;
1864 target
= get_current_target(CMD_CTX
);
1865 arm
= target_to_arm(target
);
1868 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1875 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1879 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1881 command_print(CMD_CTX
, "trace capture running, stop first");
1885 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1891 int retval
= fileio_size(&file
, &filesize
);
1892 if (retval
!= ERROR_OK
)
1894 fileio_close(&file
);
1900 command_print(CMD_CTX
, "size isn't a multiple of 4, no valid trace data");
1901 fileio_close(&file
);
1905 if (etm_ctx
->trace_depth
> 0)
1907 free(etm_ctx
->trace_data
);
1908 etm_ctx
->trace_data
= NULL
;
1913 fileio_read_u32(&file
, &tmp
); etm_ctx
->capture_status
= tmp
;
1914 fileio_read_u32(&file
, &tmp
); etm_ctx
->control
= tmp
;
1915 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1917 etm_ctx
->trace_data
= malloc(sizeof(struct etmv1_trace_data
) * etm_ctx
->trace_depth
);
1918 if (etm_ctx
->trace_data
== NULL
)
1920 command_print(CMD_CTX
, "not enough memory to perform operation");
1921 fileio_close(&file
);
1925 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1927 uint32_t pipestat
, packet
, flags
;
1928 fileio_read_u32(&file
, &pipestat
);
1929 fileio_read_u32(&file
, &packet
);
1930 fileio_read_u32(&file
, &flags
);
1931 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1932 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1933 etm_ctx
->trace_data
[i
].flags
= flags
;
1936 fileio_close(&file
);
1941 COMMAND_HANDLER(handle_etm_start_command
)
1943 struct target
*target
;
1945 struct etm_context
*etm_ctx
;
1946 struct reg
*etm_ctrl_reg
;
1948 target
= get_current_target(CMD_CTX
);
1949 arm
= target_to_arm(target
);
1952 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1959 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1963 /* invalidate old tracing data */
1964 etm_ctx
->capture_status
= TRACE_IDLE
;
1965 if (etm_ctx
->trace_depth
> 0)
1967 free(etm_ctx
->trace_data
);
1968 etm_ctx
->trace_data
= NULL
;
1970 etm_ctx
->trace_depth
= 0;
1972 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1976 etm_get_reg(etm_ctrl_reg
);
1978 /* Clear programming bit (10), set port selection bit (11) */
1979 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1981 etm_store_reg(etm_ctrl_reg
);
1982 jtag_execute_queue();
1984 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1989 COMMAND_HANDLER(handle_etm_stop_command
)
1991 struct target
*target
;
1993 struct etm_context
*etm_ctx
;
1994 struct reg
*etm_ctrl_reg
;
1996 target
= get_current_target(CMD_CTX
);
1997 arm
= target_to_arm(target
);
2000 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
2007 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
2011 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
2015 etm_get_reg(etm_ctrl_reg
);
2017 /* Set programming bit (10), clear port selection bit (11) */
2018 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
2020 etm_store_reg(etm_ctrl_reg
);
2021 jtag_execute_queue();
2023 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
2028 COMMAND_HANDLER(handle_etm_trigger_debug_command
)
2030 struct target
*target
;
2032 struct etm_context
*etm
;
2034 target
= get_current_target(CMD_CTX
);
2035 arm
= target_to_arm(target
);
2038 command_print(CMD_CTX
, "ETM: %s isn't an ARM",
2039 target_name(target
));
2046 command_print(CMD_CTX
, "ETM: no ETM configured for %s",
2047 target_name(target
));
2051 if (CMD_ARGC
== 1) {
2052 struct reg
*etm_ctrl_reg
;
2055 etm_ctrl_reg
= etm_reg_lookup(etm
, ETM_CTRL
);
2059 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], dbgrq
);
2061 etm
->control
|= ETM_CTRL_DBGRQ
;
2063 etm
->control
&= ~ETM_CTRL_DBGRQ
;
2065 /* etm->control will be written to hardware
2066 * the next time an "etm start" is issued.
2068 buf_set_u32(etm_ctrl_reg
->value
, 0, 32, etm
->control
);
2071 command_print(CMD_CTX
, "ETM: %s debug halt",
2072 (etm
->control
& ETM_CTRL_DBGRQ
)
2074 : "does not trigger");
2078 COMMAND_HANDLER(handle_etm_analyze_command
)
2080 struct target
*target
;
2082 struct etm_context
*etm_ctx
;
2085 target
= get_current_target(CMD_CTX
);
2086 arm
= target_to_arm(target
);
2089 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
2096 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
2100 if ((retval
= etmv1_analyze_trace(etm_ctx
, CMD_CTX
)) != ERROR_OK
)
2102 /* FIX! error should be reported inside etmv1_analyze_trace() */
2105 case ERROR_ETM_ANALYSIS_FAILED
:
2106 command_print(CMD_CTX
, "further analysis failed (corrupted trace data or just end of data");
2108 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE
:
2109 command_print(CMD_CTX
, "no instruction for current address available, analysis aborted");
2111 case ERROR_TRACE_IMAGE_UNAVAILABLE
:
2112 command_print(CMD_CTX
, "no image available for trace analysis");
2115 command_print(CMD_CTX
, "unknown error");
2122 static const struct command_registration etm_config_command_handlers
[] = {
2124 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2125 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2127 * Also, these parameters don't match ETM v3+ modules...
2130 .handler
= handle_etm_config_command
,
2131 .mode
= COMMAND_CONFIG
,
2132 .help
= "Set up ETM output port.",
2133 .usage
= "target port_width port_mode clocking capture_driver",
2135 COMMAND_REGISTRATION_DONE
2137 const struct command_registration etm_command_handlers
[] = {
2140 .mode
= COMMAND_ANY
,
2141 .help
= "Emebdded Trace Macrocell command group",
2143 .chain
= etm_config_command_handlers
,
2145 COMMAND_REGISTRATION_DONE
2148 static const struct command_registration etm_exec_command_handlers
[] = {
2150 .name
= "tracemode",
2151 .handler
= handle_etm_tracemode_command
,
2152 .mode
= COMMAND_EXEC
,
2153 .help
= "configure/display trace mode",
2154 .usage
= "('none'|'data'|'address'|'all') "
2156 "['enable'|'disable'] "
2157 "['enable'|'disable']",
2161 .handler
= handle_etm_info_command
,
2162 .mode
= COMMAND_EXEC
,
2164 .help
= "display info about the current target's ETM",
2168 .handler
= handle_etm_status_command
,
2169 .mode
= COMMAND_EXEC
,
2171 .help
= "display current target's ETM status",
2175 .handler
= handle_etm_start_command
,
2176 .mode
= COMMAND_EXEC
,
2178 .help
= "start ETM trace collection",
2182 .handler
= handle_etm_stop_command
,
2183 .mode
= COMMAND_EXEC
,
2185 .help
= "stop ETM trace collection",
2188 .name
= "trigger_debug",
2189 .handler
= handle_etm_trigger_debug_command
,
2190 .mode
= COMMAND_EXEC
,
2191 .help
= "enable/disable debug entry on trigger",
2192 .usage
= "['enable'|'disable']",
2196 .handler
= handle_etm_analyze_command
,
2197 .mode
= COMMAND_EXEC
,
2199 .help
= "analyze collected ETM trace",
2203 .handler
= handle_etm_image_command
,
2204 .mode
= COMMAND_EXEC
,
2205 .help
= "load image from file with optional offset",
2206 .usage
= "<file> [base address] [type]",
2210 .handler
= handle_etm_dump_command
,
2211 .mode
= COMMAND_EXEC
,
2212 .help
= "dump captured trace data to file",
2213 .usage
= "filename",
2217 .handler
= handle_etm_load_command
,
2218 .mode
= COMMAND_EXEC
,
2220 .help
= "load trace data for analysis <file>",
2222 COMMAND_REGISTRATION_DONE
2225 static int etm_register_user_commands(struct command_context
*cmd_ctx
)
2227 struct command
*etm_cmd
= command_find_in_context(cmd_ctx
, "etm");
2228 return register_commands(cmd_ctx
, etm_cmd
, etm_exec_command_handlers
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)