1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
28 #include "arm_disassembler.h"
30 #include "etm_dummy.h"
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
67 uint8_t size
; /* low-N of 32 bits */
68 uint8_t mode
; /* RO, WO, RW */
69 uint8_t bcd_vers
; /* 1.0, 2.0, etc */
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core
[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG
, 32, RO
, 0x10, "ETM_config", },
84 { ETM_ID
, 32, RO
, 0x20, "ETM_id", },
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic
[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL
, 32, RW
, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT
, 17, WO
, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL
, 8, WO
, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS
, 3, RO
, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG
, 9, RO
, 0x12, "ETM_sys_config", },
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL
, 32, WO
, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2
, 16, WO
, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT
, 17, WO
, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1
, 26, WO
, 0x10, "ETM_trace_en_ctrl1", },
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT
, 17, WO
, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1
, 32, WO
, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2
, 32, WO
, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3
, 17, WO
, 0x10, "ETM_viewdata_ctrl3", },
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
110 { 0x78, 12, WO
, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO
, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO
, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO
, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO
, 0x34, "ETM_behavior_control", },
117 static const struct etm_reg_info etm_fifofull
[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION
, 25, WO
, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL
, 8, WO
, 0x10, "ETM_fifofull_level", },
123 static const struct etm_reg_info etm_addr_comp
[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
147 #undef ADDR_COMPARATOR
150 static const struct etm_reg_info etm_data_comp
[] = {
151 /* Data Value Comparators (NOTE: odd addresses are reserved) */
152 #define DATA_COMPARATOR(i) \
153 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
154 "ETM_data_" #i "_comparator_value", }, \
155 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
156 "ETM_data_" #i "_comparator_mask", }
165 #undef DATA_COMPARATOR
168 static const struct etm_reg_info etm_counters
[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
185 static const struct etm_reg_info etm_sequencer
[] = {
187 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
188 "ETM_sequencer_event" #i, }
189 ETM_SEQ(0), /* 1->2 */
190 ETM_SEQ(1), /* 2->1 */
191 ETM_SEQ(2), /* 2->3 */
192 ETM_SEQ(3), /* 3->1 */
193 ETM_SEQ(4), /* 3->2 */
194 ETM_SEQ(5), /* 1->3 */
197 { ETM_SEQUENCER_STATE
, 2, RO
, 0x10, "ETM_sequencer_state", },
200 static const struct etm_reg_info etm_outputs
[] = {
201 #define ETM_OUTPUT(i) \
202 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
203 "ETM_external_output" #i, }
213 /* registers from 0x6c..0x7f were added after ETMv1.3 */
215 /* Context ID Comparators */
216 { 0x6c, 32, RO
, 0x20, "ETM_contextid_comparator_value1", }
217 { 0x6d, 32, RO
, 0x20, "ETM_contextid_comparator_value2", }
218 { 0x6e, 32, RO
, 0x20, "ETM_contextid_comparator_value3", }
219 { 0x6f, 32, RO
, 0x20, "ETM_contextid_comparator_mask", }
222 static int etm_get_reg(struct reg
*reg
);
223 static int etm_read_reg_w_check(struct reg
*reg
,
224 uint8_t* check_value
, uint8_t* check_mask
);
225 static int etm_register_user_commands(struct command_context
*cmd_ctx
);
226 static int etm_set_reg_w_exec(struct reg
*reg
, uint8_t *buf
);
227 static int etm_write_reg(struct reg
*reg
, uint32_t value
);
229 static const struct reg_arch_type etm_scan6_type
= {
231 .set
= etm_set_reg_w_exec
,
234 /* Look up register by ID ... most ETM instances only
235 * support a subset of the possible registers.
237 static struct reg
*etm_reg_lookup(struct etm_context
*etm_ctx
, unsigned id
)
239 struct reg_cache
*cache
= etm_ctx
->reg_cache
;
242 for (i
= 0; i
< cache
->num_regs
; i
++) {
243 struct etm_reg
*reg
= cache
->reg_list
[i
].arch_info
;
245 if (reg
->reg_info
->addr
== id
)
246 return &cache
->reg_list
[i
];
249 /* caller asking for nonexistent register is a bug! */
250 /* REVISIT say which of the N targets was involved */
251 LOG_ERROR("ETM: register 0x%02x not available", id
);
255 static void etm_reg_add(unsigned bcd_vers
, struct arm_jtag
*jtag_info
,
256 struct reg_cache
*cache
, struct etm_reg
*ereg
,
257 const struct etm_reg_info
*r
, unsigned nreg
)
259 struct reg
*reg
= cache
->reg_list
;
261 reg
+= cache
->num_regs
;
262 ereg
+= cache
->num_regs
;
264 /* add up to "nreg" registers from "r", if supported by this
265 * version of the ETM, to the specified cache.
267 for (; nreg
--; r
++) {
269 /* this ETM may be too old to have some registers */
270 if (r
->bcd_vers
> bcd_vers
)
275 reg
->value
= &ereg
->value
;
276 reg
->arch_info
= ereg
;
277 reg
->type
= &etm_scan6_type
;
282 ereg
->jtag_info
= jtag_info
;
287 struct reg_cache
*etm_build_reg_cache(struct target
*target
,
288 struct arm_jtag
*jtag_info
, struct etm_context
*etm_ctx
)
290 struct reg_cache
*reg_cache
= malloc(sizeof(struct reg_cache
));
291 struct reg
*reg_list
= NULL
;
292 struct etm_reg
*arch_info
= NULL
;
293 unsigned bcd_vers
, config
;
295 /* the actual registers are kept in two arrays */
296 reg_list
= calloc(128, sizeof(struct reg
));
297 arch_info
= calloc(128, sizeof(struct etm_reg
));
299 /* fill in values for the reg cache */
300 reg_cache
->name
= "etm registers";
301 reg_cache
->next
= NULL
;
302 reg_cache
->reg_list
= reg_list
;
303 reg_cache
->num_regs
= 0;
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
308 etm_reg_add(0x10, jtag_info
, reg_cache
, arch_info
,
311 etm_get_reg(reg_list
);
312 etm_ctx
->config
= buf_get_u32((void *)&arch_info
->value
, 0, 32);
313 config
= etm_ctx
->config
;
315 /* figure ETM version then add base registers */
316 if (config
& (1 << 31)) {
318 LOG_WARNING("ETMv2+ support is incomplete");
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
325 etm_reg_add(0x20, jtag_info
, reg_cache
, arch_info
,
327 etm_get_reg(reg_list
+ 1);
328 etm_ctx
->id
= buf_get_u32(
329 (void *)&arch_info
[1].value
, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx
->id
);
331 bcd_vers
= 0x10 + (((etm_ctx
->id
) >> 4) & 0xff);
334 switch (config
>> 28) {
351 LOG_WARNING("Bad ETMv1 protocol %d", config
>> 28);
355 etm_ctx
->bcd_vers
= bcd_vers
;
356 LOG_INFO("ETM v%d.%d", bcd_vers
>> 4, bcd_vers
& 0xf);
358 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
359 etm_basic
, ARRAY_SIZE(etm_basic
));
361 /* address and data comparators; counters; outputs */
362 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
363 etm_addr_comp
, 4 * (0x0f & (config
>> 0)));
364 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
365 etm_data_comp
, 2 * (0x0f & (config
>> 4)));
366 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
367 etm_counters
, 4 * (0x07 & (config
>> 13)));
368 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
369 etm_outputs
, (0x07 & (config
>> 20)));
371 /* FIFOFULL presence is optional
372 * REVISIT for ETMv1.2 and later, don't bother adding this
373 * unless ETM_SYS_CONFIG says it's also *supported* ...
375 if (config
& (1 << 23))
376 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
377 etm_fifofull
, ARRAY_SIZE(etm_fifofull
));
379 /* sequencer is optional (for state-dependant triggering) */
380 if (config
& (1 << 16))
381 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
382 etm_sequencer
, ARRAY_SIZE(etm_sequencer
));
384 /* REVISIT could realloc and likely save half the memory
385 * in the two chunks we allocated...
388 /* the ETM might have an ETB connected */
389 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0)
391 struct etb
*etb
= etm_ctx
->capture_driver_priv
;
395 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
399 reg_cache
->next
= etb_build_reg_cache(etb
);
401 etb
->reg_cache
= reg_cache
->next
;
404 etm_ctx
->reg_cache
= reg_cache
;
414 static int etm_read_reg(struct reg
*reg
)
416 return etm_read_reg_w_check(reg
, NULL
, NULL
);
419 static int etm_store_reg(struct reg
*reg
)
421 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
424 int etm_setup(struct target
*target
)
427 uint32_t etm_ctrl_value
;
428 struct arm
*arm
= target_to_arm(target
);
429 struct etm_context
*etm_ctx
= arm
->etm
;
430 struct reg
*etm_ctrl_reg
;
432 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg
);
438 etm_ctrl_value
= buf_get_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
);
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value
&= ~0x1;
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
446 etm_ctrl_value
= (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
449 & ~ETM_PORT_CLOCK_MASK
)
452 buf_set_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
, etm_ctrl_value
);
453 etm_store_reg(etm_ctrl_reg
);
455 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
458 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
459 * verify that those width and mode settings are OK ...
462 if ((retval
= etm_ctx
->capture_driver
->init(etm_ctx
)) != ERROR_OK
)
464 LOG_ERROR("ETM capture driver initialization failed");
470 static int etm_get_reg(struct reg
*reg
)
474 if ((retval
= etm_read_reg(reg
)) != ERROR_OK
)
476 LOG_ERROR("BUG: error scheduling etm register read");
480 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
482 LOG_ERROR("register read failed");
489 static int etm_read_reg_w_check(struct reg
*reg
,
490 uint8_t* check_value
, uint8_t* check_mask
)
492 struct etm_reg
*etm_reg
= reg
->arch_info
;
493 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
494 uint8_t reg_addr
= r
->addr
& 0x7f;
495 struct scan_field fields
[3];
497 if (etm_reg
->reg_info
->mode
== WO
) {
498 LOG_ERROR("BUG: can't read write-only register %s", r
->name
);
499 return ERROR_INVALID_ARGUMENTS
;
502 LOG_DEBUG("%s (%u)", r
->name
, reg_addr
);
504 jtag_set_end_state(TAP_IDLE
);
505 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
506 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
508 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
509 fields
[0].num_bits
= 32;
510 fields
[0].out_value
= reg
->value
;
511 fields
[0].in_value
= NULL
;
512 fields
[0].check_value
= NULL
;
513 fields
[0].check_mask
= NULL
;
515 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
516 fields
[1].num_bits
= 7;
517 fields
[1].out_value
= malloc(1);
518 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
519 fields
[1].in_value
= NULL
;
520 fields
[1].check_value
= NULL
;
521 fields
[1].check_mask
= NULL
;
523 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
524 fields
[2].num_bits
= 1;
525 fields
[2].out_value
= malloc(1);
526 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
527 fields
[2].in_value
= NULL
;
528 fields
[2].check_value
= NULL
;
529 fields
[2].check_mask
= NULL
;
531 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
533 fields
[0].in_value
= reg
->value
;
534 fields
[0].check_value
= check_value
;
535 fields
[0].check_mask
= check_mask
;
537 jtag_add_dr_scan_check(3, fields
, jtag_get_end_state());
539 free(fields
[1].out_value
);
540 free(fields
[2].out_value
);
545 static int etm_set_reg(struct reg
*reg
, uint32_t value
)
549 if ((retval
= etm_write_reg(reg
, value
)) != ERROR_OK
)
551 LOG_ERROR("BUG: error scheduling etm register write");
555 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
562 static int etm_set_reg_w_exec(struct reg
*reg
, uint8_t *buf
)
566 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
568 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
570 LOG_ERROR("register write failed");
576 static int etm_write_reg(struct reg
*reg
, uint32_t value
)
578 struct etm_reg
*etm_reg
= reg
->arch_info
;
579 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
580 uint8_t reg_addr
= r
->addr
& 0x7f;
581 struct scan_field fields
[3];
583 if (etm_reg
->reg_info
->mode
== RO
) {
584 LOG_ERROR("BUG: can't write read--only register %s", r
->name
);
585 return ERROR_INVALID_ARGUMENTS
;
588 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32
"", r
->name
, reg_addr
, value
);
590 jtag_set_end_state(TAP_IDLE
);
591 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
592 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
594 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
595 fields
[0].num_bits
= 32;
597 fields
[0].out_value
= tmp1
;
598 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
599 fields
[0].in_value
= NULL
;
601 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
602 fields
[1].num_bits
= 7;
604 fields
[1].out_value
= &tmp2
;
605 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
606 fields
[1].in_value
= NULL
;
608 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
609 fields
[2].num_bits
= 1;
611 fields
[2].out_value
= &tmp3
;
612 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
613 fields
[2].in_value
= NULL
;
615 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
621 /* ETM trace analysis functionality */
623 static struct etm_capture_driver
*etm_capture_drivers
[] =
626 &etm_dummy_capture_driver
,
627 #if BUILD_OOCD_TRACE == 1
628 &oocd_trace_capture_driver
,
633 static int etm_read_instruction(struct etm_context
*ctx
, struct arm_instruction
*instruction
)
642 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
644 /* search for the section the current instruction belongs to */
645 for (i
= 0; i
< ctx
->image
->num_sections
; i
++)
647 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
648 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
> ctx
->current_pc
))
657 /* current instruction couldn't be found in the image */
658 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
661 if (ctx
->core_state
== ARM_STATE_ARM
)
664 if ((retval
= image_read_section(ctx
->image
, section
,
665 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
666 4, buf
, &size_read
)) != ERROR_OK
)
668 LOG_ERROR("error while reading instruction: %i", retval
);
669 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
671 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
672 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
674 else if (ctx
->core_state
== ARM_STATE_THUMB
)
677 if ((retval
= image_read_section(ctx
->image
, section
,
678 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
679 2, buf
, &size_read
)) != ERROR_OK
)
681 LOG_ERROR("error while reading instruction: %i", retval
);
682 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
684 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
685 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
687 else if (ctx
->core_state
== ARM_STATE_JAZELLE
)
689 LOG_ERROR("BUG: tracing of jazelle code not supported");
694 LOG_ERROR("BUG: unknown core state encountered");
701 static int etmv1_next_packet(struct etm_context
*ctx
, uint8_t *packet
, int apo
)
703 while (ctx
->data_index
< ctx
->trace_depth
)
705 /* if the caller specified an address packet offset, skip until the
706 * we reach the n-th cycle marked with tracesync */
709 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
720 /* no tracedata output during a TD cycle
721 * or in a trigger cycle */
722 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
723 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
))
730 if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
)
732 if (ctx
->data_half
== 0)
734 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
739 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
744 else if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
746 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
751 /* on a 4-bit port, a packet will be output during two consecutive cycles */
752 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
755 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
756 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
757 ctx
->data_index
+= 2;
766 static int etmv1_branch_address(struct etm_context
*ctx
)
774 /* quit analysis if less than two cycles are left in the trace
775 * because we can't extract the APO */
776 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
779 /* a BE could be output during an APO cycle, skip the current
780 * and continue with the new one */
781 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
783 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
786 /* address packet offset encoded in the next two cycles' pipestat bits */
787 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
788 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
790 /* count number of tracesync cycles between current pipe_index and data_index
791 * i.e. the number of tracesyncs that data_index already passed by
792 * to subtract them from the APO */
793 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++)
795 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
799 /* extract up to four 7-bit packets */
801 if ((retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0)) != 0)
803 ctx
->last_branch
&= ~(0x7f << shift
);
804 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
806 } while ((packet
& 0x80) && (shift
< 28));
808 /* one last packet holding 4 bits of the address, plus the branch reason code */
809 if ((shift
== 28) && (packet
& 0x80))
811 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
813 ctx
->last_branch
&= 0x0fffffff;
814 ctx
->last_branch
|= (packet
& 0x0f) << 28;
815 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
820 ctx
->last_branch_reason
= 0;
828 /* if a full address was output, we might have branched into Jazelle state */
829 if ((shift
== 32) && (packet
& 0x80))
831 ctx
->core_state
= ARM_STATE_JAZELLE
;
835 /* if we didn't branch into Jazelle state, the current processor state is
836 * encoded in bit 0 of the branch target address */
837 if (ctx
->last_branch
& 0x1)
839 ctx
->core_state
= ARM_STATE_THUMB
;
840 ctx
->last_branch
&= ~0x1;
844 ctx
->core_state
= ARM_STATE_ARM
;
845 ctx
->last_branch
&= ~0x3;
852 static int etmv1_data(struct etm_context
*ctx
, int size
, uint32_t *data
)
858 for (j
= 0; j
< size
; j
++)
860 if ((retval
= etmv1_next_packet(ctx
, &buf
[j
], 0)) != 0)
866 LOG_ERROR("TODO: add support for 64-bit values");
870 *data
= target_buffer_get_u32(ctx
->target
, buf
);
872 *data
= target_buffer_get_u16(ctx
->target
, buf
);
881 static int etmv1_analyze_trace(struct etm_context
*ctx
, struct command_context
*cmd_ctx
)
884 struct arm_instruction instruction
;
886 /* read the trace data if it wasn't read already */
887 if (ctx
->trace_depth
== 0)
888 ctx
->capture_driver
->read_trace(ctx
);
890 /* start at the beginning of the captured trace */
895 /* neither the PC nor the data pointer are valid */
899 while (ctx
->pipe_index
< ctx
->trace_depth
)
901 uint8_t pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
902 uint32_t next_pc
= ctx
->current_pc
;
903 uint32_t old_data_index
= ctx
->data_index
;
904 uint32_t old_data_half
= ctx
->data_half
;
905 uint32_t old_index
= ctx
->pipe_index
;
906 uint32_t last_instruction
= ctx
->last_instruction
;
908 int current_pc_ok
= ctx
->pc_ok
;
910 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
912 command_print(cmd_ctx
, "--- trigger ---");
915 /* instructions execute in IE/D or BE/D cycles */
916 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
917 ctx
->last_instruction
= ctx
->pipe_index
;
919 /* if we don't have a valid pc skip until we reach an indirect branch */
920 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
))
926 /* any indirect branch could have interrupted instruction flow
927 * - the branch reason code could indicate a trace discontinuity
928 * - a branch to the exception vectors indicates an exception
930 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
))
932 /* backup current data index, to be able to consume the branch address
933 * before examining data address and values
935 old_data_index
= ctx
->data_index
;
936 old_data_half
= ctx
->data_half
;
938 ctx
->last_instruction
= ctx
->pipe_index
;
940 if ((retval
= etmv1_branch_address(ctx
)) != 0)
942 /* negative return value from etmv1_branch_address means we ran out of packets,
943 * quit analysing the trace */
947 /* a positive return values means the current branch was abandoned,
948 * and a new branch was encountered in cycle ctx->pipe_index + retval;
950 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
951 ctx
->pipe_index
+= retval
;
955 /* skip over APO cycles */
956 ctx
->pipe_index
+= 2;
958 switch (ctx
->last_branch_reason
)
960 case 0x0: /* normal PC change */
961 next_pc
= ctx
->last_branch
;
963 case 0x1: /* tracing enabled */
964 command_print(cmd_ctx
, "--- tracing enabled at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
965 ctx
->current_pc
= ctx
->last_branch
;
969 case 0x2: /* trace restarted after FIFO overflow */
970 command_print(cmd_ctx
, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
971 ctx
->current_pc
= ctx
->last_branch
;
975 case 0x3: /* exit from debug state */
976 command_print(cmd_ctx
, "--- exit from debug state at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
977 ctx
->current_pc
= ctx
->last_branch
;
981 case 0x4: /* periodic synchronization point */
982 next_pc
= ctx
->last_branch
;
983 /* if we had no valid PC prior to this synchronization point,
984 * we have to move on with the next trace cycle
988 command_print(cmd_ctx
, "--- periodic synchronization point at 0x%8.8" PRIx32
" ---", next_pc
);
989 ctx
->current_pc
= next_pc
;
994 default: /* reserved */
995 LOG_ERROR("BUG: branch reason code 0x%" PRIx32
" is reserved", ctx
->last_branch_reason
);
999 /* if we got here the branch was a normal PC change
1000 * (or a periodic synchronization point, which means the same for that matter)
1001 * if we didn't accquire a complete PC continue with the next cycle
1006 /* indirect branch to the exception vector means an exception occured */
1007 if ((ctx
->last_branch
<= 0x20)
1008 || ((ctx
->last_branch
>= 0xffff0000) && (ctx
->last_branch
<= 0xffff0020)))
1010 if ((ctx
->last_branch
& 0xff) == 0x10)
1012 command_print(cmd_ctx
, "data abort");
1016 command_print(cmd_ctx
, "exception vector 0x%2.2" PRIx32
"", ctx
->last_branch
);
1017 ctx
->current_pc
= ctx
->last_branch
;
1024 /* an instruction was executed (or not, depending on the condition flags)
1025 * retrieve it from the image for displaying */
1026 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
1027 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
1028 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4))))
1030 if ((retval
= etm_read_instruction(ctx
, &instruction
)) != ERROR_OK
)
1032 /* can't continue tracing with no image available */
1033 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
1037 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
1039 /* TODO: handle incomplete images
1040 * for now we just quit the analsysis*/
1045 cycles
= old_index
- last_instruction
;
1048 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
))
1050 uint32_t new_data_index
= ctx
->data_index
;
1051 uint32_t new_data_half
= ctx
->data_half
;
1053 /* in case of a branch with data, the branch target address was consumed before
1054 * we temporarily go back to the saved data index */
1055 if (pipestat
== STAT_BD
)
1057 ctx
->data_index
= old_data_index
;
1058 ctx
->data_half
= old_data_half
;
1061 if (ctx
->tracemode
& ETMV1_TRACE_ADDR
)
1067 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
1068 return ERROR_ETM_ANALYSIS_FAILED
;
1069 ctx
->last_ptr
&= ~(0x7f << shift
);
1070 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
1072 } while ((packet
& 0x80) && (shift
< 32));
1079 command_print(cmd_ctx
, "address: 0x%8.8" PRIx32
"", ctx
->last_ptr
);
1083 if (ctx
->tracemode
& ETMV1_TRACE_DATA
)
1085 if ((instruction
.type
== ARM_LDM
) || (instruction
.type
== ARM_STM
))
1088 for (i
= 0; i
< 16; i
++)
1090 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
1093 if (etmv1_data(ctx
, 4, &data
) != 0)
1094 return ERROR_ETM_ANALYSIS_FAILED
;
1095 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1099 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_STRH
))
1102 if (etmv1_data(ctx
, arm_access_size(&instruction
), &data
) != 0)
1103 return ERROR_ETM_ANALYSIS_FAILED
;
1104 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1108 /* restore data index after consuming BD address and data */
1109 if (pipestat
== STAT_BD
)
1111 ctx
->data_index
= new_data_index
;
1112 ctx
->data_half
= new_data_half
;
1117 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
1119 if (((instruction
.type
== ARM_B
) ||
1120 (instruction
.type
== ARM_BL
) ||
1121 (instruction
.type
== ARM_BLX
)) &&
1122 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff))
1124 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
1128 next_pc
+= (ctx
->core_state
== ARM_STATE_ARM
) ? 4 : 2;
1131 else if (pipestat
== STAT_IN
)
1133 next_pc
+= (ctx
->core_state
== ARM_STATE_ARM
) ? 4 : 2;
1136 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
))
1138 char cycles_text
[32] = "";
1140 /* if the trace was captured with cycle accurate tracing enabled,
1141 * output the number of cycles since the last executed instruction
1143 if (ctx
->tracemode
& ETMV1_CYCLE_ACCURATE
)
1145 snprintf(cycles_text
, 32, " (%i %s)",
1147 (cycles
== 1) ? "cycle" : "cycles");
1150 command_print(cmd_ctx
, "%s%s%s",
1152 (pipestat
== STAT_IN
) ? " (not executed)" : "",
1155 ctx
->current_pc
= next_pc
;
1157 /* packets for an instruction don't start on or before the preceding
1158 * functional pipestat (i.e. other than WT or TD)
1160 if (ctx
->data_index
<= ctx
->pipe_index
)
1162 ctx
->data_index
= ctx
->pipe_index
+ 1;
1167 ctx
->pipe_index
+= 1;
1173 static COMMAND_HELPER(handle_etm_tracemode_command_update
,
1174 etmv1_tracemode_t
*mode
)
1176 etmv1_tracemode_t tracemode
;
1178 /* what parts of data access are traced? */
1179 if (strcmp(CMD_ARGV
[0], "none") == 0)
1180 tracemode
= ETMV1_TRACE_NONE
;
1181 else if (strcmp(CMD_ARGV
[0], "data") == 0)
1182 tracemode
= ETMV1_TRACE_DATA
;
1183 else if (strcmp(CMD_ARGV
[0], "address") == 0)
1184 tracemode
= ETMV1_TRACE_ADDR
;
1185 else if (strcmp(CMD_ARGV
[0], "all") == 0)
1186 tracemode
= ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
;
1189 command_print(CMD_CTX
, "invalid option '%s'", CMD_ARGV
[0]);
1190 return ERROR_INVALID_ARGUMENTS
;
1194 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[1], context_id
);
1198 tracemode
|= ETMV1_CONTEXTID_NONE
;
1201 tracemode
|= ETMV1_CONTEXTID_8
;
1204 tracemode
|= ETMV1_CONTEXTID_16
;
1207 tracemode
|= ETMV1_CONTEXTID_32
;
1210 command_print(CMD_CTX
, "invalid option '%s'", CMD_ARGV
[1]);
1211 return ERROR_INVALID_ARGUMENTS
;
1214 bool etmv1_cycle_accurate
;
1215 COMMAND_PARSE_ENABLE(CMD_ARGV
[2], etmv1_cycle_accurate
);
1216 if (etmv1_cycle_accurate
)
1217 tracemode
|= ETMV1_CYCLE_ACCURATE
;
1219 bool etmv1_branch_output
;
1220 COMMAND_PARSE_ENABLE(CMD_ARGV
[3], etmv1_branch_output
);
1221 tracemode
|= ETMV1_BRANCH_OUTPUT
;
1224 * - CPRT tracing (coprocessor register transfers)
1225 * - debug request (causes debug entry on trigger)
1226 * - stall on FIFOFULL (preventing tracedata lossage)
1233 COMMAND_HANDLER(handle_etm_tracemode_command
)
1235 struct target
*target
= get_current_target(CMD_CTX
);
1236 struct arm
*arm
= target_to_arm(target
);
1237 struct etm_context
*etm
;
1240 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1246 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1250 etmv1_tracemode_t tracemode
= etm
->tracemode
;
1257 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update
, &tracemode
);
1260 command_print(CMD_CTX
, "usage: configure trace mode "
1261 "<none | data | address | all> "
1262 "<context id bits> <cycle accurate> <branch output>");
1267 * todo: fail if parameters were invalid for this hardware,
1268 * or couldn't be written; display actual hardware state...
1271 command_print(CMD_CTX
, "current tracemode configuration:");
1273 switch (tracemode
& ETMV1_TRACE_MASK
)
1275 case ETMV1_TRACE_NONE
:
1276 command_print(CMD_CTX
, "data tracing: none");
1278 case ETMV1_TRACE_DATA
:
1279 command_print(CMD_CTX
, "data tracing: data only");
1281 case ETMV1_TRACE_ADDR
:
1282 command_print(CMD_CTX
, "data tracing: address only");
1284 case ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
:
1285 command_print(CMD_CTX
, "data tracing: address and data");
1289 switch (tracemode
& ETMV1_CONTEXTID_MASK
)
1291 case ETMV1_CONTEXTID_NONE
:
1292 command_print(CMD_CTX
, "contextid tracing: none");
1294 case ETMV1_CONTEXTID_8
:
1295 command_print(CMD_CTX
, "contextid tracing: 8 bit");
1297 case ETMV1_CONTEXTID_16
:
1298 command_print(CMD_CTX
, "contextid tracing: 16 bit");
1300 case ETMV1_CONTEXTID_32
:
1301 command_print(CMD_CTX
, "contextid tracing: 32 bit");
1305 if (tracemode
& ETMV1_CYCLE_ACCURATE
)
1307 command_print(CMD_CTX
, "cycle-accurate tracing enabled");
1311 command_print(CMD_CTX
, "cycle-accurate tracing disabled");
1314 if (tracemode
& ETMV1_BRANCH_OUTPUT
)
1316 command_print(CMD_CTX
, "full branch address output enabled");
1320 command_print(CMD_CTX
, "full branch address output disabled");
1323 /* only update ETM_CTRL register if tracemode changed */
1324 if (etm
->tracemode
!= tracemode
)
1326 struct reg
*etm_ctrl_reg
;
1328 etm_ctrl_reg
= etm_reg_lookup(etm
, ETM_CTRL
);
1332 etm_get_reg(etm_ctrl_reg
);
1334 buf_set_u32(etm_ctrl_reg
->value
, 2, 2, tracemode
& ETMV1_TRACE_MASK
);
1335 buf_set_u32(etm_ctrl_reg
->value
, 14, 2, (tracemode
& ETMV1_CONTEXTID_MASK
) >> 4);
1336 buf_set_u32(etm_ctrl_reg
->value
, 12, 1, (tracemode
& ETMV1_CYCLE_ACCURATE
) >> 8);
1337 buf_set_u32(etm_ctrl_reg
->value
, 8, 1, (tracemode
& ETMV1_BRANCH_OUTPUT
) >> 9);
1338 etm_store_reg(etm_ctrl_reg
);
1340 etm
->tracemode
= tracemode
;
1342 /* invalidate old trace data */
1343 etm
->capture_status
= TRACE_IDLE
;
1344 if (etm
->trace_depth
> 0)
1346 free(etm
->trace_data
);
1347 etm
->trace_data
= NULL
;
1349 etm
->trace_depth
= 0;
1355 COMMAND_HANDLER(handle_etm_config_command
)
1357 struct target
*target
;
1359 etm_portmode_t portmode
= 0x0;
1360 struct etm_context
*etm_ctx
;
1364 return ERROR_COMMAND_SYNTAX_ERROR
;
1366 target
= get_target(CMD_ARGV
[0]);
1369 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
1373 arm
= target_to_arm(target
);
1375 command_print(CMD_CTX
, "target '%s' is '%s'; not an ARM",
1376 target_name(target
),
1377 target_type_name(target
));
1381 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1382 * version we'll be using!! -- so we can't know how to validate
1383 * params yet. "etm config" should likely be *AFTER* hookup...
1385 * - Many more widths might be supported ... and we can easily
1386 * check whether our setting "took".
1388 * - The "clock" and "mode" bits are interpreted differently.
1389 * See ARM IHI 0014O table 2-17 for the old behavior, and
1390 * table 2-18 for the new. With ETB it's best to specify
1394 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[1], port_width
);
1397 /* before ETMv3.0 */
1399 portmode
|= ETM_PORT_4BIT
;
1402 portmode
|= ETM_PORT_8BIT
;
1405 portmode
|= ETM_PORT_16BIT
;
1407 /* ETMv3.0 and later*/
1409 portmode
|= ETM_PORT_24BIT
;
1412 portmode
|= ETM_PORT_32BIT
;
1415 portmode
|= ETM_PORT_48BIT
;
1418 portmode
|= ETM_PORT_64BIT
;
1421 portmode
|= ETM_PORT_1BIT
;
1424 portmode
|= ETM_PORT_2BIT
;
1427 command_print(CMD_CTX
,
1428 "unsupported ETM port width '%s'", CMD_ARGV
[1]);
1432 if (strcmp("normal", CMD_ARGV
[2]) == 0)
1434 portmode
|= ETM_PORT_NORMAL
;
1436 else if (strcmp("multiplexed", CMD_ARGV
[2]) == 0)
1438 portmode
|= ETM_PORT_MUXED
;
1440 else if (strcmp("demultiplexed", CMD_ARGV
[2]) == 0)
1442 portmode
|= ETM_PORT_DEMUXED
;
1446 command_print(CMD_CTX
, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV
[2]);
1450 if (strcmp("half", CMD_ARGV
[3]) == 0)
1452 portmode
|= ETM_PORT_HALF_CLOCK
;
1454 else if (strcmp("full", CMD_ARGV
[3]) == 0)
1456 portmode
|= ETM_PORT_FULL_CLOCK
;
1460 command_print(CMD_CTX
, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV
[3]);
1464 etm_ctx
= calloc(1, sizeof(struct etm_context
));
1466 LOG_DEBUG("out of memory");
1470 for (i
= 0; etm_capture_drivers
[i
]; i
++)
1472 if (strcmp(CMD_ARGV
[4], etm_capture_drivers
[i
]->name
) == 0)
1474 int retval
= register_commands(CMD_CTX
, NULL
,
1475 etm_capture_drivers
[i
]->commands
);
1476 if (ERROR_OK
!= retval
)
1482 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1488 if (!etm_capture_drivers
[i
])
1490 /* no supported capture driver found, don't register an ETM */
1492 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV
[4]);
1496 etm_ctx
->target
= target
;
1497 etm_ctx
->trace_data
= NULL
;
1498 etm_ctx
->portmode
= portmode
;
1499 etm_ctx
->core_state
= ARM_STATE_ARM
;
1503 return etm_register_user_commands(CMD_CTX
);
1506 COMMAND_HANDLER(handle_etm_info_command
)
1508 struct target
*target
;
1510 struct etm_context
*etm
;
1511 struct reg
*etm_sys_config_reg
;
1515 target
= get_current_target(CMD_CTX
);
1516 arm
= target_to_arm(target
);
1519 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1526 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1530 command_print(CMD_CTX
, "ETM v%d.%d",
1531 etm
->bcd_vers
>> 4, etm
->bcd_vers
& 0xf);
1532 command_print(CMD_CTX
, "pairs of address comparators: %i",
1533 (int) (etm
->config
>> 0) & 0x0f);
1534 command_print(CMD_CTX
, "data comparators: %i",
1535 (int) (etm
->config
>> 4) & 0x0f);
1536 command_print(CMD_CTX
, "memory map decoders: %i",
1537 (int) (etm
->config
>> 8) & 0x1f);
1538 command_print(CMD_CTX
, "number of counters: %i",
1539 (int) (etm
->config
>> 13) & 0x07);
1540 command_print(CMD_CTX
, "sequencer %spresent",
1541 (int) (etm
->config
& (1 << 16)) ? "" : "not ");
1542 command_print(CMD_CTX
, "number of ext. inputs: %i",
1543 (int) (etm
->config
>> 17) & 0x07);
1544 command_print(CMD_CTX
, "number of ext. outputs: %i",
1545 (int) (etm
->config
>> 20) & 0x07);
1546 command_print(CMD_CTX
, "FIFO full %spresent",
1547 (int) (etm
->config
& (1 << 23)) ? "" : "not ");
1548 if (etm
->bcd_vers
< 0x20)
1549 command_print(CMD_CTX
, "protocol version: %i",
1550 (int) (etm
->config
>> 28) & 0x07);
1552 command_print(CMD_CTX
,
1553 "coprocessor and memory access %ssupported",
1554 (etm
->config
& (1 << 26)) ? "" : "not ");
1555 command_print(CMD_CTX
, "trace start/stop %spresent",
1556 (etm
->config
& (1 << 26)) ? "" : "not ");
1557 command_print(CMD_CTX
, "number of context comparators: %i",
1558 (int) (etm
->config
>> 24) & 0x03);
1561 /* SYS_CONFIG isn't present before ETMv1.2 */
1562 etm_sys_config_reg
= etm_reg_lookup(etm
, ETM_SYS_CONFIG
);
1563 if (!etm_sys_config_reg
)
1566 etm_get_reg(etm_sys_config_reg
);
1567 config
= buf_get_u32(etm_sys_config_reg
->value
, 0, 32);
1569 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config
);
1571 max_port_size
= config
& 0x7;
1572 if (etm
->bcd_vers
>= 0x30)
1573 max_port_size
|= (config
>> 6) & 0x08;
1574 switch (max_port_size
)
1576 /* before ETMv3.0 */
1586 /* ETMv3.0 and later*/
1606 LOG_ERROR("Illegal max_port_size");
1609 command_print(CMD_CTX
, "max. port size: %i", max_port_size
);
1611 if (etm
->bcd_vers
< 0x30) {
1612 command_print(CMD_CTX
, "half-rate clocking %ssupported",
1613 (config
& (1 << 3)) ? "" : "not ");
1614 command_print(CMD_CTX
, "full-rate clocking %ssupported",
1615 (config
& (1 << 4)) ? "" : "not ");
1616 command_print(CMD_CTX
, "normal trace format %ssupported",
1617 (config
& (1 << 5)) ? "" : "not ");
1618 command_print(CMD_CTX
, "multiplex trace format %ssupported",
1619 (config
& (1 << 6)) ? "" : "not ");
1620 command_print(CMD_CTX
, "demultiplex trace format %ssupported",
1621 (config
& (1 << 7)) ? "" : "not ");
1623 /* REVISIT show which size and format are selected ... */
1624 command_print(CMD_CTX
, "current port size %ssupported",
1625 (config
& (1 << 10)) ? "" : "not ");
1626 command_print(CMD_CTX
, "current trace format %ssupported",
1627 (config
& (1 << 11)) ? "" : "not ");
1629 if (etm
->bcd_vers
>= 0x21)
1630 command_print(CMD_CTX
, "fetch comparisons %ssupported",
1631 (config
& (1 << 17)) ? "not " : "");
1632 command_print(CMD_CTX
, "FIFO full %ssupported",
1633 (config
& (1 << 8)) ? "" : "not ");
1638 COMMAND_HANDLER(handle_etm_status_command
)
1640 struct target
*target
;
1642 struct etm_context
*etm
;
1643 trace_status_t trace_status
;
1645 target
= get_current_target(CMD_CTX
);
1646 arm
= target_to_arm(target
);
1649 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1656 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1661 if (etm
->bcd_vers
>= 0x11) {
1664 reg
= etm_reg_lookup(etm
, ETM_STATUS
);
1667 if (etm_get_reg(reg
) == ERROR_OK
) {
1668 unsigned s
= buf_get_u32(reg
->value
, 0, reg
->size
);
1670 command_print(CMD_CTX
, "etm: %s%s%s%s",
1671 /* bit(1) == progbit */
1672 (etm
->bcd_vers
>= 0x12)
1674 ? "disabled" : "enabled")
1676 ((s
& (1 << 3)) && etm
->bcd_vers
>= 0x31)
1677 ? " triggered" : "",
1678 ((s
& (1 << 2)) && etm
->bcd_vers
>= 0x12)
1679 ? " start/stop" : "",
1680 ((s
& (1 << 0)) && etm
->bcd_vers
>= 0x11)
1681 ? " untraced-overflow" : "");
1682 } /* else ignore and try showing trace port status */
1685 /* Trace Port Driver status */
1686 trace_status
= etm
->capture_driver
->status(etm
);
1687 if (trace_status
== TRACE_IDLE
)
1689 command_print(CMD_CTX
, "%s: idle", etm
->capture_driver
->name
);
1693 static char *completed
= " completed";
1694 static char *running
= " is running";
1695 static char *overflowed
= ", overflowed";
1696 static char *triggered
= ", triggered";
1698 command_print(CMD_CTX
, "%s: trace collection%s%s%s",
1699 etm
->capture_driver
->name
,
1700 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1701 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1702 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1704 if (etm
->trace_depth
> 0)
1706 command_print(CMD_CTX
, "%i frames of trace data read",
1707 (int)(etm
->trace_depth
));
1714 COMMAND_HANDLER(handle_etm_image_command
)
1716 struct target
*target
;
1718 struct etm_context
*etm_ctx
;
1722 command_print(CMD_CTX
, "usage: etm image <file> [base address] [type]");
1726 target
= get_current_target(CMD_CTX
);
1727 arm
= target_to_arm(target
);
1730 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1737 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1743 image_close(etm_ctx
->image
);
1744 free(etm_ctx
->image
);
1745 command_print(CMD_CTX
, "previously loaded image found and closed");
1748 etm_ctx
->image
= malloc(sizeof(struct image
));
1749 etm_ctx
->image
->base_address_set
= 0;
1750 etm_ctx
->image
->start_address_set
= 0;
1752 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1755 etm_ctx
->image
->base_address_set
= 1;
1756 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], etm_ctx
->image
->base_address
);
1760 etm_ctx
->image
->base_address_set
= 0;
1763 if (image_open(etm_ctx
->image
, CMD_ARGV
[0], (CMD_ARGC
>= 3) ? CMD_ARGV
[2] : NULL
) != ERROR_OK
)
1765 free(etm_ctx
->image
);
1766 etm_ctx
->image
= NULL
;
1773 COMMAND_HANDLER(handle_etm_dump_command
)
1776 struct target
*target
;
1778 struct etm_context
*etm_ctx
;
1783 command_print(CMD_CTX
, "usage: etm dump <file>");
1787 target
= get_current_target(CMD_CTX
);
1788 arm
= target_to_arm(target
);
1791 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1798 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1802 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
)
1804 command_print(CMD_CTX
, "trace capture wasn't enabled, no trace data captured");
1808 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1810 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1811 command_print(CMD_CTX
, "trace capture not completed");
1815 /* read the trace data if it wasn't read already */
1816 if (etm_ctx
->trace_depth
== 0)
1817 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1819 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1824 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1825 fileio_write_u32(&file
, etm_ctx
->portmode
);
1826 fileio_write_u32(&file
, etm_ctx
->tracemode
);
1827 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1829 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1831 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1832 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1833 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1836 fileio_close(&file
);
1841 COMMAND_HANDLER(handle_etm_load_command
)
1844 struct target
*target
;
1846 struct etm_context
*etm_ctx
;
1851 command_print(CMD_CTX
, "usage: etm load <file>");
1855 target
= get_current_target(CMD_CTX
);
1856 arm
= target_to_arm(target
);
1859 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1866 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1870 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1872 command_print(CMD_CTX
, "trace capture running, stop first");
1876 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1883 command_print(CMD_CTX
, "size isn't a multiple of 4, no valid trace data");
1884 fileio_close(&file
);
1888 if (etm_ctx
->trace_depth
> 0)
1890 free(etm_ctx
->trace_data
);
1891 etm_ctx
->trace_data
= NULL
;
1896 fileio_read_u32(&file
, &tmp
); etm_ctx
->capture_status
= tmp
;
1897 fileio_read_u32(&file
, &tmp
); etm_ctx
->portmode
= tmp
;
1898 fileio_read_u32(&file
, &tmp
); etm_ctx
->tracemode
= tmp
;
1899 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1901 etm_ctx
->trace_data
= malloc(sizeof(struct etmv1_trace_data
) * etm_ctx
->trace_depth
);
1902 if (etm_ctx
->trace_data
== NULL
)
1904 command_print(CMD_CTX
, "not enough memory to perform operation");
1905 fileio_close(&file
);
1909 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1911 uint32_t pipestat
, packet
, flags
;
1912 fileio_read_u32(&file
, &pipestat
);
1913 fileio_read_u32(&file
, &packet
);
1914 fileio_read_u32(&file
, &flags
);
1915 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1916 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1917 etm_ctx
->trace_data
[i
].flags
= flags
;
1920 fileio_close(&file
);
1925 COMMAND_HANDLER(handle_etm_start_command
)
1927 struct target
*target
;
1929 struct etm_context
*etm_ctx
;
1930 struct reg
*etm_ctrl_reg
;
1932 target
= get_current_target(CMD_CTX
);
1933 arm
= target_to_arm(target
);
1936 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1943 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1947 /* invalidate old tracing data */
1948 etm_ctx
->capture_status
= TRACE_IDLE
;
1949 if (etm_ctx
->trace_depth
> 0)
1951 free(etm_ctx
->trace_data
);
1952 etm_ctx
->trace_data
= NULL
;
1954 etm_ctx
->trace_depth
= 0;
1956 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1960 etm_get_reg(etm_ctrl_reg
);
1962 /* Clear programming bit (10), set port selection bit (11) */
1963 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1965 etm_store_reg(etm_ctrl_reg
);
1966 jtag_execute_queue();
1968 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1973 COMMAND_HANDLER(handle_etm_stop_command
)
1975 struct target
*target
;
1977 struct etm_context
*etm_ctx
;
1978 struct reg
*etm_ctrl_reg
;
1980 target
= get_current_target(CMD_CTX
);
1981 arm
= target_to_arm(target
);
1984 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1991 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1995 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1999 etm_get_reg(etm_ctrl_reg
);
2001 /* Set programming bit (10), clear port selection bit (11) */
2002 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
2004 etm_store_reg(etm_ctrl_reg
);
2005 jtag_execute_queue();
2007 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
2012 COMMAND_HANDLER(handle_etm_analyze_command
)
2014 struct target
*target
;
2016 struct etm_context
*etm_ctx
;
2019 target
= get_current_target(CMD_CTX
);
2020 arm
= target_to_arm(target
);
2023 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
2030 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
2034 if ((retval
= etmv1_analyze_trace(etm_ctx
, CMD_CTX
)) != ERROR_OK
)
2038 case ERROR_ETM_ANALYSIS_FAILED
:
2039 command_print(CMD_CTX
, "further analysis failed (corrupted trace data or just end of data");
2041 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE
:
2042 command_print(CMD_CTX
, "no instruction for current address available, analysis aborted");
2044 case ERROR_TRACE_IMAGE_UNAVAILABLE
:
2045 command_print(CMD_CTX
, "no image available for trace analysis");
2048 command_print(CMD_CTX
, "unknown error: %i", retval
);
2055 static const struct command_registration etm_config_command_handlers
[] = {
2058 .handler
= &handle_etm_config_command
,
2059 .mode
= COMMAND_CONFIG
,
2060 .usage
= "<target> <port_width> <port_mode> "
2061 "<clocking> <capture_driver>",
2063 COMMAND_REGISTRATION_DONE
2065 const struct command_registration etm_command_handlers
[] = {
2068 .mode
= COMMAND_ANY
,
2069 .help
= "Emebdded Trace Macrocell command group",
2070 .chain
= etm_config_command_handlers
,
2072 COMMAND_REGISTRATION_DONE
2075 static const struct command_registration etm_exec_command_handlers
[] = {
2077 .name
= "tracemode", handle_etm_tracemode_command
,
2078 .mode
= COMMAND_EXEC
,
2079 .help
= "configure/display trace mode",
2080 .usage
= "<none | data | address | all> "
2081 "<context_id_bits> <cycle_accurate> <branch_output>",
2085 .handler
= &handle_etm_info_command
,
2086 .mode
= COMMAND_EXEC
,
2087 .help
= "display info about the current target's ETM",
2091 .handler
= &handle_etm_status_command
,
2092 .mode
= COMMAND_EXEC
,
2093 .help
= "display current target's ETM status",
2097 .handler
= &handle_etm_start_command
,
2098 .mode
= COMMAND_EXEC
,
2099 .help
= "start ETM trace collection",
2103 .handler
= &handle_etm_stop_command
,
2104 .mode
= COMMAND_EXEC
,
2105 .help
= "stop ETM trace collection",
2109 .handler
= &handle_etm_analyze_command
,
2110 .mode
= COMMAND_EXEC
,
2111 .help
= "anaylze collected ETM trace",
2115 .handler
= &handle_etm_image_command
,
2116 .mode
= COMMAND_EXEC
,
2117 .help
= "load image from <file> [base address]",
2121 .handler
= &handle_etm_dump_command
,
2122 .mode
= COMMAND_EXEC
,
2123 .help
= "dump captured trace data <file>",
2127 .handler
= &handle_etm_load_command
,
2128 .mode
= COMMAND_EXEC
,
2129 .help
= "load trace data for analysis <file>",
2131 COMMAND_REGISTRATION_DONE
2134 static int etm_register_user_commands(struct command_context
*cmd_ctx
)
2136 struct command
*etm_cmd
= command_find_in_context(cmd_ctx
, "etm");
2137 return register_commands(cmd_ctx
, etm_cmd
, etm_exec_command_handlers
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)