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[openocd.git] / src / target / etm.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm.h"
25 #include "etm.h"
26 #include "etb.h"
27 #include "image.h"
28 #include "arm_disassembler.h"
29 #include "register.h"
30 #include "etm_dummy.h"
31
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
34 #endif
35
36
37 /*
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
39 *
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
43 *
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
48 *
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
52 *
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
57 */
58
59 enum {
60 RO, /* read/only */
61 WO, /* write/only */
62 RW, /* read/write */
63 };
64
65 struct etm_reg_info {
66 uint8_t addr;
67 uint8_t size; /* low-N of 32 bits */
68 uint8_t mode; /* RO, WO, RW */
69 uint8_t bcd_vers; /* 1.0, 2.0, etc */
70 char *name;
71 };
72
73 /*
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
78 */
79
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
84 { ETM_ID, 32, RO, 0x20, "ETM_id", },
85 };
86
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
95
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
101
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
107
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
109
110 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
115 };
116
117 static const struct etm_reg_info etm_fifofull[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
121 };
122
123 static const struct etm_reg_info etm_addr_comp[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
130 ADDR_COMPARATOR(1),
131 ADDR_COMPARATOR(2),
132 ADDR_COMPARATOR(3),
133 ADDR_COMPARATOR(4),
134 ADDR_COMPARATOR(5),
135 ADDR_COMPARATOR(6),
136 ADDR_COMPARATOR(7),
137 ADDR_COMPARATOR(8),
138
139 ADDR_COMPARATOR(9),
140 ADDR_COMPARATOR(10),
141 ADDR_COMPARATOR(11),
142 ADDR_COMPARATOR(12),
143 ADDR_COMPARATOR(13),
144 ADDR_COMPARATOR(14),
145 ADDR_COMPARATOR(15),
146 ADDR_COMPARATOR(16),
147 #undef ADDR_COMPARATOR
148 };
149
150 static const struct etm_reg_info etm_data_comp[] = {
151 /* Data Value Comparators (NOTE: odd addresses are reserved) */
152 #define DATA_COMPARATOR(i) \
153 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
154 "ETM_data_" #i "_comparator_value", }, \
155 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
156 "ETM_data_" #i "_comparator_mask", }
157 DATA_COMPARATOR(1),
158 DATA_COMPARATOR(2),
159 DATA_COMPARATOR(3),
160 DATA_COMPARATOR(4),
161 DATA_COMPARATOR(5),
162 DATA_COMPARATOR(6),
163 DATA_COMPARATOR(7),
164 DATA_COMPARATOR(8),
165 #undef DATA_COMPARATOR
166 };
167
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
178 ETM_COUNTER(1),
179 ETM_COUNTER(2),
180 ETM_COUNTER(3),
181 ETM_COUNTER(4),
182 #undef ETM_COUNTER
183 };
184
185 static const struct etm_reg_info etm_sequencer[] = {
186 #define ETM_SEQ(i) \
187 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
188 "ETM_sequencer_event" #i, }
189 ETM_SEQ(0), /* 1->2 */
190 ETM_SEQ(1), /* 2->1 */
191 ETM_SEQ(2), /* 2->3 */
192 ETM_SEQ(3), /* 3->1 */
193 ETM_SEQ(4), /* 3->2 */
194 ETM_SEQ(5), /* 1->3 */
195 #undef ETM_SEQ
196 /* 0x66 reserved */
197 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
198 };
199
200 static const struct etm_reg_info etm_outputs[] = {
201 #define ETM_OUTPUT(i) \
202 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
203 "ETM_external_output" #i, }
204
205 ETM_OUTPUT(1),
206 ETM_OUTPUT(2),
207 ETM_OUTPUT(3),
208 ETM_OUTPUT(4),
209 #undef ETM_OUTPUT
210 };
211
212 #if 0
213 /* registers from 0x6c..0x7f were added after ETMv1.3 */
214
215 /* Context ID Comparators */
216 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
217 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
218 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
219 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
220 #endif
221
222 static int etm_get_reg(struct reg *reg);
223 static int etm_read_reg_w_check(struct reg *reg,
224 uint8_t* check_value, uint8_t* check_mask);
225 static int etm_register_user_commands(struct command_context *cmd_ctx);
226 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
227 static int etm_write_reg(struct reg *reg, uint32_t value);
228
229 static const struct reg_arch_type etm_scan6_type = {
230 .get = etm_get_reg,
231 .set = etm_set_reg_w_exec,
232 };
233
234 /* Look up register by ID ... most ETM instances only
235 * support a subset of the possible registers.
236 */
237 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
238 {
239 struct reg_cache *cache = etm_ctx->reg_cache;
240 unsigned i;
241
242 for (i = 0; i < cache->num_regs; i++) {
243 struct etm_reg *reg = cache->reg_list[i].arch_info;
244
245 if (reg->reg_info->addr == id)
246 return &cache->reg_list[i];
247 }
248
249 /* caller asking for nonexistent register is a bug! */
250 /* REVISIT say which of the N targets was involved */
251 LOG_ERROR("ETM: register 0x%02x not available", id);
252 return NULL;
253 }
254
255 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
256 struct reg_cache *cache, struct etm_reg *ereg,
257 const struct etm_reg_info *r, unsigned nreg)
258 {
259 struct reg *reg = cache->reg_list;
260
261 reg += cache->num_regs;
262 ereg += cache->num_regs;
263
264 /* add up to "nreg" registers from "r", if supported by this
265 * version of the ETM, to the specified cache.
266 */
267 for (; nreg--; r++) {
268
269 /* this ETM may be too old to have some registers */
270 if (r->bcd_vers > bcd_vers)
271 continue;
272
273 reg->name = r->name;
274 reg->size = r->size;
275 reg->value = &ereg->value;
276 reg->arch_info = ereg;
277 reg->type = &etm_scan6_type;
278 reg++;
279 cache->num_regs++;
280
281 ereg->reg_info = r;
282 ereg->jtag_info = jtag_info;
283 ereg++;
284 }
285 }
286
287 struct reg_cache *etm_build_reg_cache(struct target *target,
288 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
289 {
290 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
291 struct reg *reg_list = NULL;
292 struct etm_reg *arch_info = NULL;
293 unsigned bcd_vers, config;
294
295 /* the actual registers are kept in two arrays */
296 reg_list = calloc(128, sizeof(struct reg));
297 arch_info = calloc(128, sizeof(struct etm_reg));
298
299 /* fill in values for the reg cache */
300 reg_cache->name = "etm registers";
301 reg_cache->next = NULL;
302 reg_cache->reg_list = reg_list;
303 reg_cache->num_regs = 0;
304
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
307 */
308 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
309 etm_core, 1);
310
311 etm_get_reg(reg_list);
312 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
313 config = etm_ctx->config;
314
315 /* figure ETM version then add base registers */
316 if (config & (1 << 31)) {
317 bcd_vers = 0x20;
318 LOG_WARNING("ETMv2+ support is incomplete");
319
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
324 */
325 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
326 etm_core + 1, 1);
327 etm_get_reg(reg_list + 1);
328 etm_ctx->id = buf_get_u32(
329 (void *)&arch_info[1].value, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
331 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
332
333 } else {
334 switch (config >> 28) {
335 case 7:
336 case 5:
337 case 3:
338 bcd_vers = 0x13;
339 break;
340 case 4:
341 case 2:
342 bcd_vers = 0x12;
343 break;
344 case 1:
345 bcd_vers = 0x11;
346 break;
347 case 0:
348 bcd_vers = 0x10;
349 break;
350 default:
351 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
352 goto fail;
353 }
354 }
355 etm_ctx->bcd_vers = bcd_vers;
356 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
357
358 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
359 etm_basic, ARRAY_SIZE(etm_basic));
360
361 /* address and data comparators; counters; outputs */
362 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
363 etm_addr_comp, 4 * (0x0f & (config >> 0)));
364 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
365 etm_data_comp, 2 * (0x0f & (config >> 4)));
366 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
367 etm_counters, 4 * (0x07 & (config >> 13)));
368 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
369 etm_outputs, (0x07 & (config >> 20)));
370
371 /* FIFOFULL presence is optional
372 * REVISIT for ETMv1.2 and later, don't bother adding this
373 * unless ETM_SYS_CONFIG says it's also *supported* ...
374 */
375 if (config & (1 << 23))
376 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
377 etm_fifofull, ARRAY_SIZE(etm_fifofull));
378
379 /* sequencer is optional (for state-dependant triggering) */
380 if (config & (1 << 16))
381 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
382 etm_sequencer, ARRAY_SIZE(etm_sequencer));
383
384 /* REVISIT could realloc and likely save half the memory
385 * in the two chunks we allocated...
386 */
387
388 /* the ETM might have an ETB connected */
389 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
390 {
391 struct etb *etb = etm_ctx->capture_driver_priv;
392
393 if (!etb)
394 {
395 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
396 goto fail;
397 }
398
399 reg_cache->next = etb_build_reg_cache(etb);
400
401 etb->reg_cache = reg_cache->next;
402 }
403
404 etm_ctx->reg_cache = reg_cache;
405 return reg_cache;
406
407 fail:
408 free(reg_cache);
409 free(reg_list);
410 free(arch_info);
411 return NULL;
412 }
413
414 static int etm_read_reg(struct reg *reg)
415 {
416 return etm_read_reg_w_check(reg, NULL, NULL);
417 }
418
419 static int etm_store_reg(struct reg *reg)
420 {
421 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
422 }
423
424 int etm_setup(struct target *target)
425 {
426 int retval;
427 uint32_t etm_ctrl_value;
428 struct arm *arm = target_to_arm(target);
429 struct etm_context *etm_ctx = arm->etm;
430 struct reg *etm_ctrl_reg;
431
432 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
433 if (!etm_ctrl_reg)
434 return ERROR_OK;
435
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg);
438 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
439
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value &= ~0x1;
442
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
445 */
446 etm_ctrl_value = (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
449 & ~ETM_PORT_CLOCK_MASK)
450 | etm_ctx->portmode;
451
452 buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
453 etm_store_reg(etm_ctrl_reg);
454
455 if ((retval = jtag_execute_queue()) != ERROR_OK)
456 return retval;
457
458 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
459 * verify that those width and mode settings are OK ...
460 */
461
462 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
463 {
464 LOG_ERROR("ETM capture driver initialization failed");
465 return retval;
466 }
467 return ERROR_OK;
468 }
469
470 static int etm_get_reg(struct reg *reg)
471 {
472 int retval;
473
474 if ((retval = etm_read_reg(reg)) != ERROR_OK)
475 {
476 LOG_ERROR("BUG: error scheduling etm register read");
477 return retval;
478 }
479
480 if ((retval = jtag_execute_queue()) != ERROR_OK)
481 {
482 LOG_ERROR("register read failed");
483 return retval;
484 }
485
486 return ERROR_OK;
487 }
488
489 static int etm_read_reg_w_check(struct reg *reg,
490 uint8_t* check_value, uint8_t* check_mask)
491 {
492 struct etm_reg *etm_reg = reg->arch_info;
493 const struct etm_reg_info *r = etm_reg->reg_info;
494 uint8_t reg_addr = r->addr & 0x7f;
495 struct scan_field fields[3];
496
497 if (etm_reg->reg_info->mode == WO) {
498 LOG_ERROR("BUG: can't read write-only register %s", r->name);
499 return ERROR_INVALID_ARGUMENTS;
500 }
501
502 LOG_DEBUG("%s (%u)", r->name, reg_addr);
503
504 jtag_set_end_state(TAP_IDLE);
505 arm_jtag_scann(etm_reg->jtag_info, 0x6);
506 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
507
508 fields[0].tap = etm_reg->jtag_info->tap;
509 fields[0].num_bits = 32;
510 fields[0].out_value = reg->value;
511 fields[0].in_value = NULL;
512 fields[0].check_value = NULL;
513 fields[0].check_mask = NULL;
514
515 fields[1].tap = etm_reg->jtag_info->tap;
516 fields[1].num_bits = 7;
517 fields[1].out_value = malloc(1);
518 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
519 fields[1].in_value = NULL;
520 fields[1].check_value = NULL;
521 fields[1].check_mask = NULL;
522
523 fields[2].tap = etm_reg->jtag_info->tap;
524 fields[2].num_bits = 1;
525 fields[2].out_value = malloc(1);
526 buf_set_u32(fields[2].out_value, 0, 1, 0);
527 fields[2].in_value = NULL;
528 fields[2].check_value = NULL;
529 fields[2].check_mask = NULL;
530
531 jtag_add_dr_scan(3, fields, jtag_get_end_state());
532
533 fields[0].in_value = reg->value;
534 fields[0].check_value = check_value;
535 fields[0].check_mask = check_mask;
536
537 jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
538
539 free(fields[1].out_value);
540 free(fields[2].out_value);
541
542 return ERROR_OK;
543 }
544
545 static int etm_set_reg(struct reg *reg, uint32_t value)
546 {
547 int retval;
548
549 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
550 {
551 LOG_ERROR("BUG: error scheduling etm register write");
552 return retval;
553 }
554
555 buf_set_u32(reg->value, 0, reg->size, value);
556 reg->valid = 1;
557 reg->dirty = 0;
558
559 return ERROR_OK;
560 }
561
562 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
563 {
564 int retval;
565
566 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
567
568 if ((retval = jtag_execute_queue()) != ERROR_OK)
569 {
570 LOG_ERROR("register write failed");
571 return retval;
572 }
573 return ERROR_OK;
574 }
575
576 static int etm_write_reg(struct reg *reg, uint32_t value)
577 {
578 struct etm_reg *etm_reg = reg->arch_info;
579 const struct etm_reg_info *r = etm_reg->reg_info;
580 uint8_t reg_addr = r->addr & 0x7f;
581 struct scan_field fields[3];
582
583 if (etm_reg->reg_info->mode == RO) {
584 LOG_ERROR("BUG: can't write read--only register %s", r->name);
585 return ERROR_INVALID_ARGUMENTS;
586 }
587
588 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
589
590 jtag_set_end_state(TAP_IDLE);
591 arm_jtag_scann(etm_reg->jtag_info, 0x6);
592 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
593
594 fields[0].tap = etm_reg->jtag_info->tap;
595 fields[0].num_bits = 32;
596 uint8_t tmp1[4];
597 fields[0].out_value = tmp1;
598 buf_set_u32(fields[0].out_value, 0, 32, value);
599 fields[0].in_value = NULL;
600
601 fields[1].tap = etm_reg->jtag_info->tap;
602 fields[1].num_bits = 7;
603 uint8_t tmp2;
604 fields[1].out_value = &tmp2;
605 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
606 fields[1].in_value = NULL;
607
608 fields[2].tap = etm_reg->jtag_info->tap;
609 fields[2].num_bits = 1;
610 uint8_t tmp3;
611 fields[2].out_value = &tmp3;
612 buf_set_u32(fields[2].out_value, 0, 1, 1);
613 fields[2].in_value = NULL;
614
615 jtag_add_dr_scan(3, fields, jtag_get_end_state());
616
617 return ERROR_OK;
618 }
619
620
621 /* ETM trace analysis functionality */
622
623 static struct etm_capture_driver *etm_capture_drivers[] =
624 {
625 &etb_capture_driver,
626 &etm_dummy_capture_driver,
627 #if BUILD_OOCD_TRACE == 1
628 &oocd_trace_capture_driver,
629 #endif
630 NULL
631 };
632
633 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
634 {
635 int i;
636 int section = -1;
637 size_t size_read;
638 uint32_t opcode;
639 int retval;
640
641 if (!ctx->image)
642 return ERROR_TRACE_IMAGE_UNAVAILABLE;
643
644 /* search for the section the current instruction belongs to */
645 for (i = 0; i < ctx->image->num_sections; i++)
646 {
647 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
648 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
649 {
650 section = i;
651 break;
652 }
653 }
654
655 if (section == -1)
656 {
657 /* current instruction couldn't be found in the image */
658 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
659 }
660
661 if (ctx->core_state == ARM_STATE_ARM)
662 {
663 uint8_t buf[4];
664 if ((retval = image_read_section(ctx->image, section,
665 ctx->current_pc - ctx->image->sections[section].base_address,
666 4, buf, &size_read)) != ERROR_OK)
667 {
668 LOG_ERROR("error while reading instruction: %i", retval);
669 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
670 }
671 opcode = target_buffer_get_u32(ctx->target, buf);
672 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
673 }
674 else if (ctx->core_state == ARM_STATE_THUMB)
675 {
676 uint8_t buf[2];
677 if ((retval = image_read_section(ctx->image, section,
678 ctx->current_pc - ctx->image->sections[section].base_address,
679 2, buf, &size_read)) != ERROR_OK)
680 {
681 LOG_ERROR("error while reading instruction: %i", retval);
682 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
683 }
684 opcode = target_buffer_get_u16(ctx->target, buf);
685 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
686 }
687 else if (ctx->core_state == ARM_STATE_JAZELLE)
688 {
689 LOG_ERROR("BUG: tracing of jazelle code not supported");
690 return ERROR_FAIL;
691 }
692 else
693 {
694 LOG_ERROR("BUG: unknown core state encountered");
695 return ERROR_FAIL;
696 }
697
698 return ERROR_OK;
699 }
700
701 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
702 {
703 while (ctx->data_index < ctx->trace_depth)
704 {
705 /* if the caller specified an address packet offset, skip until the
706 * we reach the n-th cycle marked with tracesync */
707 if (apo > 0)
708 {
709 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
710 apo--;
711
712 if (apo > 0)
713 {
714 ctx->data_index++;
715 ctx->data_half = 0;
716 }
717 continue;
718 }
719
720 /* no tracedata output during a TD cycle
721 * or in a trigger cycle */
722 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
723 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
724 {
725 ctx->data_index++;
726 ctx->data_half = 0;
727 continue;
728 }
729
730 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
731 {
732 if (ctx->data_half == 0)
733 {
734 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
735 ctx->data_half = 1;
736 }
737 else
738 {
739 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
740 ctx->data_half = 0;
741 ctx->data_index++;
742 }
743 }
744 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
745 {
746 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
747 ctx->data_index++;
748 }
749 else
750 {
751 /* on a 4-bit port, a packet will be output during two consecutive cycles */
752 if (ctx->data_index > (ctx->trace_depth - 2))
753 return -1;
754
755 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
756 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
757 ctx->data_index += 2;
758 }
759
760 return 0;
761 }
762
763 return -1;
764 }
765
766 static int etmv1_branch_address(struct etm_context *ctx)
767 {
768 int retval;
769 uint8_t packet;
770 int shift = 0;
771 int apo;
772 uint32_t i;
773
774 /* quit analysis if less than two cycles are left in the trace
775 * because we can't extract the APO */
776 if (ctx->data_index > (ctx->trace_depth - 2))
777 return -1;
778
779 /* a BE could be output during an APO cycle, skip the current
780 * and continue with the new one */
781 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
782 return 1;
783 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
784 return 2;
785
786 /* address packet offset encoded in the next two cycles' pipestat bits */
787 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
788 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
789
790 /* count number of tracesync cycles between current pipe_index and data_index
791 * i.e. the number of tracesyncs that data_index already passed by
792 * to subtract them from the APO */
793 for (i = ctx->pipe_index; i < ctx->data_index; i++)
794 {
795 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
796 apo--;
797 }
798
799 /* extract up to four 7-bit packets */
800 do {
801 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
802 return -1;
803 ctx->last_branch &= ~(0x7f << shift);
804 ctx->last_branch |= (packet & 0x7f) << shift;
805 shift += 7;
806 } while ((packet & 0x80) && (shift < 28));
807
808 /* one last packet holding 4 bits of the address, plus the branch reason code */
809 if ((shift == 28) && (packet & 0x80))
810 {
811 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
812 return -1;
813 ctx->last_branch &= 0x0fffffff;
814 ctx->last_branch |= (packet & 0x0f) << 28;
815 ctx->last_branch_reason = (packet & 0x70) >> 4;
816 shift += 4;
817 }
818 else
819 {
820 ctx->last_branch_reason = 0;
821 }
822
823 if (shift == 32)
824 {
825 ctx->pc_ok = 1;
826 }
827
828 /* if a full address was output, we might have branched into Jazelle state */
829 if ((shift == 32) && (packet & 0x80))
830 {
831 ctx->core_state = ARM_STATE_JAZELLE;
832 }
833 else
834 {
835 /* if we didn't branch into Jazelle state, the current processor state is
836 * encoded in bit 0 of the branch target address */
837 if (ctx->last_branch & 0x1)
838 {
839 ctx->core_state = ARM_STATE_THUMB;
840 ctx->last_branch &= ~0x1;
841 }
842 else
843 {
844 ctx->core_state = ARM_STATE_ARM;
845 ctx->last_branch &= ~0x3;
846 }
847 }
848
849 return 0;
850 }
851
852 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
853 {
854 int j;
855 uint8_t buf[4];
856 int retval;
857
858 for (j = 0; j < size; j++)
859 {
860 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
861 return -1;
862 }
863
864 if (size == 8)
865 {
866 LOG_ERROR("TODO: add support for 64-bit values");
867 return -1;
868 }
869 else if (size == 4)
870 *data = target_buffer_get_u32(ctx->target, buf);
871 else if (size == 2)
872 *data = target_buffer_get_u16(ctx->target, buf);
873 else if (size == 1)
874 *data = buf[0];
875 else
876 return -1;
877
878 return 0;
879 }
880
881 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
882 {
883 int retval;
884 struct arm_instruction instruction;
885
886 /* read the trace data if it wasn't read already */
887 if (ctx->trace_depth == 0)
888 ctx->capture_driver->read_trace(ctx);
889
890 /* start at the beginning of the captured trace */
891 ctx->pipe_index = 0;
892 ctx->data_index = 0;
893 ctx->data_half = 0;
894
895 /* neither the PC nor the data pointer are valid */
896 ctx->pc_ok = 0;
897 ctx->ptr_ok = 0;
898
899 while (ctx->pipe_index < ctx->trace_depth)
900 {
901 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
902 uint32_t next_pc = ctx->current_pc;
903 uint32_t old_data_index = ctx->data_index;
904 uint32_t old_data_half = ctx->data_half;
905 uint32_t old_index = ctx->pipe_index;
906 uint32_t last_instruction = ctx->last_instruction;
907 uint32_t cycles = 0;
908 int current_pc_ok = ctx->pc_ok;
909
910 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
911 {
912 command_print(cmd_ctx, "--- trigger ---");
913 }
914
915 /* instructions execute in IE/D or BE/D cycles */
916 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
917 ctx->last_instruction = ctx->pipe_index;
918
919 /* if we don't have a valid pc skip until we reach an indirect branch */
920 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
921 {
922 ctx->pipe_index++;
923 continue;
924 }
925
926 /* any indirect branch could have interrupted instruction flow
927 * - the branch reason code could indicate a trace discontinuity
928 * - a branch to the exception vectors indicates an exception
929 */
930 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
931 {
932 /* backup current data index, to be able to consume the branch address
933 * before examining data address and values
934 */
935 old_data_index = ctx->data_index;
936 old_data_half = ctx->data_half;
937
938 ctx->last_instruction = ctx->pipe_index;
939
940 if ((retval = etmv1_branch_address(ctx)) != 0)
941 {
942 /* negative return value from etmv1_branch_address means we ran out of packets,
943 * quit analysing the trace */
944 if (retval < 0)
945 break;
946
947 /* a positive return values means the current branch was abandoned,
948 * and a new branch was encountered in cycle ctx->pipe_index + retval;
949 */
950 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
951 ctx->pipe_index += retval;
952 continue;
953 }
954
955 /* skip over APO cycles */
956 ctx->pipe_index += 2;
957
958 switch (ctx->last_branch_reason)
959 {
960 case 0x0: /* normal PC change */
961 next_pc = ctx->last_branch;
962 break;
963 case 0x1: /* tracing enabled */
964 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
965 ctx->current_pc = ctx->last_branch;
966 ctx->pipe_index++;
967 continue;
968 break;
969 case 0x2: /* trace restarted after FIFO overflow */
970 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
971 ctx->current_pc = ctx->last_branch;
972 ctx->pipe_index++;
973 continue;
974 break;
975 case 0x3: /* exit from debug state */
976 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
977 ctx->current_pc = ctx->last_branch;
978 ctx->pipe_index++;
979 continue;
980 break;
981 case 0x4: /* periodic synchronization point */
982 next_pc = ctx->last_branch;
983 /* if we had no valid PC prior to this synchronization point,
984 * we have to move on with the next trace cycle
985 */
986 if (!current_pc_ok)
987 {
988 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
989 ctx->current_pc = next_pc;
990 ctx->pipe_index++;
991 continue;
992 }
993 break;
994 default: /* reserved */
995 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
996 return ERROR_FAIL;
997 }
998
999 /* if we got here the branch was a normal PC change
1000 * (or a periodic synchronization point, which means the same for that matter)
1001 * if we didn't accquire a complete PC continue with the next cycle
1002 */
1003 if (!ctx->pc_ok)
1004 continue;
1005
1006 /* indirect branch to the exception vector means an exception occured */
1007 if ((ctx->last_branch <= 0x20)
1008 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1009 {
1010 if ((ctx->last_branch & 0xff) == 0x10)
1011 {
1012 command_print(cmd_ctx, "data abort");
1013 }
1014 else
1015 {
1016 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1017 ctx->current_pc = ctx->last_branch;
1018 ctx->pipe_index++;
1019 continue;
1020 }
1021 }
1022 }
1023
1024 /* an instruction was executed (or not, depending on the condition flags)
1025 * retrieve it from the image for displaying */
1026 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1027 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1028 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1029 {
1030 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1031 {
1032 /* can't continue tracing with no image available */
1033 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1034 {
1035 return retval;
1036 }
1037 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1038 {
1039 /* TODO: handle incomplete images
1040 * for now we just quit the analsysis*/
1041 return retval;
1042 }
1043 }
1044
1045 cycles = old_index - last_instruction;
1046 }
1047
1048 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1049 {
1050 uint32_t new_data_index = ctx->data_index;
1051 uint32_t new_data_half = ctx->data_half;
1052
1053 /* in case of a branch with data, the branch target address was consumed before
1054 * we temporarily go back to the saved data index */
1055 if (pipestat == STAT_BD)
1056 {
1057 ctx->data_index = old_data_index;
1058 ctx->data_half = old_data_half;
1059 }
1060
1061 if (ctx->tracemode & ETMV1_TRACE_ADDR)
1062 {
1063 uint8_t packet;
1064 int shift = 0;
1065
1066 do {
1067 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1068 return ERROR_ETM_ANALYSIS_FAILED;
1069 ctx->last_ptr &= ~(0x7f << shift);
1070 ctx->last_ptr |= (packet & 0x7f) << shift;
1071 shift += 7;
1072 } while ((packet & 0x80) && (shift < 32));
1073
1074 if (shift >= 32)
1075 ctx->ptr_ok = 1;
1076
1077 if (ctx->ptr_ok)
1078 {
1079 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1080 }
1081 }
1082
1083 if (ctx->tracemode & ETMV1_TRACE_DATA)
1084 {
1085 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1086 {
1087 int i;
1088 for (i = 0; i < 16; i++)
1089 {
1090 if (instruction.info.load_store_multiple.register_list & (1 << i))
1091 {
1092 uint32_t data;
1093 if (etmv1_data(ctx, 4, &data) != 0)
1094 return ERROR_ETM_ANALYSIS_FAILED;
1095 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1096 }
1097 }
1098 }
1099 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1100 {
1101 uint32_t data;
1102 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1103 return ERROR_ETM_ANALYSIS_FAILED;
1104 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1105 }
1106 }
1107
1108 /* restore data index after consuming BD address and data */
1109 if (pipestat == STAT_BD)
1110 {
1111 ctx->data_index = new_data_index;
1112 ctx->data_half = new_data_half;
1113 }
1114 }
1115
1116 /* adjust PC */
1117 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1118 {
1119 if (((instruction.type == ARM_B) ||
1120 (instruction.type == ARM_BL) ||
1121 (instruction.type == ARM_BLX)) &&
1122 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1123 {
1124 next_pc = instruction.info.b_bl_bx_blx.target_address;
1125 }
1126 else
1127 {
1128 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1129 }
1130 }
1131 else if (pipestat == STAT_IN)
1132 {
1133 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1134 }
1135
1136 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1137 {
1138 char cycles_text[32] = "";
1139
1140 /* if the trace was captured with cycle accurate tracing enabled,
1141 * output the number of cycles since the last executed instruction
1142 */
1143 if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1144 {
1145 snprintf(cycles_text, 32, " (%i %s)",
1146 (int)cycles,
1147 (cycles == 1) ? "cycle" : "cycles");
1148 }
1149
1150 command_print(cmd_ctx, "%s%s%s",
1151 instruction.text,
1152 (pipestat == STAT_IN) ? " (not executed)" : "",
1153 cycles_text);
1154
1155 ctx->current_pc = next_pc;
1156
1157 /* packets for an instruction don't start on or before the preceding
1158 * functional pipestat (i.e. other than WT or TD)
1159 */
1160 if (ctx->data_index <= ctx->pipe_index)
1161 {
1162 ctx->data_index = ctx->pipe_index + 1;
1163 ctx->data_half = 0;
1164 }
1165 }
1166
1167 ctx->pipe_index += 1;
1168 }
1169
1170 return ERROR_OK;
1171 }
1172
1173 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1174 etmv1_tracemode_t *mode)
1175 {
1176 etmv1_tracemode_t tracemode;
1177
1178 /* what parts of data access are traced? */
1179 if (strcmp(CMD_ARGV[0], "none") == 0)
1180 tracemode = ETMV1_TRACE_NONE;
1181 else if (strcmp(CMD_ARGV[0], "data") == 0)
1182 tracemode = ETMV1_TRACE_DATA;
1183 else if (strcmp(CMD_ARGV[0], "address") == 0)
1184 tracemode = ETMV1_TRACE_ADDR;
1185 else if (strcmp(CMD_ARGV[0], "all") == 0)
1186 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1187 else
1188 {
1189 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1190 return ERROR_INVALID_ARGUMENTS;
1191 }
1192
1193 uint8_t context_id;
1194 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1195 switch (context_id)
1196 {
1197 case 0:
1198 tracemode |= ETMV1_CONTEXTID_NONE;
1199 break;
1200 case 8:
1201 tracemode |= ETMV1_CONTEXTID_8;
1202 break;
1203 case 16:
1204 tracemode |= ETMV1_CONTEXTID_16;
1205 break;
1206 case 32:
1207 tracemode |= ETMV1_CONTEXTID_32;
1208 break;
1209 default:
1210 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1211 return ERROR_INVALID_ARGUMENTS;
1212 }
1213
1214 bool etmv1_cycle_accurate;
1215 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1216 if (etmv1_cycle_accurate)
1217 tracemode |= ETMV1_CYCLE_ACCURATE;
1218
1219 bool etmv1_branch_output;
1220 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1221 tracemode |= ETMV1_BRANCH_OUTPUT;
1222
1223 /* IGNORED:
1224 * - CPRT tracing (coprocessor register transfers)
1225 * - debug request (causes debug entry on trigger)
1226 * - stall on FIFOFULL (preventing tracedata lossage)
1227 */
1228 *mode = tracemode;
1229
1230 return ERROR_OK;
1231 }
1232
1233 COMMAND_HANDLER(handle_etm_tracemode_command)
1234 {
1235 struct target *target = get_current_target(CMD_CTX);
1236 struct arm *arm = target_to_arm(target);
1237 struct etm_context *etm;
1238
1239 if (!is_arm(arm)) {
1240 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1241 return ERROR_FAIL;
1242 }
1243
1244 etm = arm->etm;
1245 if (!etm) {
1246 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1247 return ERROR_FAIL;
1248 }
1249
1250 etmv1_tracemode_t tracemode = etm->tracemode;
1251
1252 switch (CMD_ARGC)
1253 {
1254 case 0:
1255 break;
1256 case 4:
1257 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, &tracemode);
1258 break;
1259 default:
1260 command_print(CMD_CTX, "usage: configure trace mode "
1261 "<none | data | address | all> "
1262 "<context id bits> <cycle accurate> <branch output>");
1263 return ERROR_FAIL;
1264 }
1265
1266 /**
1267 * todo: fail if parameters were invalid for this hardware,
1268 * or couldn't be written; display actual hardware state...
1269 */
1270
1271 command_print(CMD_CTX, "current tracemode configuration:");
1272
1273 switch (tracemode & ETMV1_TRACE_MASK)
1274 {
1275 case ETMV1_TRACE_NONE:
1276 command_print(CMD_CTX, "data tracing: none");
1277 break;
1278 case ETMV1_TRACE_DATA:
1279 command_print(CMD_CTX, "data tracing: data only");
1280 break;
1281 case ETMV1_TRACE_ADDR:
1282 command_print(CMD_CTX, "data tracing: address only");
1283 break;
1284 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1285 command_print(CMD_CTX, "data tracing: address and data");
1286 break;
1287 }
1288
1289 switch (tracemode & ETMV1_CONTEXTID_MASK)
1290 {
1291 case ETMV1_CONTEXTID_NONE:
1292 command_print(CMD_CTX, "contextid tracing: none");
1293 break;
1294 case ETMV1_CONTEXTID_8:
1295 command_print(CMD_CTX, "contextid tracing: 8 bit");
1296 break;
1297 case ETMV1_CONTEXTID_16:
1298 command_print(CMD_CTX, "contextid tracing: 16 bit");
1299 break;
1300 case ETMV1_CONTEXTID_32:
1301 command_print(CMD_CTX, "contextid tracing: 32 bit");
1302 break;
1303 }
1304
1305 if (tracemode & ETMV1_CYCLE_ACCURATE)
1306 {
1307 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1308 }
1309 else
1310 {
1311 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1312 }
1313
1314 if (tracemode & ETMV1_BRANCH_OUTPUT)
1315 {
1316 command_print(CMD_CTX, "full branch address output enabled");
1317 }
1318 else
1319 {
1320 command_print(CMD_CTX, "full branch address output disabled");
1321 }
1322
1323 /* only update ETM_CTRL register if tracemode changed */
1324 if (etm->tracemode != tracemode)
1325 {
1326 struct reg *etm_ctrl_reg;
1327
1328 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1329 if (!etm_ctrl_reg)
1330 return ERROR_FAIL;
1331
1332 etm_get_reg(etm_ctrl_reg);
1333
1334 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1335 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1336 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1337 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1338 etm_store_reg(etm_ctrl_reg);
1339
1340 etm->tracemode = tracemode;
1341
1342 /* invalidate old trace data */
1343 etm->capture_status = TRACE_IDLE;
1344 if (etm->trace_depth > 0)
1345 {
1346 free(etm->trace_data);
1347 etm->trace_data = NULL;
1348 }
1349 etm->trace_depth = 0;
1350 }
1351
1352 return ERROR_OK;
1353 }
1354
1355 COMMAND_HANDLER(handle_etm_config_command)
1356 {
1357 struct target *target;
1358 struct arm *arm;
1359 etm_portmode_t portmode = 0x0;
1360 struct etm_context *etm_ctx;
1361 int i;
1362
1363 if (CMD_ARGC != 5)
1364 return ERROR_COMMAND_SYNTAX_ERROR;
1365
1366 target = get_target(CMD_ARGV[0]);
1367 if (!target)
1368 {
1369 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1370 return ERROR_FAIL;
1371 }
1372
1373 arm = target_to_arm(target);
1374 if (!is_arm(arm)) {
1375 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1376 target_name(target),
1377 target_type_name(target));
1378 return ERROR_FAIL;
1379 }
1380
1381 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1382 * version we'll be using!! -- so we can't know how to validate
1383 * params yet. "etm config" should likely be *AFTER* hookup...
1384 *
1385 * - Many more widths might be supported ... and we can easily
1386 * check whether our setting "took".
1387 *
1388 * - The "clock" and "mode" bits are interpreted differently.
1389 * See ARM IHI 0014O table 2-17 for the old behavior, and
1390 * table 2-18 for the new. With ETB it's best to specify
1391 * "normal full" ...
1392 */
1393 uint8_t port_width;
1394 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1395 switch (port_width)
1396 {
1397 /* before ETMv3.0 */
1398 case 4:
1399 portmode |= ETM_PORT_4BIT;
1400 break;
1401 case 8:
1402 portmode |= ETM_PORT_8BIT;
1403 break;
1404 case 16:
1405 portmode |= ETM_PORT_16BIT;
1406 break;
1407 /* ETMv3.0 and later*/
1408 case 24:
1409 portmode |= ETM_PORT_24BIT;
1410 break;
1411 case 32:
1412 portmode |= ETM_PORT_32BIT;
1413 break;
1414 case 48:
1415 portmode |= ETM_PORT_48BIT;
1416 break;
1417 case 64:
1418 portmode |= ETM_PORT_64BIT;
1419 break;
1420 case 1:
1421 portmode |= ETM_PORT_1BIT;
1422 break;
1423 case 2:
1424 portmode |= ETM_PORT_2BIT;
1425 break;
1426 default:
1427 command_print(CMD_CTX,
1428 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1429 return ERROR_FAIL;
1430 }
1431
1432 if (strcmp("normal", CMD_ARGV[2]) == 0)
1433 {
1434 portmode |= ETM_PORT_NORMAL;
1435 }
1436 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1437 {
1438 portmode |= ETM_PORT_MUXED;
1439 }
1440 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1441 {
1442 portmode |= ETM_PORT_DEMUXED;
1443 }
1444 else
1445 {
1446 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1447 return ERROR_FAIL;
1448 }
1449
1450 if (strcmp("half", CMD_ARGV[3]) == 0)
1451 {
1452 portmode |= ETM_PORT_HALF_CLOCK;
1453 }
1454 else if (strcmp("full", CMD_ARGV[3]) == 0)
1455 {
1456 portmode |= ETM_PORT_FULL_CLOCK;
1457 }
1458 else
1459 {
1460 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1461 return ERROR_FAIL;
1462 }
1463
1464 etm_ctx = calloc(1, sizeof(struct etm_context));
1465 if (!etm_ctx) {
1466 LOG_DEBUG("out of memory");
1467 return ERROR_FAIL;
1468 }
1469
1470 for (i = 0; etm_capture_drivers[i]; i++)
1471 {
1472 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1473 {
1474 int retval = register_commands(CMD_CTX, NULL,
1475 etm_capture_drivers[i]->commands);
1476 if (ERROR_OK != retval)
1477 {
1478 free(etm_ctx);
1479 return retval;
1480 }
1481
1482 etm_ctx->capture_driver = etm_capture_drivers[i];
1483
1484 break;
1485 }
1486 }
1487
1488 if (!etm_capture_drivers[i])
1489 {
1490 /* no supported capture driver found, don't register an ETM */
1491 free(etm_ctx);
1492 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1493 return ERROR_FAIL;
1494 }
1495
1496 etm_ctx->target = target;
1497 etm_ctx->trigger_percent = 50;
1498 etm_ctx->trace_data = NULL;
1499 etm_ctx->portmode = portmode;
1500 etm_ctx->core_state = ARM_STATE_ARM;
1501
1502 arm->etm = etm_ctx;
1503
1504 return etm_register_user_commands(CMD_CTX);
1505 }
1506
1507 COMMAND_HANDLER(handle_etm_info_command)
1508 {
1509 struct target *target;
1510 struct arm *arm;
1511 struct etm_context *etm;
1512 struct reg *etm_sys_config_reg;
1513 int max_port_size;
1514 uint32_t config;
1515
1516 target = get_current_target(CMD_CTX);
1517 arm = target_to_arm(target);
1518 if (!is_arm(arm))
1519 {
1520 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1521 return ERROR_FAIL;
1522 }
1523
1524 etm = arm->etm;
1525 if (!etm)
1526 {
1527 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1528 return ERROR_FAIL;
1529 }
1530
1531 command_print(CMD_CTX, "ETM v%d.%d",
1532 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1533 command_print(CMD_CTX, "pairs of address comparators: %i",
1534 (int) (etm->config >> 0) & 0x0f);
1535 command_print(CMD_CTX, "data comparators: %i",
1536 (int) (etm->config >> 4) & 0x0f);
1537 command_print(CMD_CTX, "memory map decoders: %i",
1538 (int) (etm->config >> 8) & 0x1f);
1539 command_print(CMD_CTX, "number of counters: %i",
1540 (int) (etm->config >> 13) & 0x07);
1541 command_print(CMD_CTX, "sequencer %spresent",
1542 (int) (etm->config & (1 << 16)) ? "" : "not ");
1543 command_print(CMD_CTX, "number of ext. inputs: %i",
1544 (int) (etm->config >> 17) & 0x07);
1545 command_print(CMD_CTX, "number of ext. outputs: %i",
1546 (int) (etm->config >> 20) & 0x07);
1547 command_print(CMD_CTX, "FIFO full %spresent",
1548 (int) (etm->config & (1 << 23)) ? "" : "not ");
1549 if (etm->bcd_vers < 0x20)
1550 command_print(CMD_CTX, "protocol version: %i",
1551 (int) (etm->config >> 28) & 0x07);
1552 else {
1553 command_print(CMD_CTX,
1554 "coprocessor and memory access %ssupported",
1555 (etm->config & (1 << 26)) ? "" : "not ");
1556 command_print(CMD_CTX, "trace start/stop %spresent",
1557 (etm->config & (1 << 26)) ? "" : "not ");
1558 command_print(CMD_CTX, "number of context comparators: %i",
1559 (int) (etm->config >> 24) & 0x03);
1560 }
1561
1562 /* SYS_CONFIG isn't present before ETMv1.2 */
1563 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1564 if (!etm_sys_config_reg)
1565 return ERROR_OK;
1566
1567 etm_get_reg(etm_sys_config_reg);
1568 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1569
1570 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1571
1572 max_port_size = config & 0x7;
1573 if (etm->bcd_vers >= 0x30)
1574 max_port_size |= (config >> 6) & 0x08;
1575 switch (max_port_size)
1576 {
1577 /* before ETMv3.0 */
1578 case 0:
1579 max_port_size = 4;
1580 break;
1581 case 1:
1582 max_port_size = 8;
1583 break;
1584 case 2:
1585 max_port_size = 16;
1586 break;
1587 /* ETMv3.0 and later*/
1588 case 3:
1589 max_port_size = 24;
1590 break;
1591 case 4:
1592 max_port_size = 32;
1593 break;
1594 case 5:
1595 max_port_size = 48;
1596 break;
1597 case 6:
1598 max_port_size = 64;
1599 break;
1600 case 8:
1601 max_port_size = 1;
1602 break;
1603 case 9:
1604 max_port_size = 2;
1605 break;
1606 default:
1607 LOG_ERROR("Illegal max_port_size");
1608 return ERROR_FAIL;
1609 }
1610 command_print(CMD_CTX, "max. port size: %i", max_port_size);
1611
1612 if (etm->bcd_vers < 0x30) {
1613 command_print(CMD_CTX, "half-rate clocking %ssupported",
1614 (config & (1 << 3)) ? "" : "not ");
1615 command_print(CMD_CTX, "full-rate clocking %ssupported",
1616 (config & (1 << 4)) ? "" : "not ");
1617 command_print(CMD_CTX, "normal trace format %ssupported",
1618 (config & (1 << 5)) ? "" : "not ");
1619 command_print(CMD_CTX, "multiplex trace format %ssupported",
1620 (config & (1 << 6)) ? "" : "not ");
1621 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1622 (config & (1 << 7)) ? "" : "not ");
1623 } else {
1624 /* REVISIT show which size and format are selected ... */
1625 command_print(CMD_CTX, "current port size %ssupported",
1626 (config & (1 << 10)) ? "" : "not ");
1627 command_print(CMD_CTX, "current trace format %ssupported",
1628 (config & (1 << 11)) ? "" : "not ");
1629 }
1630 if (etm->bcd_vers >= 0x21)
1631 command_print(CMD_CTX, "fetch comparisons %ssupported",
1632 (config & (1 << 17)) ? "not " : "");
1633 command_print(CMD_CTX, "FIFO full %ssupported",
1634 (config & (1 << 8)) ? "" : "not ");
1635
1636 return ERROR_OK;
1637 }
1638
1639 COMMAND_HANDLER(handle_etm_status_command)
1640 {
1641 struct target *target;
1642 struct arm *arm;
1643 struct etm_context *etm;
1644 trace_status_t trace_status;
1645
1646 target = get_current_target(CMD_CTX);
1647 arm = target_to_arm(target);
1648 if (!is_arm(arm))
1649 {
1650 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1651 return ERROR_FAIL;
1652 }
1653
1654 etm = arm->etm;
1655 if (!etm)
1656 {
1657 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1658 return ERROR_FAIL;
1659 }
1660
1661 /* ETM status */
1662 if (etm->bcd_vers >= 0x11) {
1663 struct reg *reg;
1664
1665 reg = etm_reg_lookup(etm, ETM_STATUS);
1666 if (!reg)
1667 return ERROR_FAIL;
1668 if (etm_get_reg(reg) == ERROR_OK) {
1669 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1670
1671 command_print(CMD_CTX, "etm: %s%s%s%s",
1672 /* bit(1) == progbit */
1673 (etm->bcd_vers >= 0x12)
1674 ? ((s & (1 << 1))
1675 ? "disabled" : "enabled")
1676 : "?",
1677 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1678 ? " triggered" : "",
1679 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1680 ? " start/stop" : "",
1681 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1682 ? " untraced-overflow" : "");
1683 } /* else ignore and try showing trace port status */
1684 }
1685
1686 /* Trace Port Driver status */
1687 trace_status = etm->capture_driver->status(etm);
1688 if (trace_status == TRACE_IDLE)
1689 {
1690 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1691 }
1692 else
1693 {
1694 static char *completed = " completed";
1695 static char *running = " is running";
1696 static char *overflowed = ", overflowed";
1697 static char *triggered = ", triggered";
1698
1699 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1700 etm->capture_driver->name,
1701 (trace_status & TRACE_RUNNING) ? running : completed,
1702 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1703 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1704
1705 if (etm->trace_depth > 0)
1706 {
1707 command_print(CMD_CTX, "%i frames of trace data read",
1708 (int)(etm->trace_depth));
1709 }
1710 }
1711
1712 return ERROR_OK;
1713 }
1714
1715 COMMAND_HANDLER(handle_etm_image_command)
1716 {
1717 struct target *target;
1718 struct arm *arm;
1719 struct etm_context *etm_ctx;
1720
1721 if (CMD_ARGC < 1)
1722 {
1723 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1724 return ERROR_FAIL;
1725 }
1726
1727 target = get_current_target(CMD_CTX);
1728 arm = target_to_arm(target);
1729 if (!is_arm(arm))
1730 {
1731 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1732 return ERROR_FAIL;
1733 }
1734
1735 etm_ctx = arm->etm;
1736 if (!etm_ctx)
1737 {
1738 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1739 return ERROR_FAIL;
1740 }
1741
1742 if (etm_ctx->image)
1743 {
1744 image_close(etm_ctx->image);
1745 free(etm_ctx->image);
1746 command_print(CMD_CTX, "previously loaded image found and closed");
1747 }
1748
1749 etm_ctx->image = malloc(sizeof(struct image));
1750 etm_ctx->image->base_address_set = 0;
1751 etm_ctx->image->start_address_set = 0;
1752
1753 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1754 if (CMD_ARGC >= 2)
1755 {
1756 etm_ctx->image->base_address_set = 1;
1757 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], etm_ctx->image->base_address);
1758 }
1759 else
1760 {
1761 etm_ctx->image->base_address_set = 0;
1762 }
1763
1764 if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1765 {
1766 free(etm_ctx->image);
1767 etm_ctx->image = NULL;
1768 return ERROR_FAIL;
1769 }
1770
1771 return ERROR_OK;
1772 }
1773
1774 COMMAND_HANDLER(handle_etm_dump_command)
1775 {
1776 struct fileio file;
1777 struct target *target;
1778 struct arm *arm;
1779 struct etm_context *etm_ctx;
1780 uint32_t i;
1781
1782 if (CMD_ARGC != 1)
1783 {
1784 command_print(CMD_CTX, "usage: etm dump <file>");
1785 return ERROR_FAIL;
1786 }
1787
1788 target = get_current_target(CMD_CTX);
1789 arm = target_to_arm(target);
1790 if (!is_arm(arm))
1791 {
1792 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1793 return ERROR_FAIL;
1794 }
1795
1796 etm_ctx = arm->etm;
1797 if (!etm_ctx)
1798 {
1799 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1800 return ERROR_FAIL;
1801 }
1802
1803 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1804 {
1805 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1806 return ERROR_OK;
1807 }
1808
1809 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1810 {
1811 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1812 command_print(CMD_CTX, "trace capture not completed");
1813 return ERROR_FAIL;
1814 }
1815
1816 /* read the trace data if it wasn't read already */
1817 if (etm_ctx->trace_depth == 0)
1818 etm_ctx->capture_driver->read_trace(etm_ctx);
1819
1820 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1821 {
1822 return ERROR_FAIL;
1823 }
1824
1825 fileio_write_u32(&file, etm_ctx->capture_status);
1826 fileio_write_u32(&file, etm_ctx->portmode);
1827 fileio_write_u32(&file, etm_ctx->tracemode);
1828 fileio_write_u32(&file, etm_ctx->trace_depth);
1829
1830 for (i = 0; i < etm_ctx->trace_depth; i++)
1831 {
1832 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1833 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1834 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1835 }
1836
1837 fileio_close(&file);
1838
1839 return ERROR_OK;
1840 }
1841
1842 COMMAND_HANDLER(handle_etm_load_command)
1843 {
1844 struct fileio file;
1845 struct target *target;
1846 struct arm *arm;
1847 struct etm_context *etm_ctx;
1848 uint32_t i;
1849
1850 if (CMD_ARGC != 1)
1851 {
1852 command_print(CMD_CTX, "usage: etm load <file>");
1853 return ERROR_FAIL;
1854 }
1855
1856 target = get_current_target(CMD_CTX);
1857 arm = target_to_arm(target);
1858 if (!is_arm(arm))
1859 {
1860 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1861 return ERROR_FAIL;
1862 }
1863
1864 etm_ctx = arm->etm;
1865 if (!etm_ctx)
1866 {
1867 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1868 return ERROR_FAIL;
1869 }
1870
1871 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1872 {
1873 command_print(CMD_CTX, "trace capture running, stop first");
1874 return ERROR_FAIL;
1875 }
1876
1877 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1878 {
1879 return ERROR_FAIL;
1880 }
1881
1882 if (file.size % 4)
1883 {
1884 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1885 fileio_close(&file);
1886 return ERROR_FAIL;
1887 }
1888
1889 if (etm_ctx->trace_depth > 0)
1890 {
1891 free(etm_ctx->trace_data);
1892 etm_ctx->trace_data = NULL;
1893 }
1894
1895 {
1896 uint32_t tmp;
1897 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1898 fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1899 fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1900 fileio_read_u32(&file, &etm_ctx->trace_depth);
1901 }
1902 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1903 if (etm_ctx->trace_data == NULL)
1904 {
1905 command_print(CMD_CTX, "not enough memory to perform operation");
1906 fileio_close(&file);
1907 return ERROR_FAIL;
1908 }
1909
1910 for (i = 0; i < etm_ctx->trace_depth; i++)
1911 {
1912 uint32_t pipestat, packet, flags;
1913 fileio_read_u32(&file, &pipestat);
1914 fileio_read_u32(&file, &packet);
1915 fileio_read_u32(&file, &flags);
1916 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1917 etm_ctx->trace_data[i].packet = packet & 0xffff;
1918 etm_ctx->trace_data[i].flags = flags;
1919 }
1920
1921 fileio_close(&file);
1922
1923 return ERROR_OK;
1924 }
1925
1926 COMMAND_HANDLER(handle_etm_trigger_percent_command)
1927 {
1928 struct target *target;
1929 struct arm *arm;
1930 struct etm_context *etm_ctx;
1931
1932 target = get_current_target(CMD_CTX);
1933 arm = target_to_arm(target);
1934 if (!is_arm(arm))
1935 {
1936 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1937 return ERROR_FAIL;
1938 }
1939
1940 etm_ctx = arm->etm;
1941 if (!etm_ctx)
1942 {
1943 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1944 return ERROR_FAIL;
1945 }
1946
1947 if (CMD_ARGC > 0)
1948 {
1949 uint32_t new_value;
1950 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
1951
1952 if ((new_value < 2) || (new_value > 100))
1953 {
1954 command_print(CMD_CTX, "valid settings are 2%% to 100%%");
1955 }
1956 else
1957 {
1958 etm_ctx->trigger_percent = new_value;
1959 }
1960 }
1961
1962 command_print(CMD_CTX, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1963
1964 return ERROR_OK;
1965 }
1966
1967 COMMAND_HANDLER(handle_etm_start_command)
1968 {
1969 struct target *target;
1970 struct arm *arm;
1971 struct etm_context *etm_ctx;
1972 struct reg *etm_ctrl_reg;
1973
1974 target = get_current_target(CMD_CTX);
1975 arm = target_to_arm(target);
1976 if (!is_arm(arm))
1977 {
1978 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1979 return ERROR_FAIL;
1980 }
1981
1982 etm_ctx = arm->etm;
1983 if (!etm_ctx)
1984 {
1985 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1986 return ERROR_FAIL;
1987 }
1988
1989 /* invalidate old tracing data */
1990 etm_ctx->capture_status = TRACE_IDLE;
1991 if (etm_ctx->trace_depth > 0)
1992 {
1993 free(etm_ctx->trace_data);
1994 etm_ctx->trace_data = NULL;
1995 }
1996 etm_ctx->trace_depth = 0;
1997
1998 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1999 if (!etm_ctrl_reg)
2000 return ERROR_FAIL;
2001
2002 etm_get_reg(etm_ctrl_reg);
2003
2004 /* Clear programming bit (10), set port selection bit (11) */
2005 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
2006
2007 etm_store_reg(etm_ctrl_reg);
2008 jtag_execute_queue();
2009
2010 etm_ctx->capture_driver->start_capture(etm_ctx);
2011
2012 return ERROR_OK;
2013 }
2014
2015 COMMAND_HANDLER(handle_etm_stop_command)
2016 {
2017 struct target *target;
2018 struct arm *arm;
2019 struct etm_context *etm_ctx;
2020 struct reg *etm_ctrl_reg;
2021
2022 target = get_current_target(CMD_CTX);
2023 arm = target_to_arm(target);
2024 if (!is_arm(arm))
2025 {
2026 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2027 return ERROR_FAIL;
2028 }
2029
2030 etm_ctx = arm->etm;
2031 if (!etm_ctx)
2032 {
2033 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2034 return ERROR_FAIL;
2035 }
2036
2037 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2038 if (!etm_ctrl_reg)
2039 return ERROR_FAIL;
2040
2041 etm_get_reg(etm_ctrl_reg);
2042
2043 /* Set programming bit (10), clear port selection bit (11) */
2044 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2045
2046 etm_store_reg(etm_ctrl_reg);
2047 jtag_execute_queue();
2048
2049 etm_ctx->capture_driver->stop_capture(etm_ctx);
2050
2051 return ERROR_OK;
2052 }
2053
2054 COMMAND_HANDLER(handle_etm_analyze_command)
2055 {
2056 struct target *target;
2057 struct arm *arm;
2058 struct etm_context *etm_ctx;
2059 int retval;
2060
2061 target = get_current_target(CMD_CTX);
2062 arm = target_to_arm(target);
2063 if (!is_arm(arm))
2064 {
2065 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2066 return ERROR_FAIL;
2067 }
2068
2069 etm_ctx = arm->etm;
2070 if (!etm_ctx)
2071 {
2072 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2073 return ERROR_FAIL;
2074 }
2075
2076 if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2077 {
2078 switch (retval)
2079 {
2080 case ERROR_ETM_ANALYSIS_FAILED:
2081 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2082 break;
2083 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2084 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2085 break;
2086 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2087 command_print(CMD_CTX, "no image available for trace analysis");
2088 break;
2089 default:
2090 command_print(CMD_CTX, "unknown error: %i", retval);
2091 }
2092 }
2093
2094 return retval;
2095 }
2096
2097 static const struct command_registration etm_config_command_handlers[] = {
2098 {
2099 .name = "config",
2100 .handler = &handle_etm_config_command,
2101 .mode = COMMAND_CONFIG,
2102 .usage = "<target> <port_width> <port_mode> "
2103 "<clocking> <capture_driver>",
2104 },
2105 COMMAND_REGISTRATION_DONE
2106 };
2107 const struct command_registration etm_command_handlers[] = {
2108 {
2109 .name = "etm",
2110 .mode = COMMAND_ANY,
2111 .help = "Emebdded Trace Macrocell command group",
2112 .chain = etm_config_command_handlers,
2113 },
2114 COMMAND_REGISTRATION_DONE
2115 };
2116
2117 static const struct command_registration etm_exec_command_handlers[] = {
2118 {
2119 .name = "tracemode", handle_etm_tracemode_command,
2120 .mode = COMMAND_EXEC,
2121 .help = "configure/display trace mode",
2122 .usage = "<none | data | address | all> "
2123 "<context_id_bits> <cycle_accurate> <branch_output>",
2124 },
2125 {
2126 .name = "info",
2127 .handler = &handle_etm_info_command,
2128 .mode = COMMAND_EXEC,
2129 .help = "display info about the current target's ETM",
2130 },
2131 {
2132 .name = "trigger_percent",
2133 .handler = &handle_etm_trigger_percent_command,
2134 .mode = COMMAND_EXEC,
2135 .help = "amount (<percent>) of trace buffer "
2136 "to be filled after the trigger occured",
2137 },
2138 {
2139 .name = "status",
2140 .handler = &handle_etm_status_command,
2141 .mode = COMMAND_EXEC,
2142 .help = "display current target's ETM status",
2143 },
2144 {
2145 .name = "start",
2146 .handler = &handle_etm_start_command,
2147 .mode = COMMAND_EXEC,
2148 .help = "start ETM trace collection",
2149 },
2150 {
2151 .name = "stop",
2152 .handler = &handle_etm_stop_command,
2153 .mode = COMMAND_EXEC,
2154 .help = "stop ETM trace collection",
2155 },
2156 {
2157 .name = "analyze",
2158 .handler = &handle_etm_analyze_command,
2159 .mode = COMMAND_EXEC,
2160 .help = "anaylze collected ETM trace",
2161 },
2162 {
2163 .name = "image",
2164 .handler = &handle_etm_image_command,
2165 .mode = COMMAND_EXEC,
2166 .help = "load image from <file> [base address]",
2167 },
2168 {
2169 .name = "dump",
2170 .handler = &handle_etm_dump_command,
2171 .mode = COMMAND_EXEC,
2172 .help = "dump captured trace data <file>",
2173 },
2174 {
2175 .name = "load",
2176 .handler = &handle_etm_load_command,
2177 .mode = COMMAND_EXEC,
2178 .help = "load trace data for analysis <file>",
2179 },
2180 COMMAND_REGISTRATION_DONE
2181 };
2182
2183 static int etm_register_user_commands(struct command_context *cmd_ctx)
2184 {
2185 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2186 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2187 }
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