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helper/binarybuffer: fix clang static analyzer warnings
[openocd.git] / src / target / etm.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18 #ifdef HAVE_CONFIG_H
19 #include "config.h"
20 #endif
21
22 #include "arm.h"
23 #include "etm.h"
24 #include "etb.h"
25 #include "image.h"
26 #include "arm_disassembler.h"
27 #include "register.h"
28 #include "etm_dummy.h"
29
30 #if BUILD_OOCD_TRACE == 1
31 #include "oocd_trace.h"
32 #endif
33
34
35 /*
36 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
37 *
38 * ETM modules collect instruction and/or data trace information, compress
39 * it, and transfer it to a debugging host through either a (buffered) trace
40 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
41 *
42 * There are several generations of these modules. Original versions have
43 * JTAG access through a dedicated scan chain. Recent versions have added
44 * access via coprocessor instructions, memory addressing, and the ARM Debug
45 * Interface v5 (ADIv5); and phased out direct JTAG access.
46 *
47 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
48 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
49 * implying non-JTAG connectivity options.
50 *
51 * Relevant documentation includes:
52 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
53 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
54 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
55 */
56
57 enum {
58 RO, /* read/only */
59 WO, /* write/only */
60 RW, /* read/write */
61 };
62
63 struct etm_reg_info {
64 uint8_t addr;
65 uint8_t size; /* low-N of 32 bits */
66 uint8_t mode; /* RO, WO, RW */
67 uint8_t bcd_vers; /* 1.0, 2.0, etc */
68 const char *name;
69 };
70
71 /*
72 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
73 * (Or on some processors, through coprocessor operations.)
74 * Newer versions of ETM make some W/O registers R/W, and
75 * provide definitions for some previously-unused bits.
76 */
77
78 /* core registers used to version/configure the ETM */
79 static const struct etm_reg_info etm_core[] = {
80 /* NOTE: we "know" the order here ... */
81 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
82 { ETM_ID, 32, RO, 0x20, "ETM_id", },
83 };
84
85 /* basic registers that are always there given the right ETM version */
86 static const struct etm_reg_info etm_basic[] = {
87 /* ETM Trace Registers */
88 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
89 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
90 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
91 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
92 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
93
94 /* TraceEnable configuration */
95 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
96 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
97 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
98 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
99
100 /* ViewData configuration (data trace) */
101 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
102 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
103 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
104 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
105
106 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
107
108 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
109 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
110 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
111 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
112 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
113 };
114
115 static const struct etm_reg_info etm_fifofull[] = {
116 /* FIFOFULL configuration */
117 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
118 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
119 };
120
121 static const struct etm_reg_info etm_addr_comp[] = {
122 /* Address comparator register pairs */
123 #define ADDR_COMPARATOR(i) \
124 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
125 "ETM_addr_" #i "_comparator_value", }, \
126 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
127 "ETM_addr_" #i "_access_type", }
128 ADDR_COMPARATOR(1),
129 ADDR_COMPARATOR(2),
130 ADDR_COMPARATOR(3),
131 ADDR_COMPARATOR(4),
132 ADDR_COMPARATOR(5),
133 ADDR_COMPARATOR(6),
134 ADDR_COMPARATOR(7),
135 ADDR_COMPARATOR(8),
136
137 ADDR_COMPARATOR(9),
138 ADDR_COMPARATOR(10),
139 ADDR_COMPARATOR(11),
140 ADDR_COMPARATOR(12),
141 ADDR_COMPARATOR(13),
142 ADDR_COMPARATOR(14),
143 ADDR_COMPARATOR(15),
144 ADDR_COMPARATOR(16),
145 { 0, 0, 0, 0, NULL }
146 #undef ADDR_COMPARATOR
147 };
148
149 static const struct etm_reg_info etm_data_comp[] = {
150 /* Data Value Comparators (NOTE: odd addresses are reserved) */
151 #define DATA_COMPARATOR(i) \
152 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
153 "ETM_data_" #i "_comparator_value", }, \
154 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
155 "ETM_data_" #i "_comparator_mask", }
156 DATA_COMPARATOR(1),
157 DATA_COMPARATOR(2),
158 DATA_COMPARATOR(3),
159 DATA_COMPARATOR(4),
160 DATA_COMPARATOR(5),
161 DATA_COMPARATOR(6),
162 DATA_COMPARATOR(7),
163 DATA_COMPARATOR(8),
164 { 0, 0, 0, 0, NULL }
165 #undef DATA_COMPARATOR
166 };
167
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
178 ETM_COUNTER(1),
179 ETM_COUNTER(2),
180 ETM_COUNTER(3),
181 ETM_COUNTER(4),
182 { 0, 0, 0, 0, NULL }
183 #undef ETM_COUNTER
184 };
185
186 static const struct etm_reg_info etm_sequencer[] = {
187 #define ETM_SEQ(i) \
188 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
189 "ETM_sequencer_event" #i, }
190 ETM_SEQ(0), /* 1->2 */
191 ETM_SEQ(1), /* 2->1 */
192 ETM_SEQ(2), /* 2->3 */
193 ETM_SEQ(3), /* 3->1 */
194 ETM_SEQ(4), /* 3->2 */
195 ETM_SEQ(5), /* 1->3 */
196 #undef ETM_SEQ
197 /* 0x66 reserved */
198 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
199 };
200
201 static const struct etm_reg_info etm_outputs[] = {
202 #define ETM_OUTPUT(i) \
203 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
204 "ETM_external_output" #i, }
205
206 ETM_OUTPUT(1),
207 ETM_OUTPUT(2),
208 ETM_OUTPUT(3),
209 ETM_OUTPUT(4),
210 { 0, 0, 0, 0, NULL }
211 #undef ETM_OUTPUT
212 };
213
214 #if 0
215 /* registers from 0x6c..0x7f were added after ETMv1.3 */
216
217 /* Context ID Comparators */
218 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
219 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
220 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
221 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
222 #endif
223
224 static int etm_get_reg(struct reg *reg);
225 static int etm_read_reg_w_check(struct reg *reg,
226 uint8_t *check_value, uint8_t *check_mask);
227 static int etm_register_user_commands(struct command_context *cmd_ctx);
228 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
229 static int etm_write_reg(struct reg *reg, uint32_t value);
230
231 static const struct reg_arch_type etm_scan6_type = {
232 .get = etm_get_reg,
233 .set = etm_set_reg_w_exec,
234 };
235
236 /* Look up register by ID ... most ETM instances only
237 * support a subset of the possible registers.
238 */
239 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
240 {
241 struct reg_cache *cache = etm_ctx->reg_cache;
242 unsigned i;
243
244 for (i = 0; i < cache->num_regs; i++) {
245 struct etm_reg *reg = cache->reg_list[i].arch_info;
246
247 if (reg->reg_info->addr == id)
248 return &cache->reg_list[i];
249 }
250
251 /* caller asking for nonexistent register is a bug!
252 * REVISIT say which of the N targets was involved */
253 LOG_ERROR("ETM: register 0x%02x not available", id);
254 return NULL;
255 }
256
257 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
258 struct reg_cache *cache, struct etm_reg *ereg,
259 const struct etm_reg_info *r, unsigned nreg)
260 {
261 struct reg *reg = cache->reg_list;
262
263 reg += cache->num_regs;
264 ereg += cache->num_regs;
265
266 /* add up to "nreg" registers from "r", if supported by this
267 * version of the ETM, to the specified cache.
268 */
269 for (; nreg--; r++) {
270 /* No more registers to add */
271 if (!r->size) {
272 LOG_ERROR("etm_reg_add is requested to add non-existing registers, ETM config might be bogus");
273 return;
274 }
275
276 /* this ETM may be too old to have some registers */
277 if (r->bcd_vers > bcd_vers)
278 continue;
279
280 reg->name = r->name;
281 reg->size = r->size;
282 reg->value = &ereg->value;
283 reg->arch_info = ereg;
284 reg->type = &etm_scan6_type;
285 reg++;
286 cache->num_regs++;
287
288 ereg->reg_info = r;
289 ereg->jtag_info = jtag_info;
290 ereg++;
291 }
292 }
293
294 struct reg_cache *etm_build_reg_cache(struct target *target,
295 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
296 {
297 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
298 struct reg *reg_list = NULL;
299 struct etm_reg *arch_info = NULL;
300 unsigned bcd_vers, config;
301
302 /* the actual registers are kept in two arrays */
303 reg_list = calloc(128, sizeof(struct reg));
304 arch_info = calloc(128, sizeof(struct etm_reg));
305
306 if (reg_cache == NULL || reg_list == NULL || arch_info == NULL) {
307 LOG_ERROR("No memory");
308 goto fail;
309 }
310
311 /* fill in values for the reg cache */
312 reg_cache->name = "etm registers";
313 reg_cache->next = NULL;
314 reg_cache->reg_list = reg_list;
315 reg_cache->num_regs = 0;
316
317 /* add ETM_CONFIG, then parse its values to see
318 * which other registers exist in this ETM
319 */
320 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
321 etm_core, 1);
322
323 etm_get_reg(reg_list);
324 etm_ctx->config = buf_get_u32(arch_info->value, 0, 32);
325 config = etm_ctx->config;
326
327 /* figure ETM version then add base registers */
328 if (config & (1 << 31)) {
329 LOG_WARNING("ETMv2+ support is incomplete");
330
331 /* REVISIT more registers may exist; they may now be
332 * readable; more register bits have defined meanings;
333 * don't presume trace start/stop support is present;
334 * and include any context ID comparator registers.
335 */
336 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
337 etm_core + 1, 1);
338 etm_get_reg(reg_list + 1);
339 etm_ctx->id = buf_get_u32(
340 arch_info[1].value, 0, 32);
341 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
342 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
343
344 } else {
345 switch (config >> 28) {
346 case 7:
347 case 5:
348 case 3:
349 bcd_vers = 0x13;
350 break;
351 case 4:
352 case 2:
353 bcd_vers = 0x12;
354 break;
355 case 1:
356 bcd_vers = 0x11;
357 break;
358 case 0:
359 bcd_vers = 0x10;
360 break;
361 default:
362 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
363 goto fail;
364 }
365 }
366 etm_ctx->bcd_vers = bcd_vers;
367 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
368
369 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
370 etm_basic, ARRAY_SIZE(etm_basic));
371
372 /* address and data comparators; counters; outputs */
373 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
374 etm_addr_comp, 4 * (0x0f & (config >> 0)));
375 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
376 etm_data_comp, 2 * (0x0f & (config >> 4)));
377 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
378 etm_counters, 4 * (0x07 & (config >> 13)));
379 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
380 etm_outputs, (0x07 & (config >> 20)));
381
382 /* FIFOFULL presence is optional
383 * REVISIT for ETMv1.2 and later, don't bother adding this
384 * unless ETM_SYS_CONFIG says it's also *supported* ...
385 */
386 if (config & (1 << 23))
387 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
388 etm_fifofull, ARRAY_SIZE(etm_fifofull));
389
390 /* sequencer is optional (for state-dependant triggering) */
391 if (config & (1 << 16))
392 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
393 etm_sequencer, ARRAY_SIZE(etm_sequencer));
394
395 /* REVISIT could realloc and likely save half the memory
396 * in the two chunks we allocated...
397 */
398
399 /* the ETM might have an ETB connected */
400 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0) {
401 struct etb *etb = etm_ctx->capture_driver_priv;
402
403 if (!etb) {
404 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
405 goto fail;
406 }
407
408 reg_cache->next = etb_build_reg_cache(etb);
409
410 etb->reg_cache = reg_cache->next;
411 }
412
413 etm_ctx->reg_cache = reg_cache;
414 return reg_cache;
415
416 fail:
417 free(reg_cache);
418 free(reg_list);
419 free(arch_info);
420 return NULL;
421 }
422
423 static int etm_read_reg(struct reg *reg)
424 {
425 return etm_read_reg_w_check(reg, NULL, NULL);
426 }
427
428 static int etm_store_reg(struct reg *reg)
429 {
430 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
431 }
432
433 int etm_setup(struct target *target)
434 {
435 int retval;
436 uint32_t etm_ctrl_value;
437 struct arm *arm = target_to_arm(target);
438 struct etm_context *etm_ctx = arm->etm;
439 struct reg *etm_ctrl_reg;
440
441 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
442 if (!etm_ctrl_reg)
443 return ERROR_OK;
444
445 /* initialize some ETM control register settings */
446 etm_get_reg(etm_ctrl_reg);
447 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
448
449 /* clear the ETM powerdown bit (0) */
450 etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
451
452 /* configure port width (21,6:4), mode (13,17:16) and
453 * for older modules clocking (13)
454 */
455 etm_ctrl_value = (etm_ctrl_value
456 & ~ETM_PORT_WIDTH_MASK
457 & ~ETM_PORT_MODE_MASK
458 & ~ETM_CTRL_DBGRQ
459 & ~ETM_PORT_CLOCK_MASK)
460 | etm_ctx->control;
461
462 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
463 etm_store_reg(etm_ctrl_reg);
464
465 etm_ctx->control = etm_ctrl_value;
466
467 retval = jtag_execute_queue();
468 if (retval != ERROR_OK)
469 return retval;
470
471 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
472 * verify that those width and mode settings are OK ...
473 */
474
475 retval = etm_ctx->capture_driver->init(etm_ctx);
476 if (retval != ERROR_OK) {
477 LOG_ERROR("ETM capture driver initialization failed");
478 return retval;
479 }
480 return ERROR_OK;
481 }
482
483 static int etm_get_reg(struct reg *reg)
484 {
485 int retval;
486
487 retval = etm_read_reg(reg);
488 if (retval != ERROR_OK) {
489 LOG_ERROR("BUG: error scheduling etm register read");
490 return retval;
491 }
492
493 retval = jtag_execute_queue();
494 if (retval != ERROR_OK) {
495 LOG_ERROR("register read failed");
496 return retval;
497 }
498
499 return ERROR_OK;
500 }
501
502 static int etm_read_reg_w_check(struct reg *reg,
503 uint8_t *check_value, uint8_t *check_mask)
504 {
505 struct etm_reg *etm_reg = reg->arch_info;
506 assert(etm_reg);
507 const struct etm_reg_info *r = etm_reg->reg_info;
508 uint8_t reg_addr = r->addr & 0x7f;
509 struct scan_field fields[3];
510 int retval;
511
512 if (etm_reg->reg_info->mode == WO) {
513 LOG_ERROR("BUG: can't read write-only register %s", r->name);
514 return ERROR_COMMAND_SYNTAX_ERROR;
515 }
516
517 LOG_DEBUG("%s (%u)", r->name, reg_addr);
518
519 retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
520 if (retval != ERROR_OK)
521 return retval;
522 retval = arm_jtag_set_instr(etm_reg->jtag_info->tap,
523 etm_reg->jtag_info->intest_instr,
524 NULL,
525 TAP_IDLE);
526 if (retval != ERROR_OK)
527 return retval;
528
529 fields[0].num_bits = 32;
530 fields[0].out_value = reg->value;
531 fields[0].in_value = NULL;
532 fields[0].check_value = NULL;
533 fields[0].check_mask = NULL;
534
535 fields[1].num_bits = 7;
536 uint8_t temp1 = 0;
537 fields[1].out_value = &temp1;
538 buf_set_u32(&temp1, 0, 7, reg_addr);
539 fields[1].in_value = NULL;
540 fields[1].check_value = NULL;
541 fields[1].check_mask = NULL;
542
543 fields[2].num_bits = 1;
544 uint8_t temp2 = 0;
545 fields[2].out_value = &temp2;
546 buf_set_u32(&temp2, 0, 1, 0);
547 fields[2].in_value = NULL;
548 fields[2].check_value = NULL;
549 fields[2].check_mask = NULL;
550
551 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
552
553 fields[0].in_value = reg->value;
554 fields[0].check_value = check_value;
555 fields[0].check_mask = check_mask;
556
557 jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
558
559 return ERROR_OK;
560 }
561
562 static int etm_set_reg(struct reg *reg, uint32_t value)
563 {
564 int retval = etm_write_reg(reg, value);
565 if (retval != ERROR_OK) {
566 LOG_ERROR("BUG: error scheduling etm register write");
567 return retval;
568 }
569
570 buf_set_u32(reg->value, 0, reg->size, value);
571 reg->valid = 1;
572 reg->dirty = 0;
573
574 return ERROR_OK;
575 }
576
577 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
578 {
579 int retval;
580
581 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
582
583 retval = jtag_execute_queue();
584 if (retval != ERROR_OK) {
585 LOG_ERROR("register write failed");
586 return retval;
587 }
588 return ERROR_OK;
589 }
590
591 static int etm_write_reg(struct reg *reg, uint32_t value)
592 {
593 struct etm_reg *etm_reg = reg->arch_info;
594 const struct etm_reg_info *r = etm_reg->reg_info;
595 uint8_t reg_addr = r->addr & 0x7f;
596 struct scan_field fields[3];
597 int retval;
598
599 if (etm_reg->reg_info->mode == RO) {
600 LOG_ERROR("BUG: can't write read--only register %s", r->name);
601 return ERROR_COMMAND_SYNTAX_ERROR;
602 }
603
604 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
605
606 retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
607 if (retval != ERROR_OK)
608 return retval;
609 retval = arm_jtag_set_instr(etm_reg->jtag_info->tap,
610 etm_reg->jtag_info->intest_instr,
611 NULL,
612 TAP_IDLE);
613 if (retval != ERROR_OK)
614 return retval;
615
616 fields[0].num_bits = 32;
617 uint8_t tmp1[4];
618 fields[0].out_value = tmp1;
619 buf_set_u32(tmp1, 0, 32, value);
620 fields[0].in_value = NULL;
621
622 fields[1].num_bits = 7;
623 uint8_t tmp2 = 0;
624 fields[1].out_value = &tmp2;
625 buf_set_u32(&tmp2, 0, 7, reg_addr);
626 fields[1].in_value = NULL;
627
628 fields[2].num_bits = 1;
629 uint8_t tmp3 = 0;
630 fields[2].out_value = &tmp3;
631 buf_set_u32(&tmp3, 0, 1, 1);
632 fields[2].in_value = NULL;
633
634 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
635
636 return ERROR_OK;
637 }
638
639
640 /* ETM trace analysis functionality */
641
642 static struct etm_capture_driver *etm_capture_drivers[] = {
643 &etb_capture_driver,
644 &etm_dummy_capture_driver,
645 #if BUILD_OOCD_TRACE == 1
646 &oocd_trace_capture_driver,
647 #endif
648 NULL
649 };
650
651 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
652 {
653 int i;
654 int section = -1;
655 size_t size_read;
656 uint32_t opcode;
657 int retval;
658
659 if (!ctx->image)
660 return ERROR_TRACE_IMAGE_UNAVAILABLE;
661
662 /* search for the section the current instruction belongs to */
663 for (i = 0; i < ctx->image->num_sections; i++) {
664 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
665 (ctx->image->sections[i].base_address + ctx->image->sections[i].size >
666 ctx->current_pc)) {
667 section = i;
668 break;
669 }
670 }
671
672 if (section == -1) {
673 /* current instruction couldn't be found in the image */
674 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
675 }
676
677 if (ctx->core_state == ARM_STATE_ARM) {
678 uint8_t buf[4];
679 retval = image_read_section(ctx->image, section,
680 ctx->current_pc -
681 ctx->image->sections[section].base_address,
682 4, buf, &size_read);
683 if (retval != ERROR_OK) {
684 LOG_ERROR("error while reading instruction");
685 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
686 }
687 opcode = target_buffer_get_u32(ctx->target, buf);
688 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
689 } else if (ctx->core_state == ARM_STATE_THUMB) {
690 uint8_t buf[2];
691 retval = image_read_section(ctx->image, section,
692 ctx->current_pc -
693 ctx->image->sections[section].base_address,
694 2, buf, &size_read);
695 if (retval != ERROR_OK) {
696 LOG_ERROR("error while reading instruction");
697 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
698 }
699 opcode = target_buffer_get_u16(ctx->target, buf);
700 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
701 } else if (ctx->core_state == ARM_STATE_JAZELLE) {
702 LOG_ERROR("BUG: tracing of jazelle code not supported");
703 return ERROR_FAIL;
704 } else {
705 LOG_ERROR("BUG: unknown core state encountered");
706 return ERROR_FAIL;
707 }
708
709 return ERROR_OK;
710 }
711
712 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
713 {
714 while (ctx->data_index < ctx->trace_depth) {
715 /* if the caller specified an address packet offset, skip until the
716 * we reach the n-th cycle marked with tracesync */
717 if (apo > 0) {
718 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
719 apo--;
720
721 if (apo > 0) {
722 ctx->data_index++;
723 ctx->data_half = 0;
724 }
725 continue;
726 }
727
728 /* no tracedata output during a TD cycle
729 * or in a trigger cycle */
730 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
731 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE)) {
732 ctx->data_index++;
733 ctx->data_half = 0;
734 continue;
735 }
736
737 /* FIXME there are more port widths than these... */
738 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT) {
739 if (ctx->data_half == 0) {
740 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
741 ctx->data_half = 1;
742 } else {
743 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
744 ctx->data_half = 0;
745 ctx->data_index++;
746 }
747 } else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) {
748 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
749 ctx->data_index++;
750 } else {
751 /* on a 4-bit port, a packet will be output during two consecutive cycles */
752 if (ctx->data_index > (ctx->trace_depth - 2))
753 return -1;
754
755 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
756 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
757 ctx->data_index += 2;
758 }
759
760 return 0;
761 }
762
763 return -1;
764 }
765
766 static int etmv1_branch_address(struct etm_context *ctx)
767 {
768 int retval;
769 uint8_t packet;
770 int shift = 0;
771 int apo;
772 uint32_t i;
773
774 /* quit analysis if less than two cycles are left in the trace
775 * because we can't extract the APO */
776 if (ctx->data_index > (ctx->trace_depth - 2))
777 return -1;
778
779 /* a BE could be output during an APO cycle, skip the current
780 * and continue with the new one */
781 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
782 return 1;
783 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
784 return 2;
785
786 /* address packet offset encoded in the next two cycles' pipestat bits */
787 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
788 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
789
790 /* count number of tracesync cycles between current pipe_index and data_index
791 * i.e. the number of tracesyncs that data_index already passed by
792 * to subtract them from the APO */
793 for (i = ctx->pipe_index; i < ctx->data_index; i++) {
794 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
795 apo--;
796 }
797
798 /* extract up to four 7-bit packets */
799 do {
800 retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0);
801 if (retval != 0)
802 return -1;
803 ctx->last_branch &= ~(0x7f << shift);
804 ctx->last_branch |= (packet & 0x7f) << shift;
805 shift += 7;
806 } while ((packet & 0x80) && (shift < 28));
807
808 /* one last packet holding 4 bits of the address, plus the branch reason code */
809 if ((shift == 28) && (packet & 0x80)) {
810 retval = etmv1_next_packet(ctx, &packet, 0);
811 if (retval != 0)
812 return -1;
813 ctx->last_branch &= 0x0fffffff;
814 ctx->last_branch |= (packet & 0x0f) << 28;
815 ctx->last_branch_reason = (packet & 0x70) >> 4;
816 shift += 4;
817 } else
818 ctx->last_branch_reason = 0;
819
820 if (shift == 32)
821 ctx->pc_ok = 1;
822
823 /* if a full address was output, we might have branched into Jazelle state */
824 if ((shift == 32) && (packet & 0x80))
825 ctx->core_state = ARM_STATE_JAZELLE;
826 else {
827 /* if we didn't branch into Jazelle state, the current processor state is
828 * encoded in bit 0 of the branch target address */
829 if (ctx->last_branch & 0x1) {
830 ctx->core_state = ARM_STATE_THUMB;
831 ctx->last_branch &= ~0x1;
832 } else {
833 ctx->core_state = ARM_STATE_ARM;
834 ctx->last_branch &= ~0x3;
835 }
836 }
837
838 return 0;
839 }
840
841 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
842 {
843 int j;
844 uint8_t buf[4];
845 int retval;
846
847 for (j = 0; j < size; j++) {
848 retval = etmv1_next_packet(ctx, &buf[j], 0);
849 if (retval != 0)
850 return -1;
851 }
852
853 if (size == 8) {
854 LOG_ERROR("TODO: add support for 64-bit values");
855 return -1;
856 } else if (size == 4)
857 *data = target_buffer_get_u32(ctx->target, buf);
858 else if (size == 2)
859 *data = target_buffer_get_u16(ctx->target, buf);
860 else if (size == 1)
861 *data = buf[0];
862 else
863 return -1;
864
865 return 0;
866 }
867
868 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocation *cmd)
869 {
870 int retval;
871 struct arm_instruction instruction;
872
873 /* read the trace data if it wasn't read already */
874 if (ctx->trace_depth == 0)
875 ctx->capture_driver->read_trace(ctx);
876
877 if (ctx->trace_depth == 0) {
878 command_print(cmd, "Trace is empty.");
879 return ERROR_OK;
880 }
881
882 /* start at the beginning of the captured trace */
883 ctx->pipe_index = 0;
884 ctx->data_index = 0;
885 ctx->data_half = 0;
886
887 /* neither the PC nor the data pointer are valid */
888 ctx->pc_ok = 0;
889 ctx->ptr_ok = 0;
890
891 while (ctx->pipe_index < ctx->trace_depth) {
892 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
893 uint32_t next_pc = ctx->current_pc;
894 uint32_t old_data_index = ctx->data_index;
895 uint32_t old_data_half = ctx->data_half;
896 uint32_t old_index = ctx->pipe_index;
897 uint32_t last_instruction = ctx->last_instruction;
898 uint32_t cycles = 0;
899 int current_pc_ok = ctx->pc_ok;
900
901 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
902 command_print(cmd, "--- trigger ---");
903
904 /* instructions execute in IE/D or BE/D cycles */
905 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
906 ctx->last_instruction = ctx->pipe_index;
907
908 /* if we don't have a valid pc skip until we reach an indirect branch */
909 if ((!ctx->pc_ok) && (pipestat != STAT_BE)) {
910 ctx->pipe_index++;
911 continue;
912 }
913
914 /* any indirect branch could have interrupted instruction flow
915 * - the branch reason code could indicate a trace discontinuity
916 * - a branch to the exception vectors indicates an exception
917 */
918 if ((pipestat == STAT_BE) || (pipestat == STAT_BD)) {
919 /* backup current data index, to be able to consume the branch address
920 * before examining data address and values
921 */
922 old_data_index = ctx->data_index;
923 old_data_half = ctx->data_half;
924
925 ctx->last_instruction = ctx->pipe_index;
926
927 retval = etmv1_branch_address(ctx);
928 if (retval != 0) {
929 /* negative return value from etmv1_branch_address means we ran out of packets,
930 * quit analysing the trace */
931 if (retval < 0)
932 break;
933
934 /* a positive return values means the current branch was abandoned,
935 * and a new branch was encountered in cycle ctx->pipe_index + retval;
936 */
937 LOG_WARNING(
938 "abandoned branch encountered, correctness of analysis uncertain");
939 ctx->pipe_index += retval;
940 continue;
941 }
942
943 /* skip over APO cycles */
944 ctx->pipe_index += 2;
945
946 switch (ctx->last_branch_reason) {
947 case 0x0: /* normal PC change */
948 next_pc = ctx->last_branch;
949 break;
950 case 0x1: /* tracing enabled */
951 command_print(cmd,
952 "--- tracing enabled at 0x%8.8" PRIx32 " ---",
953 ctx->last_branch);
954 ctx->current_pc = ctx->last_branch;
955 ctx->pipe_index++;
956 continue;
957 break;
958 case 0x2: /* trace restarted after FIFO overflow */
959 command_print(cmd,
960 "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---",
961 ctx->last_branch);
962 ctx->current_pc = ctx->last_branch;
963 ctx->pipe_index++;
964 continue;
965 break;
966 case 0x3: /* exit from debug state */
967 command_print(cmd,
968 "--- exit from debug state at 0x%8.8" PRIx32 " ---",
969 ctx->last_branch);
970 ctx->current_pc = ctx->last_branch;
971 ctx->pipe_index++;
972 continue;
973 break;
974 case 0x4: /* periodic synchronization point */
975 next_pc = ctx->last_branch;
976 /* if we had no valid PC prior to this synchronization point,
977 * we have to move on with the next trace cycle
978 */
979 if (!current_pc_ok) {
980 command_print(cmd,
981 "--- periodic synchronization point at 0x%8.8" PRIx32 " ---",
982 next_pc);
983 ctx->current_pc = next_pc;
984 ctx->pipe_index++;
985 continue;
986 }
987 break;
988 default: /* reserved */
989 LOG_ERROR(
990 "BUG: branch reason code 0x%" PRIx32 " is reserved",
991 ctx->last_branch_reason);
992 return ERROR_FAIL;
993 }
994
995 /* if we got here the branch was a normal PC change
996 * (or a periodic synchronization point, which means the same for that matter)
997 * if we didn't acquire a complete PC continue with the next cycle
998 */
999 if (!ctx->pc_ok)
1000 continue;
1001
1002 /* indirect branch to the exception vector means an exception occurred */
1003 if ((ctx->last_branch <= 0x20)
1004 || ((ctx->last_branch >= 0xffff0000) &&
1005 (ctx->last_branch <= 0xffff0020))) {
1006 if ((ctx->last_branch & 0xff) == 0x10)
1007 command_print(cmd, "data abort");
1008 else {
1009 command_print(cmd,
1010 "exception vector 0x%2.2" PRIx32 "",
1011 ctx->last_branch);
1012 ctx->current_pc = ctx->last_branch;
1013 ctx->pipe_index++;
1014 continue;
1015 }
1016 }
1017 }
1018
1019 /* an instruction was executed (or not, depending on the condition flags)
1020 * retrieve it from the image for displaying */
1021 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1022 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1023 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4)))) {
1024 retval = etm_read_instruction(ctx, &instruction);
1025 if (retval != ERROR_OK) {
1026 /* can't continue tracing with no image available */
1027 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1028 return retval;
1029 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE) {
1030 /* TODO: handle incomplete images
1031 * for now we just quit the analysis*/
1032 return retval;
1033 }
1034 }
1035
1036 cycles = old_index - last_instruction;
1037 }
1038
1039 if ((pipestat == STAT_ID) || (pipestat == STAT_BD)) {
1040 uint32_t new_data_index = ctx->data_index;
1041 uint32_t new_data_half = ctx->data_half;
1042
1043 /* in case of a branch with data, the branch target address was consumed before
1044 * we temporarily go back to the saved data index */
1045 if (pipestat == STAT_BD) {
1046 ctx->data_index = old_data_index;
1047 ctx->data_half = old_data_half;
1048 }
1049
1050 if (ctx->control & ETM_CTRL_TRACE_ADDR) {
1051 uint8_t packet;
1052 int shift = 0;
1053
1054 do {
1055 retval = etmv1_next_packet(ctx, &packet, 0);
1056 if (retval != 0)
1057 return ERROR_ETM_ANALYSIS_FAILED;
1058 ctx->last_ptr &= ~(0x7f << shift);
1059 ctx->last_ptr |= (packet & 0x7f) << shift;
1060 shift += 7;
1061 } while ((packet & 0x80) && (shift < 32));
1062
1063 if (shift >= 32)
1064 ctx->ptr_ok = 1;
1065
1066 if (ctx->ptr_ok)
1067 command_print(cmd,
1068 "address: 0x%8.8" PRIx32 "",
1069 ctx->last_ptr);
1070 }
1071
1072 if (ctx->control & ETM_CTRL_TRACE_DATA) {
1073 if ((instruction.type == ARM_LDM) ||
1074 (instruction.type == ARM_STM)) {
1075 int i;
1076 for (i = 0; i < 16; i++) {
1077 if (instruction.info.load_store_multiple.
1078 register_list & (1 << i)) {
1079 uint32_t data;
1080 if (etmv1_data(ctx, 4, &data) != 0)
1081 return ERROR_ETM_ANALYSIS_FAILED;
1082 command_print(cmd,
1083 "data: 0x%8.8" PRIx32 "",
1084 data);
1085 }
1086 }
1087 } else if ((instruction.type >= ARM_LDR) &&
1088 (instruction.type <= ARM_STRH)) {
1089 uint32_t data;
1090 if (etmv1_data(ctx, arm_access_size(&instruction),
1091 &data) != 0)
1092 return ERROR_ETM_ANALYSIS_FAILED;
1093 command_print(cmd, "data: 0x%8.8" PRIx32 "", data);
1094 }
1095 }
1096
1097 /* restore data index after consuming BD address and data */
1098 if (pipestat == STAT_BD) {
1099 ctx->data_index = new_data_index;
1100 ctx->data_half = new_data_half;
1101 }
1102 }
1103
1104 /* adjust PC */
1105 if ((pipestat == STAT_IE) || (pipestat == STAT_ID)) {
1106 if (((instruction.type == ARM_B) ||
1107 (instruction.type == ARM_BL) ||
1108 (instruction.type == ARM_BLX)) &&
1109 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1110 next_pc = instruction.info.b_bl_bx_blx.target_address;
1111 else
1112 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1113 } else if (pipestat == STAT_IN)
1114 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1115
1116 if ((pipestat != STAT_TD) && (pipestat != STAT_WT)) {
1117 char cycles_text[32] = "";
1118
1119 /* if the trace was captured with cycle accurate tracing enabled,
1120 * output the number of cycles since the last executed instruction
1121 */
1122 if (ctx->control & ETM_CTRL_CYCLE_ACCURATE) {
1123 snprintf(cycles_text, 32, " (%i %s)",
1124 (int)cycles,
1125 (cycles == 1) ? "cycle" : "cycles");
1126 }
1127
1128 command_print(cmd, "%s%s%s",
1129 instruction.text,
1130 (pipestat == STAT_IN) ? " (not executed)" : "",
1131 cycles_text);
1132
1133 ctx->current_pc = next_pc;
1134
1135 /* packets for an instruction don't start on or before the preceding
1136 * functional pipestat (i.e. other than WT or TD)
1137 */
1138 if (ctx->data_index <= ctx->pipe_index) {
1139 ctx->data_index = ctx->pipe_index + 1;
1140 ctx->data_half = 0;
1141 }
1142 }
1143
1144 ctx->pipe_index += 1;
1145 }
1146
1147 return ERROR_OK;
1148 }
1149
1150 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1151 uint32_t *mode)
1152 {
1153 uint32_t tracemode;
1154
1155 /* what parts of data access are traced? */
1156 if (strcmp(CMD_ARGV[0], "none") == 0)
1157 tracemode = 0;
1158 else if (strcmp(CMD_ARGV[0], "data") == 0)
1159 tracemode = ETM_CTRL_TRACE_DATA;
1160 else if (strcmp(CMD_ARGV[0], "address") == 0)
1161 tracemode = ETM_CTRL_TRACE_ADDR;
1162 else if (strcmp(CMD_ARGV[0], "all") == 0)
1163 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1164 else {
1165 command_print(CMD, "invalid option '%s'", CMD_ARGV[0]);
1166 return ERROR_COMMAND_SYNTAX_ERROR;
1167 }
1168
1169 uint8_t context_id;
1170 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1171 switch (context_id) {
1172 case 0:
1173 tracemode |= ETM_CTRL_CONTEXTID_NONE;
1174 break;
1175 case 8:
1176 tracemode |= ETM_CTRL_CONTEXTID_8;
1177 break;
1178 case 16:
1179 tracemode |= ETM_CTRL_CONTEXTID_16;
1180 break;
1181 case 32:
1182 tracemode |= ETM_CTRL_CONTEXTID_32;
1183 break;
1184 default:
1185 command_print(CMD, "invalid option '%s'", CMD_ARGV[1]);
1186 return ERROR_COMMAND_SYNTAX_ERROR;
1187 }
1188
1189 bool etmv1_cycle_accurate;
1190 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1191 if (etmv1_cycle_accurate)
1192 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1193
1194 bool etmv1_branch_output;
1195 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1196 if (etmv1_branch_output)
1197 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1198
1199 /* IGNORED:
1200 * - CPRT tracing (coprocessor register transfers)
1201 * - debug request (causes debug entry on trigger)
1202 * - stall on FIFOFULL (preventing tracedata loss)
1203 */
1204 *mode = tracemode;
1205
1206 return ERROR_OK;
1207 }
1208
1209 COMMAND_HANDLER(handle_etm_tracemode_command)
1210 {
1211 struct target *target = get_current_target(CMD_CTX);
1212 struct arm *arm = target_to_arm(target);
1213 struct etm_context *etm;
1214
1215 if (!is_arm(arm)) {
1216 command_print(CMD, "ETM: current target isn't an ARM");
1217 return ERROR_FAIL;
1218 }
1219
1220 etm = arm->etm;
1221 if (!etm) {
1222 command_print(CMD, "current target doesn't have an ETM configured");
1223 return ERROR_FAIL;
1224 }
1225
1226 uint32_t tracemode = etm->control;
1227
1228 switch (CMD_ARGC) {
1229 case 0:
1230 break;
1231 case 4:
1232 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1233 &tracemode);
1234 break;
1235 default:
1236 return ERROR_COMMAND_SYNTAX_ERROR;
1237 }
1238
1239 /**
1240 * todo: fail if parameters were invalid for this hardware,
1241 * or couldn't be written; display actual hardware state...
1242 */
1243
1244 command_print(CMD, "current tracemode configuration:");
1245
1246 switch (tracemode & ETM_CTRL_TRACE_MASK) {
1247 default:
1248 command_print(CMD, "data tracing: none");
1249 break;
1250 case ETM_CTRL_TRACE_DATA:
1251 command_print(CMD, "data tracing: data only");
1252 break;
1253 case ETM_CTRL_TRACE_ADDR:
1254 command_print(CMD, "data tracing: address only");
1255 break;
1256 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1257 command_print(CMD, "data tracing: address and data");
1258 break;
1259 }
1260
1261 switch (tracemode & ETM_CTRL_CONTEXTID_MASK) {
1262 case ETM_CTRL_CONTEXTID_NONE:
1263 command_print(CMD, "contextid tracing: none");
1264 break;
1265 case ETM_CTRL_CONTEXTID_8:
1266 command_print(CMD, "contextid tracing: 8 bit");
1267 break;
1268 case ETM_CTRL_CONTEXTID_16:
1269 command_print(CMD, "contextid tracing: 16 bit");
1270 break;
1271 case ETM_CTRL_CONTEXTID_32:
1272 command_print(CMD, "contextid tracing: 32 bit");
1273 break;
1274 }
1275
1276 if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1277 command_print(CMD, "cycle-accurate tracing enabled");
1278 else
1279 command_print(CMD, "cycle-accurate tracing disabled");
1280
1281 if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1282 command_print(CMD, "full branch address output enabled");
1283 else
1284 command_print(CMD, "full branch address output disabled");
1285
1286 #define TRACEMODE_MASK ( \
1287 ETM_CTRL_CONTEXTID_MASK \
1288 | ETM_CTRL_BRANCH_OUTPUT \
1289 | ETM_CTRL_CYCLE_ACCURATE \
1290 | ETM_CTRL_TRACE_MASK \
1291 )
1292
1293 /* only update ETM_CTRL register if tracemode changed */
1294 if ((etm->control & TRACEMODE_MASK) != tracemode) {
1295 struct reg *etm_ctrl_reg;
1296
1297 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1298 if (!etm_ctrl_reg)
1299 return ERROR_FAIL;
1300
1301 etm->control &= ~TRACEMODE_MASK;
1302 etm->control |= tracemode & TRACEMODE_MASK;
1303
1304 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1305 etm_store_reg(etm_ctrl_reg);
1306
1307 /* invalidate old trace data */
1308 etm->capture_status = TRACE_IDLE;
1309 if (etm->trace_depth > 0) {
1310 free(etm->trace_data);
1311 etm->trace_data = NULL;
1312 }
1313 etm->trace_depth = 0;
1314 }
1315
1316 #undef TRACEMODE_MASK
1317
1318 return ERROR_OK;
1319 }
1320
1321 COMMAND_HANDLER(handle_etm_config_command)
1322 {
1323 struct target *target;
1324 struct arm *arm;
1325 uint32_t portmode = 0x0;
1326 struct etm_context *etm_ctx;
1327 int i;
1328
1329 if (CMD_ARGC != 5)
1330 return ERROR_COMMAND_SYNTAX_ERROR;
1331
1332 target = get_target(CMD_ARGV[0]);
1333 if (!target) {
1334 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1335 return ERROR_FAIL;
1336 }
1337
1338 arm = target_to_arm(target);
1339 if (!is_arm(arm)) {
1340 command_print(CMD, "target '%s' is '%s'; not an ARM",
1341 target_name(target),
1342 target_type_name(target));
1343 return ERROR_FAIL;
1344 }
1345
1346 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1347 * version we'll be using!! -- so we can't know how to validate
1348 * params yet. "etm config" should likely be *AFTER* hookup...
1349 *
1350 * - Many more widths might be supported ... and we can easily
1351 * check whether our setting "took".
1352 *
1353 * - The "clock" and "mode" bits are interpreted differently.
1354 * See ARM IHI 0014O table 2-17 for the old behaviour, and
1355 * table 2-18 for the new. With ETB it's best to specify
1356 * "normal full" ...
1357 */
1358 uint8_t port_width;
1359 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1360 switch (port_width) {
1361 /* before ETMv3.0 */
1362 case 4:
1363 portmode |= ETM_PORT_4BIT;
1364 break;
1365 case 8:
1366 portmode |= ETM_PORT_8BIT;
1367 break;
1368 case 16:
1369 portmode |= ETM_PORT_16BIT;
1370 break;
1371 /* ETMv3.0 and later*/
1372 case 24:
1373 portmode |= ETM_PORT_24BIT;
1374 break;
1375 case 32:
1376 portmode |= ETM_PORT_32BIT;
1377 break;
1378 case 48:
1379 portmode |= ETM_PORT_48BIT;
1380 break;
1381 case 64:
1382 portmode |= ETM_PORT_64BIT;
1383 break;
1384 case 1:
1385 portmode |= ETM_PORT_1BIT;
1386 break;
1387 case 2:
1388 portmode |= ETM_PORT_2BIT;
1389 break;
1390 default:
1391 command_print(CMD,
1392 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1393 return ERROR_FAIL;
1394 }
1395
1396 if (strcmp("normal", CMD_ARGV[2]) == 0)
1397 portmode |= ETM_PORT_NORMAL;
1398 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1399 portmode |= ETM_PORT_MUXED;
1400 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1401 portmode |= ETM_PORT_DEMUXED;
1402 else {
1403 command_print(CMD,
1404 "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'",
1405 CMD_ARGV[2]);
1406 return ERROR_FAIL;
1407 }
1408
1409 if (strcmp("half", CMD_ARGV[3]) == 0)
1410 portmode |= ETM_PORT_HALF_CLOCK;
1411 else if (strcmp("full", CMD_ARGV[3]) == 0)
1412 portmode |= ETM_PORT_FULL_CLOCK;
1413 else {
1414 command_print(CMD,
1415 "unsupported ETM port clocking '%s', must be 'full' or 'half'",
1416 CMD_ARGV[3]);
1417 return ERROR_FAIL;
1418 }
1419
1420 etm_ctx = calloc(1, sizeof(struct etm_context));
1421 if (!etm_ctx) {
1422 LOG_DEBUG("out of memory");
1423 return ERROR_FAIL;
1424 }
1425
1426 for (i = 0; etm_capture_drivers[i]; i++) {
1427 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0) {
1428 int retval = register_commands(CMD_CTX, NULL,
1429 etm_capture_drivers[i]->commands);
1430 if (ERROR_OK != retval) {
1431 free(etm_ctx);
1432 return retval;
1433 }
1434
1435 etm_ctx->capture_driver = etm_capture_drivers[i];
1436
1437 break;
1438 }
1439 }
1440
1441 if (!etm_capture_drivers[i]) {
1442 /* no supported capture driver found, don't register an ETM */
1443 free(etm_ctx);
1444 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1445 return ERROR_FAIL;
1446 }
1447
1448 etm_ctx->target = target;
1449 etm_ctx->trace_data = NULL;
1450 etm_ctx->control = portmode;
1451 etm_ctx->core_state = ARM_STATE_ARM;
1452
1453 arm->etm = etm_ctx;
1454
1455 return etm_register_user_commands(CMD_CTX);
1456 }
1457
1458 COMMAND_HANDLER(handle_etm_info_command)
1459 {
1460 struct target *target;
1461 struct arm *arm;
1462 struct etm_context *etm;
1463 struct reg *etm_sys_config_reg;
1464 int max_port_size;
1465 uint32_t config;
1466
1467 target = get_current_target(CMD_CTX);
1468 arm = target_to_arm(target);
1469 if (!is_arm(arm)) {
1470 command_print(CMD, "ETM: current target isn't an ARM");
1471 return ERROR_FAIL;
1472 }
1473
1474 etm = arm->etm;
1475 if (!etm) {
1476 command_print(CMD, "current target doesn't have an ETM configured");
1477 return ERROR_FAIL;
1478 }
1479
1480 command_print(CMD, "ETM v%d.%d",
1481 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1482 command_print(CMD, "pairs of address comparators: %i",
1483 (int) (etm->config >> 0) & 0x0f);
1484 command_print(CMD, "data comparators: %i",
1485 (int) (etm->config >> 4) & 0x0f);
1486 command_print(CMD, "memory map decoders: %i",
1487 (int) (etm->config >> 8) & 0x1f);
1488 command_print(CMD, "number of counters: %i",
1489 (int) (etm->config >> 13) & 0x07);
1490 command_print(CMD, "sequencer %spresent",
1491 (int) (etm->config & (1 << 16)) ? "" : "not ");
1492 command_print(CMD, "number of ext. inputs: %i",
1493 (int) (etm->config >> 17) & 0x07);
1494 command_print(CMD, "number of ext. outputs: %i",
1495 (int) (etm->config >> 20) & 0x07);
1496 command_print(CMD, "FIFO full %spresent",
1497 (int) (etm->config & (1 << 23)) ? "" : "not ");
1498 if (etm->bcd_vers < 0x20)
1499 command_print(CMD, "protocol version: %i",
1500 (int) (etm->config >> 28) & 0x07);
1501 else {
1502 command_print(CMD,
1503 "coprocessor and memory access %ssupported",
1504 (etm->config & (1 << 26)) ? "" : "not ");
1505 command_print(CMD, "trace start/stop %spresent",
1506 (etm->config & (1 << 26)) ? "" : "not ");
1507 command_print(CMD, "number of context comparators: %i",
1508 (int) (etm->config >> 24) & 0x03);
1509 }
1510
1511 /* SYS_CONFIG isn't present before ETMv1.2 */
1512 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1513 if (!etm_sys_config_reg)
1514 return ERROR_OK;
1515
1516 etm_get_reg(etm_sys_config_reg);
1517 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1518
1519 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1520
1521 max_port_size = config & 0x7;
1522 if (etm->bcd_vers >= 0x30)
1523 max_port_size |= (config >> 6) & 0x08;
1524 switch (max_port_size) {
1525 /* before ETMv3.0 */
1526 case 0:
1527 max_port_size = 4;
1528 break;
1529 case 1:
1530 max_port_size = 8;
1531 break;
1532 case 2:
1533 max_port_size = 16;
1534 break;
1535 /* ETMv3.0 and later*/
1536 case 3:
1537 max_port_size = 24;
1538 break;
1539 case 4:
1540 max_port_size = 32;
1541 break;
1542 case 5:
1543 max_port_size = 48;
1544 break;
1545 case 6:
1546 max_port_size = 64;
1547 break;
1548 case 8:
1549 max_port_size = 1;
1550 break;
1551 case 9:
1552 max_port_size = 2;
1553 break;
1554 default:
1555 LOG_ERROR("Illegal max_port_size");
1556 return ERROR_FAIL;
1557 }
1558 command_print(CMD, "max. port size: %i", max_port_size);
1559
1560 if (etm->bcd_vers < 0x30) {
1561 command_print(CMD, "half-rate clocking %ssupported",
1562 (config & (1 << 3)) ? "" : "not ");
1563 command_print(CMD, "full-rate clocking %ssupported",
1564 (config & (1 << 4)) ? "" : "not ");
1565 command_print(CMD, "normal trace format %ssupported",
1566 (config & (1 << 5)) ? "" : "not ");
1567 command_print(CMD, "multiplex trace format %ssupported",
1568 (config & (1 << 6)) ? "" : "not ");
1569 command_print(CMD, "demultiplex trace format %ssupported",
1570 (config & (1 << 7)) ? "" : "not ");
1571 } else {
1572 /* REVISIT show which size and format are selected ... */
1573 command_print(CMD, "current port size %ssupported",
1574 (config & (1 << 10)) ? "" : "not ");
1575 command_print(CMD, "current trace format %ssupported",
1576 (config & (1 << 11)) ? "" : "not ");
1577 }
1578 if (etm->bcd_vers >= 0x21)
1579 command_print(CMD, "fetch comparisons %ssupported",
1580 (config & (1 << 17)) ? "not " : "");
1581 command_print(CMD, "FIFO full %ssupported",
1582 (config & (1 << 8)) ? "" : "not ");
1583
1584 return ERROR_OK;
1585 }
1586
1587 COMMAND_HANDLER(handle_etm_status_command)
1588 {
1589 struct target *target;
1590 struct arm *arm;
1591 struct etm_context *etm;
1592 trace_status_t trace_status;
1593
1594 target = get_current_target(CMD_CTX);
1595 arm = target_to_arm(target);
1596 if (!is_arm(arm)) {
1597 command_print(CMD, "ETM: current target isn't an ARM");
1598 return ERROR_FAIL;
1599 }
1600
1601 etm = arm->etm;
1602 if (!etm) {
1603 command_print(CMD, "current target doesn't have an ETM configured");
1604 return ERROR_FAIL;
1605 }
1606
1607 /* ETM status */
1608 if (etm->bcd_vers >= 0x11) {
1609 struct reg *reg;
1610
1611 reg = etm_reg_lookup(etm, ETM_STATUS);
1612 if (!reg)
1613 return ERROR_FAIL;
1614 if (etm_get_reg(reg) == ERROR_OK) {
1615 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1616
1617 command_print(CMD, "etm: %s%s%s%s",
1618 /* bit(1) == progbit */
1619 (etm->bcd_vers >= 0x12)
1620 ? ((s & (1 << 1))
1621 ? "disabled" : "enabled")
1622 : "?",
1623 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1624 ? " triggered" : "",
1625 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1626 ? " start/stop" : "",
1627 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1628 ? " untraced-overflow" : "");
1629 } /* else ignore and try showing trace port status */
1630 }
1631
1632 /* Trace Port Driver status */
1633 trace_status = etm->capture_driver->status(etm);
1634 if (trace_status == TRACE_IDLE)
1635 command_print(CMD, "%s: idle", etm->capture_driver->name);
1636 else {
1637 static char *completed = " completed";
1638 static char *running = " is running";
1639 static char *overflowed = ", overflowed";
1640 static char *triggered = ", triggered";
1641
1642 command_print(CMD, "%s: trace collection%s%s%s",
1643 etm->capture_driver->name,
1644 (trace_status & TRACE_RUNNING) ? running : completed,
1645 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1646 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1647
1648 if (etm->trace_depth > 0) {
1649 command_print(CMD, "%i frames of trace data read",
1650 (int)(etm->trace_depth));
1651 }
1652 }
1653
1654 return ERROR_OK;
1655 }
1656
1657 COMMAND_HANDLER(handle_etm_image_command)
1658 {
1659 struct target *target;
1660 struct arm *arm;
1661 struct etm_context *etm_ctx;
1662
1663 if (CMD_ARGC < 1)
1664 return ERROR_COMMAND_SYNTAX_ERROR;
1665
1666 target = get_current_target(CMD_CTX);
1667 arm = target_to_arm(target);
1668 if (!is_arm(arm)) {
1669 command_print(CMD, "ETM: current target isn't an ARM");
1670 return ERROR_FAIL;
1671 }
1672
1673 etm_ctx = arm->etm;
1674 if (!etm_ctx) {
1675 command_print(CMD, "current target doesn't have an ETM configured");
1676 return ERROR_FAIL;
1677 }
1678
1679 if (etm_ctx->image) {
1680 image_close(etm_ctx->image);
1681 free(etm_ctx->image);
1682 command_print(CMD, "previously loaded image found and closed");
1683 }
1684
1685 etm_ctx->image = malloc(sizeof(struct image));
1686 etm_ctx->image->base_address_set = 0;
1687 etm_ctx->image->start_address_set = 0;
1688
1689 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1690 if (CMD_ARGC >= 2) {
1691 etm_ctx->image->base_address_set = 1;
1692 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address);
1693 } else
1694 etm_ctx->image->base_address_set = 0;
1695
1696 if (image_open(etm_ctx->image, CMD_ARGV[0],
1697 (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) {
1698 free(etm_ctx->image);
1699 etm_ctx->image = NULL;
1700 return ERROR_FAIL;
1701 }
1702
1703 return ERROR_OK;
1704 }
1705
1706 COMMAND_HANDLER(handle_etm_dump_command)
1707 {
1708 struct fileio *file;
1709 struct target *target;
1710 struct arm *arm;
1711 struct etm_context *etm_ctx;
1712 uint32_t i;
1713
1714 if (CMD_ARGC != 1)
1715 return ERROR_COMMAND_SYNTAX_ERROR;
1716
1717 target = get_current_target(CMD_CTX);
1718 arm = target_to_arm(target);
1719 if (!is_arm(arm)) {
1720 command_print(CMD, "ETM: current target isn't an ARM");
1721 return ERROR_FAIL;
1722 }
1723
1724 etm_ctx = arm->etm;
1725 if (!etm_ctx) {
1726 command_print(CMD, "current target doesn't have an ETM configured");
1727 return ERROR_FAIL;
1728 }
1729
1730 if (etm_ctx->capture_driver->status == TRACE_IDLE) {
1731 command_print(CMD, "trace capture wasn't enabled, no trace data captured");
1732 return ERROR_OK;
1733 }
1734
1735 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
1736 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1737 command_print(CMD, "trace capture not completed");
1738 return ERROR_FAIL;
1739 }
1740
1741 /* read the trace data if it wasn't read already */
1742 if (etm_ctx->trace_depth == 0)
1743 etm_ctx->capture_driver->read_trace(etm_ctx);
1744
1745 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1746 return ERROR_FAIL;
1747
1748 fileio_write_u32(file, etm_ctx->capture_status);
1749 fileio_write_u32(file, etm_ctx->control);
1750 fileio_write_u32(file, etm_ctx->trace_depth);
1751
1752 for (i = 0; i < etm_ctx->trace_depth; i++) {
1753 fileio_write_u32(file, etm_ctx->trace_data[i].pipestat);
1754 fileio_write_u32(file, etm_ctx->trace_data[i].packet);
1755 fileio_write_u32(file, etm_ctx->trace_data[i].flags);
1756 }
1757
1758 fileio_close(file);
1759
1760 return ERROR_OK;
1761 }
1762
1763 COMMAND_HANDLER(handle_etm_load_command)
1764 {
1765 struct fileio *file;
1766 struct target *target;
1767 struct arm *arm;
1768 struct etm_context *etm_ctx;
1769 uint32_t i;
1770
1771 if (CMD_ARGC != 1)
1772 return ERROR_COMMAND_SYNTAX_ERROR;
1773
1774 target = get_current_target(CMD_CTX);
1775 arm = target_to_arm(target);
1776 if (!is_arm(arm)) {
1777 command_print(CMD, "ETM: current target isn't an ARM");
1778 return ERROR_FAIL;
1779 }
1780
1781 etm_ctx = arm->etm;
1782 if (!etm_ctx) {
1783 command_print(CMD, "current target doesn't have an ETM configured");
1784 return ERROR_FAIL;
1785 }
1786
1787 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
1788 command_print(CMD, "trace capture running, stop first");
1789 return ERROR_FAIL;
1790 }
1791
1792 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1793 return ERROR_FAIL;
1794
1795 size_t filesize;
1796 int retval = fileio_size(file, &filesize);
1797 if (retval != ERROR_OK) {
1798 fileio_close(file);
1799 return retval;
1800 }
1801
1802 if (filesize % 4) {
1803 command_print(CMD, "size isn't a multiple of 4, no valid trace data");
1804 fileio_close(file);
1805 return ERROR_FAIL;
1806 }
1807
1808 if (etm_ctx->trace_depth > 0) {
1809 free(etm_ctx->trace_data);
1810 etm_ctx->trace_data = NULL;
1811 }
1812
1813 {
1814 uint32_t tmp;
1815 fileio_read_u32(file, &tmp); etm_ctx->capture_status = tmp;
1816 fileio_read_u32(file, &tmp); etm_ctx->control = tmp;
1817 fileio_read_u32(file, &etm_ctx->trace_depth);
1818 }
1819 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1820 if (etm_ctx->trace_data == NULL) {
1821 command_print(CMD, "not enough memory to perform operation");
1822 fileio_close(file);
1823 return ERROR_FAIL;
1824 }
1825
1826 for (i = 0; i < etm_ctx->trace_depth; i++) {
1827 uint32_t pipestat, packet, flags;
1828 fileio_read_u32(file, &pipestat);
1829 fileio_read_u32(file, &packet);
1830 fileio_read_u32(file, &flags);
1831 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1832 etm_ctx->trace_data[i].packet = packet & 0xffff;
1833 etm_ctx->trace_data[i].flags = flags;
1834 }
1835
1836 fileio_close(file);
1837
1838 return ERROR_OK;
1839 }
1840
1841 COMMAND_HANDLER(handle_etm_start_command)
1842 {
1843 struct target *target;
1844 struct arm *arm;
1845 struct etm_context *etm_ctx;
1846 struct reg *etm_ctrl_reg;
1847
1848 target = get_current_target(CMD_CTX);
1849 arm = target_to_arm(target);
1850 if (!is_arm(arm)) {
1851 command_print(CMD, "ETM: current target isn't an ARM");
1852 return ERROR_FAIL;
1853 }
1854
1855 etm_ctx = arm->etm;
1856 if (!etm_ctx) {
1857 command_print(CMD, "current target doesn't have an ETM configured");
1858 return ERROR_FAIL;
1859 }
1860
1861 /* invalidate old tracing data */
1862 etm_ctx->capture_status = TRACE_IDLE;
1863 if (etm_ctx->trace_depth > 0) {
1864 free(etm_ctx->trace_data);
1865 etm_ctx->trace_data = NULL;
1866 }
1867 etm_ctx->trace_depth = 0;
1868
1869 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1870 if (!etm_ctrl_reg)
1871 return ERROR_FAIL;
1872
1873 etm_get_reg(etm_ctrl_reg);
1874
1875 /* Clear programming bit (10), set port selection bit (11) */
1876 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1877
1878 etm_store_reg(etm_ctrl_reg);
1879 jtag_execute_queue();
1880
1881 etm_ctx->capture_driver->start_capture(etm_ctx);
1882
1883 return ERROR_OK;
1884 }
1885
1886 COMMAND_HANDLER(handle_etm_stop_command)
1887 {
1888 struct target *target;
1889 struct arm *arm;
1890 struct etm_context *etm_ctx;
1891 struct reg *etm_ctrl_reg;
1892
1893 target = get_current_target(CMD_CTX);
1894 arm = target_to_arm(target);
1895 if (!is_arm(arm)) {
1896 command_print(CMD, "ETM: current target isn't an ARM");
1897 return ERROR_FAIL;
1898 }
1899
1900 etm_ctx = arm->etm;
1901 if (!etm_ctx) {
1902 command_print(CMD, "current target doesn't have an ETM configured");
1903 return ERROR_FAIL;
1904 }
1905
1906 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1907 if (!etm_ctrl_reg)
1908 return ERROR_FAIL;
1909
1910 etm_get_reg(etm_ctrl_reg);
1911
1912 /* Set programming bit (10), clear port selection bit (11) */
1913 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1914
1915 etm_store_reg(etm_ctrl_reg);
1916 jtag_execute_queue();
1917
1918 etm_ctx->capture_driver->stop_capture(etm_ctx);
1919
1920 return ERROR_OK;
1921 }
1922
1923 COMMAND_HANDLER(handle_etm_trigger_debug_command)
1924 {
1925 struct target *target;
1926 struct arm *arm;
1927 struct etm_context *etm;
1928
1929 target = get_current_target(CMD_CTX);
1930 arm = target_to_arm(target);
1931 if (!is_arm(arm)) {
1932 command_print(CMD, "ETM: %s isn't an ARM",
1933 target_name(target));
1934 return ERROR_FAIL;
1935 }
1936
1937 etm = arm->etm;
1938 if (!etm) {
1939 command_print(CMD, "ETM: no ETM configured for %s",
1940 target_name(target));
1941 return ERROR_FAIL;
1942 }
1943
1944 if (CMD_ARGC == 1) {
1945 struct reg *etm_ctrl_reg;
1946 bool dbgrq;
1947
1948 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1949 if (!etm_ctrl_reg)
1950 return ERROR_FAIL;
1951
1952 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
1953 if (dbgrq)
1954 etm->control |= ETM_CTRL_DBGRQ;
1955 else
1956 etm->control &= ~ETM_CTRL_DBGRQ;
1957
1958 /* etm->control will be written to hardware
1959 * the next time an "etm start" is issued.
1960 */
1961 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1962 }
1963
1964 command_print(CMD, "ETM: %s debug halt",
1965 (etm->control & ETM_CTRL_DBGRQ)
1966 ? "triggers"
1967 : "does not trigger");
1968 return ERROR_OK;
1969 }
1970
1971 COMMAND_HANDLER(handle_etm_analyze_command)
1972 {
1973 struct target *target;
1974 struct arm *arm;
1975 struct etm_context *etm_ctx;
1976 int retval;
1977
1978 target = get_current_target(CMD_CTX);
1979 arm = target_to_arm(target);
1980 if (!is_arm(arm)) {
1981 command_print(CMD, "ETM: current target isn't an ARM");
1982 return ERROR_FAIL;
1983 }
1984
1985 etm_ctx = arm->etm;
1986 if (!etm_ctx) {
1987 command_print(CMD, "current target doesn't have an ETM configured");
1988 return ERROR_FAIL;
1989 }
1990
1991 retval = etmv1_analyze_trace(etm_ctx, CMD);
1992 if (retval != ERROR_OK) {
1993 /* FIX! error should be reported inside etmv1_analyze_trace() */
1994 switch (retval) {
1995 case ERROR_ETM_ANALYSIS_FAILED:
1996 command_print(CMD,
1997 "further analysis failed (corrupted trace data or just end of data");
1998 break;
1999 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2000 command_print(CMD,
2001 "no instruction for current address available, analysis aborted");
2002 break;
2003 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2004 command_print(CMD, "no image available for trace analysis");
2005 break;
2006 default:
2007 command_print(CMD, "unknown error");
2008 }
2009 }
2010
2011 return retval;
2012 }
2013
2014 static const struct command_registration etm_config_command_handlers[] = {
2015 {
2016 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2017 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2018 *
2019 * Also, these parameters don't match ETM v3+ modules...
2020 */
2021 .name = "config",
2022 .handler = handle_etm_config_command,
2023 .mode = COMMAND_CONFIG,
2024 .help = "Set up ETM output port.",
2025 .usage = "target port_width port_mode clocking capture_driver",
2026 },
2027 COMMAND_REGISTRATION_DONE
2028 };
2029 const struct command_registration etm_command_handlers[] = {
2030 {
2031 .name = "etm",
2032 .mode = COMMAND_ANY,
2033 .help = "Embedded Trace Macrocell command group",
2034 .usage = "",
2035 .chain = etm_config_command_handlers,
2036 },
2037 COMMAND_REGISTRATION_DONE
2038 };
2039
2040 static const struct command_registration etm_exec_command_handlers[] = {
2041 {
2042 .name = "tracemode",
2043 .handler = handle_etm_tracemode_command,
2044 .mode = COMMAND_EXEC,
2045 .help = "configure/display trace mode",
2046 .usage = "('none'|'data'|'address'|'all') "
2047 "context_id_bits "
2048 "['enable'|'disable'] "
2049 "['enable'|'disable']",
2050 },
2051 {
2052 .name = "info",
2053 .handler = handle_etm_info_command,
2054 .mode = COMMAND_EXEC,
2055 .usage = "",
2056 .help = "display info about the current target's ETM",
2057 },
2058 {
2059 .name = "status",
2060 .handler = handle_etm_status_command,
2061 .mode = COMMAND_EXEC,
2062 .usage = "",
2063 .help = "display current target's ETM status",
2064 },
2065 {
2066 .name = "start",
2067 .handler = handle_etm_start_command,
2068 .mode = COMMAND_EXEC,
2069 .usage = "",
2070 .help = "start ETM trace collection",
2071 },
2072 {
2073 .name = "stop",
2074 .handler = handle_etm_stop_command,
2075 .mode = COMMAND_EXEC,
2076 .usage = "",
2077 .help = "stop ETM trace collection",
2078 },
2079 {
2080 .name = "trigger_debug",
2081 .handler = handle_etm_trigger_debug_command,
2082 .mode = COMMAND_EXEC,
2083 .help = "enable/disable debug entry on trigger",
2084 .usage = "['enable'|'disable']",
2085 },
2086 {
2087 .name = "analyze",
2088 .handler = handle_etm_analyze_command,
2089 .mode = COMMAND_EXEC,
2090 .usage = "",
2091 .help = "analyze collected ETM trace",
2092 },
2093 {
2094 .name = "image",
2095 .handler = handle_etm_image_command,
2096 .mode = COMMAND_EXEC,
2097 .help = "load image from file with optional offset",
2098 .usage = "<file> [base address] [type]",
2099 },
2100 {
2101 .name = "dump",
2102 .handler = handle_etm_dump_command,
2103 .mode = COMMAND_EXEC,
2104 .help = "dump captured trace data to file",
2105 .usage = "filename",
2106 },
2107 {
2108 .name = "load",
2109 .handler = handle_etm_load_command,
2110 .mode = COMMAND_EXEC,
2111 .usage = "",
2112 .help = "load trace data for analysis <file>",
2113 },
2114 COMMAND_REGISTRATION_DONE
2115 };
2116
2117 static int etm_register_user_commands(struct command_context *cmd_ctx)
2118 {
2119 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2120 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2121 }
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