1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "arm7_9_common.h"
28 #include "arm_disassembler.h"
32 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
34 * ETM modules collect instruction and/or data trace information, compress
35 * it, and transfer it to a debugging host through either a (buffered) trace
36 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
38 * There are several generations of these modules. Original versions have
39 * JTAG access through a dedicated scan chain. Recent versions have added
40 * access via coprocessor instructions, memory addressing, and the ARM Debug
41 * Interface v5 (ADIv5); and phased out direct JTAG access.
43 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
44 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
45 * implying non-JTAG connectivity options.
47 * Relevant documentation includes:
48 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
49 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
50 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
53 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
63 uint8_t size
; /* low-N of 32 bits */
64 uint8_t mode
; /* RO, WO, RW */
65 uint8_t bcd_vers
; /* 1.0, 2.0, etc */
70 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
71 * (Or on some processors, through coprocessor operations.)
72 * Newer versions of ETM make some W/O registers R/W, and
73 * provide definitions for some previously-unused bits.
76 /* basic registers that are always there given the right ETM version */
77 static const struct etm_reg_info etm_core
[] = {
78 /* NOTE: we "know" ETM_CONFIG is listed first */
79 { ETM_CONFIG
, 32, RO
, 0x10, "ETM_config", },
81 /* ETM Trace Registers */
82 { ETM_CTRL
, 32, RW
, 0x10, "ETM_ctrl", },
83 { ETM_TRIG_EVENT
, 17, WO
, 0x10, "ETM_trig_event", },
84 { ETM_ASIC_CTRL
, 8, WO
, 0x10, "ETM_asic_ctrl", },
85 { ETM_STATUS
, 3, RO
, 0x11, "ETM_status", },
86 { ETM_SYS_CONFIG
, 9, RO
, 0x12, "ETM_sys_config", },
88 /* TraceEnable configuration */
89 { ETM_TRACE_RESOURCE_CTRL
, 32, WO
, 0x12, "ETM_trace_resource_ctrl", },
90 { ETM_TRACE_EN_CTRL2
, 16, WO
, 0x12, "ETM_trace_en_ctrl2", },
91 { ETM_TRACE_EN_EVENT
, 17, WO
, 0x10, "ETM_trace_en_event", },
92 { ETM_TRACE_EN_CTRL1
, 26, WO
, 0x10, "ETM_trace_en_ctrl1", },
94 /* ViewData configuration (data trace) */
95 { ETM_VIEWDATA_EVENT
, 17, WO
, 0x10, "ETM_viewdata_event", },
96 { ETM_VIEWDATA_CTRL1
, 32, WO
, 0x10, "ETM_viewdata_ctrl1", },
97 { ETM_VIEWDATA_CTRL2
, 32, WO
, 0x10, "ETM_viewdata_ctrl2", },
98 { ETM_VIEWDATA_CTRL3
, 17, WO
, 0x10, "ETM_viewdata_ctrl3", },
100 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
102 { 0x78, 12, WO
, 0x20, "ETM_sync_freq", },
103 { 0x79, 32, RO
, 0x20, "ETM_id", },
106 static const struct etm_reg_info etm_fifofull
[] = {
107 /* FIFOFULL configuration */
108 { ETM_FIFOFULL_REGION
, 25, WO
, 0x10, "ETM_fifofull_region", },
109 { ETM_FIFOFULL_LEVEL
, 8, WO
, 0x10, "ETM_fifofull_level", },
112 static const struct etm_reg_info etm_addr_comp
[] = {
113 /* Address comparator register pairs */
114 #define ADDR_COMPARATOR(i) \
115 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
116 "ETM_addr_" #i "_comparator_value", }, \
117 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
118 "ETM_addr_" #i "_access_type", }
136 #undef ADDR_COMPARATOR
139 static const struct etm_reg_info etm_data_comp
[] = {
140 /* Data Value Comparators (NOTE: odd addresses are reserved) */
141 #define DATA_COMPARATOR(i) \
142 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
143 "ETM_data_" #i "_comparator_value", }, \
144 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
145 "ETM_data_" #i "_comparator_mask", }
154 #undef DATA_COMPARATOR
157 static const struct etm_reg_info etm_counters
[] = {
158 #define ETM_COUNTER(i) \
159 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
160 "ETM_counter_" #i "_reload_value", }, \
161 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
162 "ETM_counter_" #i "_enable", }, \
163 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
164 "ETM_counter_" #i "_reload_event", }, \
165 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
166 "ETM_counter_" #i "_value", }
174 static const struct etm_reg_info etm_sequencer
[] = {
176 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
177 "ETM_sequencer_event" #i, }
178 ETM_SEQ(0), /* 1->2 */
179 ETM_SEQ(1), /* 2->1 */
180 ETM_SEQ(2), /* 2->3 */
181 ETM_SEQ(3), /* 3->1 */
182 ETM_SEQ(4), /* 3->2 */
183 ETM_SEQ(5), /* 1->3 */
186 { ETM_SEQUENCER_STATE
, 2, RO
, 0x10, "ETM_sequencer_state", },
189 static const struct etm_reg_info etm_outputs
[] = {
190 #define ETM_OUTPUT(i) \
191 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
192 "ETM_external_output" #i, }
202 /* registers from 0x6c..0x7f were added after ETMv1.3 */
204 /* Context ID Comparators */
205 { 0x6c, 32, RO
, 0x20, "ETM_contextid_comparator_value1", }
206 { 0x6d, 32, RO
, 0x20, "ETM_contextid_comparator_value2", }
207 { 0x6e, 32, RO
, 0x20, "ETM_contextid_comparator_value3", }
208 { 0x6f, 32, RO
, 0x20, "ETM_contextid_comparator_mask", }
211 static int etm_reg_arch_type
= -1;
213 static int etm_get_reg(reg_t
*reg
);
214 static int etm_read_reg_w_check(reg_t
*reg
,
215 uint8_t* check_value
, uint8_t* check_mask
);
216 static int etm_register_user_commands(struct command_context_s
*cmd_ctx
);
217 static int etm_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
);
218 static int etm_write_reg(reg_t
*reg
, uint32_t value
);
220 static command_t
*etm_cmd
;
223 /* Look up register by ID ... most ETM instances only
224 * support a subset of the possible registers.
226 static reg_t
*etm_reg_lookup(etm_context_t
*etm_ctx
, unsigned id
)
228 reg_cache_t
*cache
= etm_ctx
->reg_cache
;
231 for (i
= 0; i
< cache
->num_regs
; i
++) {
232 struct etm_reg_s
*reg
= cache
->reg_list
[i
].arch_info
;
234 if (reg
->reg_info
->addr
== id
)
235 return &cache
->reg_list
[i
];
238 /* caller asking for nonexistent register is a bug! */
239 /* REVISIT say which of the N targets was involved */
240 LOG_ERROR("ETM: register 0x%02x not available", id
);
244 static void etm_reg_add(unsigned bcd_vers
, arm_jtag_t
*jtag_info
,
245 reg_cache_t
*cache
, etm_reg_t
*ereg
,
246 const struct etm_reg_info
*r
, unsigned nreg
)
248 reg_t
*reg
= cache
->reg_list
;
250 reg
+= cache
->num_regs
;
251 ereg
+= cache
->num_regs
;
253 /* add up to "nreg" registers from "r", if supported by this
254 * version of the ETM, to the specified cache.
256 for (; nreg
--; r
++) {
258 /* this ETM may be too old to have some registers */
259 if (r
->bcd_vers
> bcd_vers
)
264 reg
->value
= &ereg
->value
;
265 reg
->arch_info
= ereg
;
266 reg
->arch_type
= etm_reg_arch_type
;
271 ereg
->jtag_info
= jtag_info
;
276 reg_cache_t
*etm_build_reg_cache(target_t
*target
,
277 arm_jtag_t
*jtag_info
, etm_context_t
*etm_ctx
)
279 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
280 reg_t
*reg_list
= NULL
;
281 etm_reg_t
*arch_info
= NULL
;
282 unsigned bcd_vers
, config
;
284 /* register a register arch-type for etm registers only once */
285 if (etm_reg_arch_type
== -1)
286 etm_reg_arch_type
= register_reg_arch_type(etm_get_reg
,
289 /* the actual registers are kept in two arrays */
290 reg_list
= calloc(128, sizeof(reg_t
));
291 arch_info
= calloc(128, sizeof(etm_reg_t
));
293 /* fill in values for the reg cache */
294 reg_cache
->name
= "etm registers";
295 reg_cache
->next
= NULL
;
296 reg_cache
->reg_list
= reg_list
;
297 reg_cache
->num_regs
= 0;
299 /* add ETM_CONFIG, then parse its values to see
300 * which other registers exist in this ETM
302 etm_reg_add(0x10, jtag_info
, reg_cache
, arch_info
,
305 etm_get_reg(reg_list
);
306 etm_ctx
->config
= buf_get_u32((void *)&arch_info
->value
, 0, 32);
307 config
= etm_ctx
->config
;
309 /* figure ETM version then add base registers */
310 if (config
& (1 << 31)) {
312 LOG_WARNING("ETMv2+ support is incomplete");
314 /* REVISIT read ID register, distinguish ETMv3.3 etc;
315 * don't presume trace start/stop support is present;
316 * and include any context ID comparator registers.
319 switch (config
>> 28) {
336 LOG_WARNING("Bad ETMv1 protocol %d", config
>> 28);
343 etm_ctx
->bcd_vers
= bcd_vers
;
344 LOG_INFO("ETM v%d.%d", bcd_vers
>> 4, bcd_vers
& 0xf);
346 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
347 etm_core
+ 1, ARRAY_SIZE(etm_core
) - 1);
349 /* address and data comparators; counters; outputs */
350 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
351 etm_addr_comp
, 4 * (0x0f & (config
>> 0)));
352 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
353 etm_data_comp
, 2 * (0x0f & (config
>> 4)));
354 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
355 etm_counters
, 4 * (0x07 & (config
>> 13)));
356 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
357 etm_outputs
, (0x07 & (config
>> 20)));
359 /* FIFOFULL presence is optional
360 * REVISIT for ETMv1.2 and later, don't bother adding this
361 * unless ETM_SYS_CONFIG says it's also *supported* ...
363 if (config
& (1 << 23))
364 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
365 etm_fifofull
, ARRAY_SIZE(etm_fifofull
));
367 /* sequencer is optional (for state-dependant triggering) */
368 if (config
& (1 << 16))
369 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
370 etm_sequencer
, ARRAY_SIZE(etm_sequencer
));
372 /* REVISIT could realloc and likely save half the memory
373 * in the two chunks we allocated...
376 /* the ETM might have an ETB connected */
377 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0)
379 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
383 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
390 reg_cache
->next
= etb_build_reg_cache(etb
);
392 etb
->reg_cache
= reg_cache
->next
;
399 static int etm_read_reg(reg_t
*reg
)
401 return etm_read_reg_w_check(reg
, NULL
, NULL
);
404 static int etm_store_reg(reg_t
*reg
)
406 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
409 int etm_setup(target_t
*target
)
412 uint32_t etm_ctrl_value
;
413 armv4_5_common_t
*armv4_5
= target
->arch_info
;
414 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
415 etm_context_t
*etm_ctx
= arm7_9
->etm_ctx
;
418 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
422 /* initialize some ETM control register settings */
423 etm_get_reg(etm_ctrl_reg
);
424 etm_ctrl_value
= buf_get_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
);
426 /* clear the ETM powerdown bit (0) */
427 etm_ctrl_value
&= ~0x1;
429 /* configure port width (6:4), mode (17:16) and clocking (13) */
430 etm_ctrl_value
= (etm_ctrl_value
&
431 ~ETM_PORT_WIDTH_MASK
& ~ETM_PORT_MODE_MASK
& ~ETM_PORT_CLOCK_MASK
)
434 buf_set_u32(etm_ctrl_reg
->value
, 0, etm_ctrl_reg
->size
, etm_ctrl_value
);
435 etm_store_reg(etm_ctrl_reg
);
437 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
440 if ((retval
= etm_ctx
->capture_driver
->init(etm_ctx
)) != ERROR_OK
)
442 LOG_ERROR("ETM capture driver initialization failed");
448 static int etm_get_reg(reg_t
*reg
)
452 if ((retval
= etm_read_reg(reg
)) != ERROR_OK
)
454 LOG_ERROR("BUG: error scheduling etm register read");
458 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
460 LOG_ERROR("register read failed");
467 static int etm_read_reg_w_check(reg_t
*reg
,
468 uint8_t* check_value
, uint8_t* check_mask
)
470 etm_reg_t
*etm_reg
= reg
->arch_info
;
471 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
472 uint8_t reg_addr
= r
->addr
& 0x7f;
473 scan_field_t fields
[3];
475 if (etm_reg
->reg_info
->mode
== WO
) {
476 LOG_ERROR("BUG: can't read write-only register %s", r
->name
);
477 return ERROR_INVALID_ARGUMENTS
;
480 LOG_DEBUG("%s (%u)", r
->name
, reg_addr
);
482 jtag_set_end_state(TAP_IDLE
);
483 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
484 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
486 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
487 fields
[0].num_bits
= 32;
488 fields
[0].out_value
= reg
->value
;
489 fields
[0].in_value
= NULL
;
490 fields
[0].check_value
= NULL
;
491 fields
[0].check_mask
= NULL
;
493 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
494 fields
[1].num_bits
= 7;
495 fields
[1].out_value
= malloc(1);
496 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
497 fields
[1].in_value
= NULL
;
498 fields
[1].check_value
= NULL
;
499 fields
[1].check_mask
= NULL
;
501 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
502 fields
[2].num_bits
= 1;
503 fields
[2].out_value
= malloc(1);
504 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
505 fields
[2].in_value
= NULL
;
506 fields
[2].check_value
= NULL
;
507 fields
[2].check_mask
= NULL
;
509 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
511 fields
[0].in_value
= reg
->value
;
512 fields
[0].check_value
= check_value
;
513 fields
[0].check_mask
= check_mask
;
515 jtag_add_dr_scan_check(3, fields
, jtag_get_end_state());
517 free(fields
[1].out_value
);
518 free(fields
[2].out_value
);
523 static int etm_set_reg(reg_t
*reg
, uint32_t value
)
527 if ((retval
= etm_write_reg(reg
, value
)) != ERROR_OK
)
529 LOG_ERROR("BUG: error scheduling etm register write");
533 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
540 static int etm_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
)
544 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
546 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
548 LOG_ERROR("register write failed");
554 static int etm_write_reg(reg_t
*reg
, uint32_t value
)
556 etm_reg_t
*etm_reg
= reg
->arch_info
;
557 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
558 uint8_t reg_addr
= r
->addr
& 0x7f;
559 scan_field_t fields
[3];
561 if (etm_reg
->reg_info
->mode
== RO
) {
562 LOG_ERROR("BUG: can't write read--only register %s", r
->name
);
563 return ERROR_INVALID_ARGUMENTS
;
566 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32
"", r
->name
, reg_addr
, value
);
568 jtag_set_end_state(TAP_IDLE
);
569 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
570 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
572 fields
[0].tap
= etm_reg
->jtag_info
->tap
;
573 fields
[0].num_bits
= 32;
575 fields
[0].out_value
= tmp1
;
576 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
577 fields
[0].in_value
= NULL
;
579 fields
[1].tap
= etm_reg
->jtag_info
->tap
;
580 fields
[1].num_bits
= 7;
582 fields
[1].out_value
= &tmp2
;
583 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
584 fields
[1].in_value
= NULL
;
586 fields
[2].tap
= etm_reg
->jtag_info
->tap
;
587 fields
[2].num_bits
= 1;
589 fields
[2].out_value
= &tmp3
;
590 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
591 fields
[2].in_value
= NULL
;
593 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
599 /* ETM trace analysis functionality
602 extern etm_capture_driver_t etm_dummy_capture_driver
;
603 #if BUILD_OOCD_TRACE == 1
604 extern etm_capture_driver_t oocd_trace_capture_driver
;
607 static etm_capture_driver_t
*etm_capture_drivers
[] =
610 &etm_dummy_capture_driver
,
611 #if BUILD_OOCD_TRACE == 1
612 &oocd_trace_capture_driver
,
617 static int etm_read_instruction(etm_context_t
*ctx
, arm_instruction_t
*instruction
)
626 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
628 /* search for the section the current instruction belongs to */
629 for (i
= 0; i
< ctx
->image
->num_sections
; i
++)
631 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
632 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
> ctx
->current_pc
))
641 /* current instruction couldn't be found in the image */
642 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
645 if (ctx
->core_state
== ARMV4_5_STATE_ARM
)
648 if ((retval
= image_read_section(ctx
->image
, section
,
649 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
650 4, buf
, &size_read
)) != ERROR_OK
)
652 LOG_ERROR("error while reading instruction: %i", retval
);
653 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
655 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
656 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
658 else if (ctx
->core_state
== ARMV4_5_STATE_THUMB
)
661 if ((retval
= image_read_section(ctx
->image
, section
,
662 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
663 2, buf
, &size_read
)) != ERROR_OK
)
665 LOG_ERROR("error while reading instruction: %i", retval
);
666 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
668 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
669 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
671 else if (ctx
->core_state
== ARMV4_5_STATE_JAZELLE
)
673 LOG_ERROR("BUG: tracing of jazelle code not supported");
678 LOG_ERROR("BUG: unknown core state encountered");
685 static int etmv1_next_packet(etm_context_t
*ctx
, uint8_t *packet
, int apo
)
687 while (ctx
->data_index
< ctx
->trace_depth
)
689 /* if the caller specified an address packet offset, skip until the
690 * we reach the n-th cycle marked with tracesync */
693 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
704 /* no tracedata output during a TD cycle
705 * or in a trigger cycle */
706 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
707 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
))
714 if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
)
716 if (ctx
->data_half
== 0)
718 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
723 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
728 else if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
730 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
735 /* on a 4-bit port, a packet will be output during two consecutive cycles */
736 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
739 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
740 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
741 ctx
->data_index
+= 2;
750 static int etmv1_branch_address(etm_context_t
*ctx
)
758 /* quit analysis if less than two cycles are left in the trace
759 * because we can't extract the APO */
760 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
763 /* a BE could be output during an APO cycle, skip the current
764 * and continue with the new one */
765 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
767 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
770 /* address packet offset encoded in the next two cycles' pipestat bits */
771 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
772 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
774 /* count number of tracesync cycles between current pipe_index and data_index
775 * i.e. the number of tracesyncs that data_index already passed by
776 * to subtract them from the APO */
777 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++)
779 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
783 /* extract up to four 7-bit packets */
785 if ((retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0)) != 0)
787 ctx
->last_branch
&= ~(0x7f << shift
);
788 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
790 } while ((packet
& 0x80) && (shift
< 28));
792 /* one last packet holding 4 bits of the address, plus the branch reason code */
793 if ((shift
== 28) && (packet
& 0x80))
795 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
797 ctx
->last_branch
&= 0x0fffffff;
798 ctx
->last_branch
|= (packet
& 0x0f) << 28;
799 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
804 ctx
->last_branch_reason
= 0;
812 /* if a full address was output, we might have branched into Jazelle state */
813 if ((shift
== 32) && (packet
& 0x80))
815 ctx
->core_state
= ARMV4_5_STATE_JAZELLE
;
819 /* if we didn't branch into Jazelle state, the current processor state is
820 * encoded in bit 0 of the branch target address */
821 if (ctx
->last_branch
& 0x1)
823 ctx
->core_state
= ARMV4_5_STATE_THUMB
;
824 ctx
->last_branch
&= ~0x1;
828 ctx
->core_state
= ARMV4_5_STATE_ARM
;
829 ctx
->last_branch
&= ~0x3;
836 static int etmv1_data(etm_context_t
*ctx
, int size
, uint32_t *data
)
842 for (j
= 0; j
< size
; j
++)
844 if ((retval
= etmv1_next_packet(ctx
, &buf
[j
], 0)) != 0)
850 LOG_ERROR("TODO: add support for 64-bit values");
854 *data
= target_buffer_get_u32(ctx
->target
, buf
);
856 *data
= target_buffer_get_u16(ctx
->target
, buf
);
865 static int etmv1_analyze_trace(etm_context_t
*ctx
, struct command_context_s
*cmd_ctx
)
868 arm_instruction_t instruction
;
870 /* read the trace data if it wasn't read already */
871 if (ctx
->trace_depth
== 0)
872 ctx
->capture_driver
->read_trace(ctx
);
874 /* start at the beginning of the captured trace */
879 /* neither the PC nor the data pointer are valid */
883 while (ctx
->pipe_index
< ctx
->trace_depth
)
885 uint8_t pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
886 uint32_t next_pc
= ctx
->current_pc
;
887 uint32_t old_data_index
= ctx
->data_index
;
888 uint32_t old_data_half
= ctx
->data_half
;
889 uint32_t old_index
= ctx
->pipe_index
;
890 uint32_t last_instruction
= ctx
->last_instruction
;
892 int current_pc_ok
= ctx
->pc_ok
;
894 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
896 command_print(cmd_ctx
, "--- trigger ---");
899 /* instructions execute in IE/D or BE/D cycles */
900 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
901 ctx
->last_instruction
= ctx
->pipe_index
;
903 /* if we don't have a valid pc skip until we reach an indirect branch */
904 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
))
910 /* any indirect branch could have interrupted instruction flow
911 * - the branch reason code could indicate a trace discontinuity
912 * - a branch to the exception vectors indicates an exception
914 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
))
916 /* backup current data index, to be able to consume the branch address
917 * before examining data address and values
919 old_data_index
= ctx
->data_index
;
920 old_data_half
= ctx
->data_half
;
922 ctx
->last_instruction
= ctx
->pipe_index
;
924 if ((retval
= etmv1_branch_address(ctx
)) != 0)
926 /* negative return value from etmv1_branch_address means we ran out of packets,
927 * quit analysing the trace */
931 /* a positive return values means the current branch was abandoned,
932 * and a new branch was encountered in cycle ctx->pipe_index + retval;
934 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
935 ctx
->pipe_index
+= retval
;
939 /* skip over APO cycles */
940 ctx
->pipe_index
+= 2;
942 switch (ctx
->last_branch_reason
)
944 case 0x0: /* normal PC change */
945 next_pc
= ctx
->last_branch
;
947 case 0x1: /* tracing enabled */
948 command_print(cmd_ctx
, "--- tracing enabled at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
949 ctx
->current_pc
= ctx
->last_branch
;
953 case 0x2: /* trace restarted after FIFO overflow */
954 command_print(cmd_ctx
, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
955 ctx
->current_pc
= ctx
->last_branch
;
959 case 0x3: /* exit from debug state */
960 command_print(cmd_ctx
, "--- exit from debug state at 0x%8.8" PRIx32
" ---", ctx
->last_branch
);
961 ctx
->current_pc
= ctx
->last_branch
;
965 case 0x4: /* periodic synchronization point */
966 next_pc
= ctx
->last_branch
;
967 /* if we had no valid PC prior to this synchronization point,
968 * we have to move on with the next trace cycle
972 command_print(cmd_ctx
, "--- periodic synchronization point at 0x%8.8" PRIx32
" ---", next_pc
);
973 ctx
->current_pc
= next_pc
;
978 default: /* reserved */
979 LOG_ERROR("BUG: branch reason code 0x%" PRIx32
" is reserved", ctx
->last_branch_reason
);
984 /* if we got here the branch was a normal PC change
985 * (or a periodic synchronization point, which means the same for that matter)
986 * if we didn't accquire a complete PC continue with the next cycle
991 /* indirect branch to the exception vector means an exception occured */
992 if ((ctx
->last_branch
<= 0x20)
993 || ((ctx
->last_branch
>= 0xffff0000) && (ctx
->last_branch
<= 0xffff0020)))
995 if ((ctx
->last_branch
& 0xff) == 0x10)
997 command_print(cmd_ctx
, "data abort");
1001 command_print(cmd_ctx
, "exception vector 0x%2.2" PRIx32
"", ctx
->last_branch
);
1002 ctx
->current_pc
= ctx
->last_branch
;
1009 /* an instruction was executed (or not, depending on the condition flags)
1010 * retrieve it from the image for displaying */
1011 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
1012 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
1013 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4))))
1015 if ((retval
= etm_read_instruction(ctx
, &instruction
)) != ERROR_OK
)
1017 /* can't continue tracing with no image available */
1018 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
1022 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
1024 /* TODO: handle incomplete images
1025 * for now we just quit the analsysis*/
1030 cycles
= old_index
- last_instruction
;
1033 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
))
1035 uint32_t new_data_index
= ctx
->data_index
;
1036 uint32_t new_data_half
= ctx
->data_half
;
1038 /* in case of a branch with data, the branch target address was consumed before
1039 * we temporarily go back to the saved data index */
1040 if (pipestat
== STAT_BD
)
1042 ctx
->data_index
= old_data_index
;
1043 ctx
->data_half
= old_data_half
;
1046 if (ctx
->tracemode
& ETMV1_TRACE_ADDR
)
1052 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
1053 return ERROR_ETM_ANALYSIS_FAILED
;
1054 ctx
->last_ptr
&= ~(0x7f << shift
);
1055 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
1057 } while ((packet
& 0x80) && (shift
< 32));
1064 command_print(cmd_ctx
, "address: 0x%8.8" PRIx32
"", ctx
->last_ptr
);
1068 if (ctx
->tracemode
& ETMV1_TRACE_DATA
)
1070 if ((instruction
.type
== ARM_LDM
) || (instruction
.type
== ARM_STM
))
1073 for (i
= 0; i
< 16; i
++)
1075 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
1078 if (etmv1_data(ctx
, 4, &data
) != 0)
1079 return ERROR_ETM_ANALYSIS_FAILED
;
1080 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1084 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_STRH
))
1087 if (etmv1_data(ctx
, arm_access_size(&instruction
), &data
) != 0)
1088 return ERROR_ETM_ANALYSIS_FAILED
;
1089 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1093 /* restore data index after consuming BD address and data */
1094 if (pipestat
== STAT_BD
)
1096 ctx
->data_index
= new_data_index
;
1097 ctx
->data_half
= new_data_half
;
1102 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
1104 if (((instruction
.type
== ARM_B
) ||
1105 (instruction
.type
== ARM_BL
) ||
1106 (instruction
.type
== ARM_BLX
)) &&
1107 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff))
1109 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
1113 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
1116 else if (pipestat
== STAT_IN
)
1118 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
1121 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
))
1123 char cycles_text
[32] = "";
1125 /* if the trace was captured with cycle accurate tracing enabled,
1126 * output the number of cycles since the last executed instruction
1128 if (ctx
->tracemode
& ETMV1_CYCLE_ACCURATE
)
1130 snprintf(cycles_text
, 32, " (%i %s)",
1132 (cycles
== 1) ? "cycle" : "cycles");
1135 command_print(cmd_ctx
, "%s%s%s",
1137 (pipestat
== STAT_IN
) ? " (not executed)" : "",
1140 ctx
->current_pc
= next_pc
;
1142 /* packets for an instruction don't start on or before the preceding
1143 * functional pipestat (i.e. other than WT or TD)
1145 if (ctx
->data_index
<= ctx
->pipe_index
)
1147 ctx
->data_index
= ctx
->pipe_index
+ 1;
1152 ctx
->pipe_index
+= 1;
1158 static int handle_etm_tracemode_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1161 armv4_5_common_t
*armv4_5
;
1162 arm7_9_common_t
*arm7_9
;
1163 etmv1_tracemode_t tracemode
;
1165 target
= get_current_target(cmd_ctx
);
1167 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1169 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1173 if (!arm7_9
->etm_ctx
)
1175 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1179 tracemode
= arm7_9
->etm_ctx
->tracemode
;
1183 /* what parts of data access are traced? */
1184 if (strcmp(args
[0], "none") == 0)
1186 tracemode
= ETMV1_TRACE_NONE
;
1188 else if (strcmp(args
[0], "data") == 0)
1190 tracemode
= ETMV1_TRACE_DATA
;
1192 else if (strcmp(args
[0], "address") == 0)
1194 tracemode
= ETMV1_TRACE_ADDR
;
1196 else if (strcmp(args
[0], "all") == 0)
1198 tracemode
= ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
;
1202 command_print(cmd_ctx
, "invalid option '%s'", args
[0]);
1207 COMMAND_PARSE_NUMBER(u8
, args
[1], context_id
);
1211 tracemode
|= ETMV1_CONTEXTID_NONE
;
1214 tracemode
|= ETMV1_CONTEXTID_8
;
1217 tracemode
|= ETMV1_CONTEXTID_16
;
1220 tracemode
|= ETMV1_CONTEXTID_32
;
1223 command_print(cmd_ctx
, "invalid option '%s'", args
[1]);
1227 if (strcmp(args
[2], "enable") == 0)
1229 tracemode
|= ETMV1_CYCLE_ACCURATE
;
1231 else if (strcmp(args
[2], "disable") == 0)
1237 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1241 if (strcmp(args
[3], "enable") == 0)
1243 tracemode
|= ETMV1_BRANCH_OUTPUT
;
1245 else if (strcmp(args
[3], "disable") == 0)
1251 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1256 * - CPRT tracing (coprocessor register transfers)
1257 * - debug request (causes debug entry on trigger)
1258 * - stall on FIFOFULL (preventing tracedata lossage)
1263 command_print(cmd_ctx
, "usage: configure trace mode <none | data | address | all> <context id bits> <cycle accurate> <branch output>");
1267 command_print(cmd_ctx
, "current tracemode configuration:");
1269 switch (tracemode
& ETMV1_TRACE_MASK
)
1271 case ETMV1_TRACE_NONE
:
1272 command_print(cmd_ctx
, "data tracing: none");
1274 case ETMV1_TRACE_DATA
:
1275 command_print(cmd_ctx
, "data tracing: data only");
1277 case ETMV1_TRACE_ADDR
:
1278 command_print(cmd_ctx
, "data tracing: address only");
1280 case ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
:
1281 command_print(cmd_ctx
, "data tracing: address and data");
1285 switch (tracemode
& ETMV1_CONTEXTID_MASK
)
1287 case ETMV1_CONTEXTID_NONE
:
1288 command_print(cmd_ctx
, "contextid tracing: none");
1290 case ETMV1_CONTEXTID_8
:
1291 command_print(cmd_ctx
, "contextid tracing: 8 bit");
1293 case ETMV1_CONTEXTID_16
:
1294 command_print(cmd_ctx
, "contextid tracing: 16 bit");
1296 case ETMV1_CONTEXTID_32
:
1297 command_print(cmd_ctx
, "contextid tracing: 32 bit");
1301 if (tracemode
& ETMV1_CYCLE_ACCURATE
)
1303 command_print(cmd_ctx
, "cycle-accurate tracing enabled");
1307 command_print(cmd_ctx
, "cycle-accurate tracing disabled");
1310 if (tracemode
& ETMV1_BRANCH_OUTPUT
)
1312 command_print(cmd_ctx
, "full branch address output enabled");
1316 command_print(cmd_ctx
, "full branch address output disabled");
1319 /* only update ETM_CTRL register if tracemode changed */
1320 if (arm7_9
->etm_ctx
->tracemode
!= tracemode
)
1322 reg_t
*etm_ctrl_reg
;
1324 etm_ctrl_reg
= etm_reg_lookup(arm7_9
->etm_ctx
, ETM_CTRL
);
1328 etm_get_reg(etm_ctrl_reg
);
1330 buf_set_u32(etm_ctrl_reg
->value
, 2, 2, tracemode
& ETMV1_TRACE_MASK
);
1331 buf_set_u32(etm_ctrl_reg
->value
, 14, 2, (tracemode
& ETMV1_CONTEXTID_MASK
) >> 4);
1332 buf_set_u32(etm_ctrl_reg
->value
, 12, 1, (tracemode
& ETMV1_CYCLE_ACCURATE
) >> 8);
1333 buf_set_u32(etm_ctrl_reg
->value
, 8, 1, (tracemode
& ETMV1_BRANCH_OUTPUT
) >> 9);
1334 etm_store_reg(etm_ctrl_reg
);
1336 arm7_9
->etm_ctx
->tracemode
= tracemode
;
1338 /* invalidate old trace data */
1339 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1340 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1342 free(arm7_9
->etm_ctx
->trace_data
);
1343 arm7_9
->etm_ctx
->trace_data
= NULL
;
1345 arm7_9
->etm_ctx
->trace_depth
= 0;
1351 static int handle_etm_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1354 armv4_5_common_t
*armv4_5
;
1355 arm7_9_common_t
*arm7_9
;
1356 etm_portmode_t portmode
= 0x0;
1357 etm_context_t
*etm_ctx
= malloc(sizeof(etm_context_t
));
1363 return ERROR_COMMAND_SYNTAX_ERROR
;
1366 target
= get_target(args
[0]);
1369 LOG_ERROR("target '%s' not defined", args
[0]);
1374 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1376 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1382 COMMAND_PARSE_NUMBER(u8
, args
[1], port_width
);
1386 portmode
|= ETM_PORT_4BIT
;
1389 portmode
|= ETM_PORT_8BIT
;
1392 portmode
|= ETM_PORT_16BIT
;
1395 command_print(cmd_ctx
, "unsupported ETM port width '%s', must be 4, 8 or 16", args
[1]);
1400 if (strcmp("normal", args
[2]) == 0)
1402 portmode
|= ETM_PORT_NORMAL
;
1404 else if (strcmp("multiplexed", args
[2]) == 0)
1406 portmode
|= ETM_PORT_MUXED
;
1408 else if (strcmp("demultiplexed", args
[2]) == 0)
1410 portmode
|= ETM_PORT_DEMUXED
;
1414 command_print(cmd_ctx
, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args
[2]);
1419 if (strcmp("half", args
[3]) == 0)
1421 portmode
|= ETM_PORT_HALF_CLOCK
;
1423 else if (strcmp("full", args
[3]) == 0)
1425 portmode
|= ETM_PORT_FULL_CLOCK
;
1429 command_print(cmd_ctx
, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args
[3]);
1434 for (i
= 0; etm_capture_drivers
[i
]; i
++)
1436 if (strcmp(args
[4], etm_capture_drivers
[i
]->name
) == 0)
1439 if ((retval
= etm_capture_drivers
[i
]->register_commands(cmd_ctx
)) != ERROR_OK
)
1445 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1451 if (!etm_capture_drivers
[i
])
1453 /* no supported capture driver found, don't register an ETM */
1455 LOG_ERROR("trace capture driver '%s' not found", args
[4]);
1459 etm_ctx
->target
= target
;
1460 etm_ctx
->trigger_percent
= 50;
1461 etm_ctx
->trace_data
= NULL
;
1462 etm_ctx
->trace_depth
= 0;
1463 etm_ctx
->portmode
= portmode
;
1464 etm_ctx
->tracemode
= 0x0;
1465 etm_ctx
->core_state
= ARMV4_5_STATE_ARM
;
1466 etm_ctx
->image
= NULL
;
1467 etm_ctx
->pipe_index
= 0;
1468 etm_ctx
->data_index
= 0;
1469 etm_ctx
->current_pc
= 0x0;
1471 etm_ctx
->last_branch
= 0x0;
1472 etm_ctx
->last_branch_reason
= 0x0;
1473 etm_ctx
->last_ptr
= 0x0;
1474 etm_ctx
->ptr_ok
= 0x0;
1475 etm_ctx
->last_instruction
= 0;
1477 arm7_9
->etm_ctx
= etm_ctx
;
1479 return etm_register_user_commands(cmd_ctx
);
1482 static int handle_etm_info_command(struct command_context_s
*cmd_ctx
,
1483 char *cmd
, char **args
, int argc
)
1486 armv4_5_common_t
*armv4_5
;
1487 arm7_9_common_t
*arm7_9
;
1489 reg_t
*etm_sys_config_reg
;
1493 target
= get_current_target(cmd_ctx
);
1495 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1497 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1501 etm
= arm7_9
->etm_ctx
;
1504 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1508 command_print(cmd_ctx
, "ETM v%d.%d",
1509 etm
->bcd_vers
>> 4, etm
->bcd_vers
& 0xf);
1510 command_print(cmd_ctx
, "pairs of address comparators: %i",
1511 (int) (etm
->config
>> 0) & 0x0f);
1512 command_print(cmd_ctx
, "data comparators: %i",
1513 (int) (etm
->config
>> 4) & 0x0f);
1514 command_print(cmd_ctx
, "memory map decoders: %i",
1515 (int) (etm
->config
>> 8) & 0x1f);
1516 command_print(cmd_ctx
, "number of counters: %i",
1517 (int) (etm
->config
>> 13) & 0x07);
1518 command_print(cmd_ctx
, "sequencer %spresent",
1519 (int) (etm
->config
& (1 << 16)) ? "" : "not ");
1520 command_print(cmd_ctx
, "number of ext. inputs: %i",
1521 (int) (etm
->config
>> 17) & 0x07);
1522 command_print(cmd_ctx
, "number of ext. outputs: %i",
1523 (int) (etm
->config
>> 20) & 0x07);
1524 command_print(cmd_ctx
, "FIFO full %spresent",
1525 (int) (etm
->config
& (1 << 23)) ? "" : "not ");
1526 if (etm
->bcd_vers
< 0x20)
1527 command_print(cmd_ctx
, "protocol version: %i",
1528 (int) (etm
->config
>> 28) & 0x07);
1530 command_print(cmd_ctx
, "trace start/stop %spresent",
1531 (etm
->config
& (1 << 26)) ? "" : "not ");
1532 command_print(cmd_ctx
, "number of context comparators: %i",
1533 (int) (etm
->config
>> 24) & 0x03);
1536 /* SYS_CONFIG isn't present before ETMv1.2 */
1537 etm_sys_config_reg
= etm_reg_lookup(etm
, ETM_SYS_CONFIG
);
1538 if (!etm_sys_config_reg
)
1541 etm_get_reg(etm_sys_config_reg
);
1543 switch (buf_get_u32(etm_sys_config_reg
->value
, 0, 3))
1555 LOG_ERROR("Illegal max_port_size");
1558 command_print(cmd_ctx
, "max. port size: %i", max_port_size
);
1560 command_print(cmd_ctx
, "half-rate clocking %ssupported",
1561 (buf_get_u32(etm_sys_config_reg
->value
, 3, 1) == 1) ? "" : "not ");
1562 command_print(cmd_ctx
, "full-rate clocking %ssupported",
1563 (buf_get_u32(etm_sys_config_reg
->value
, 4, 1) == 1) ? "" : "not ");
1564 command_print(cmd_ctx
, "normal trace format %ssupported",
1565 (buf_get_u32(etm_sys_config_reg
->value
, 5, 1) == 1) ? "" : "not ");
1566 command_print(cmd_ctx
, "multiplex trace format %ssupported",
1567 (buf_get_u32(etm_sys_config_reg
->value
, 6, 1) == 1) ? "" : "not ");
1568 command_print(cmd_ctx
, "demultiplex trace format %ssupported",
1569 (buf_get_u32(etm_sys_config_reg
->value
, 7, 1) == 1) ? "" : "not ");
1570 command_print(cmd_ctx
, "FIFO full %ssupported",
1571 (buf_get_u32(etm_sys_config_reg
->value
, 8, 1) == 1) ? "" : "not ");
1576 static int handle_etm_status_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1579 armv4_5_common_t
*armv4_5
;
1580 arm7_9_common_t
*arm7_9
;
1582 trace_status_t trace_status
;
1584 target
= get_current_target(cmd_ctx
);
1586 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1588 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1592 if (!arm7_9
->etm_ctx
)
1594 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1597 etm
= arm7_9
->etm_ctx
;
1600 if (etm
->bcd_vers
>= 0x11) {
1603 reg
= etm_reg_lookup(etm
, ETM_STATUS
);
1606 if (etm_get_reg(reg
) == ERROR_OK
) {
1607 unsigned s
= buf_get_u32(reg
->value
, 0, reg
->size
);
1609 command_print(cmd_ctx
, "etm: %s%s%s%s",
1610 /* bit(1) == progbit */
1611 (etm
->bcd_vers
>= 0x12)
1613 ? "disabled" : "enabled")
1615 ((s
& (1 << 3)) && etm
->bcd_vers
>= 0x31)
1616 ? " triggered" : "",
1617 ((s
& (1 << 2)) && etm
->bcd_vers
>= 0x12)
1618 ? " start/stop" : "",
1619 ((s
& (1 << 0)) && etm
->bcd_vers
>= 0x11)
1620 ? " untraced-overflow" : "");
1621 } /* else ignore and try showing trace port status */
1624 /* Trace Port Driver status */
1625 trace_status
= etm
->capture_driver
->status(etm
);
1626 if (trace_status
== TRACE_IDLE
)
1628 command_print(cmd_ctx
, "%s: idle", etm
->capture_driver
->name
);
1632 static char *completed
= " completed";
1633 static char *running
= " is running";
1634 static char *overflowed
= ", overflowed";
1635 static char *triggered
= ", triggered";
1637 command_print(cmd_ctx
, "%s: trace collection%s%s%s",
1638 etm
->capture_driver
->name
,
1639 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1640 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1641 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1643 if (etm
->trace_depth
> 0)
1645 command_print(cmd_ctx
, "%i frames of trace data read",
1646 (int)(etm
->trace_depth
));
1653 static int handle_etm_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1656 armv4_5_common_t
*armv4_5
;
1657 arm7_9_common_t
*arm7_9
;
1658 etm_context_t
*etm_ctx
;
1662 command_print(cmd_ctx
, "usage: etm image <file> [base address] [type]");
1666 target
= get_current_target(cmd_ctx
);
1668 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1670 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1674 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1676 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1682 image_close(etm_ctx
->image
);
1683 free(etm_ctx
->image
);
1684 command_print(cmd_ctx
, "previously loaded image found and closed");
1687 etm_ctx
->image
= malloc(sizeof(image_t
));
1688 etm_ctx
->image
->base_address_set
= 0;
1689 etm_ctx
->image
->start_address_set
= 0;
1691 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1694 etm_ctx
->image
->base_address_set
= 1;
1695 COMMAND_PARSE_NUMBER(int, args
[1], etm_ctx
->image
->base_address
);
1699 etm_ctx
->image
->base_address_set
= 0;
1702 if (image_open(etm_ctx
->image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
1704 free(etm_ctx
->image
);
1705 etm_ctx
->image
= NULL
;
1712 static int handle_etm_dump_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1716 armv4_5_common_t
*armv4_5
;
1717 arm7_9_common_t
*arm7_9
;
1718 etm_context_t
*etm_ctx
;
1723 command_print(cmd_ctx
, "usage: etm dump <file>");
1727 target
= get_current_target(cmd_ctx
);
1729 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1731 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1735 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1737 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1741 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
)
1743 command_print(cmd_ctx
, "trace capture wasn't enabled, no trace data captured");
1747 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1749 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1750 command_print(cmd_ctx
, "trace capture not completed");
1754 /* read the trace data if it wasn't read already */
1755 if (etm_ctx
->trace_depth
== 0)
1756 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1758 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1763 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1764 fileio_write_u32(&file
, etm_ctx
->portmode
);
1765 fileio_write_u32(&file
, etm_ctx
->tracemode
);
1766 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1768 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1770 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1771 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1772 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1775 fileio_close(&file
);
1780 static int handle_etm_load_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1784 armv4_5_common_t
*armv4_5
;
1785 arm7_9_common_t
*arm7_9
;
1786 etm_context_t
*etm_ctx
;
1791 command_print(cmd_ctx
, "usage: etm load <file>");
1795 target
= get_current_target(cmd_ctx
);
1797 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1799 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1803 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1805 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1809 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1811 command_print(cmd_ctx
, "trace capture running, stop first");
1815 if (fileio_open(&file
, args
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1822 command_print(cmd_ctx
, "size isn't a multiple of 4, no valid trace data");
1823 fileio_close(&file
);
1827 if (etm_ctx
->trace_depth
> 0)
1829 free(etm_ctx
->trace_data
);
1830 etm_ctx
->trace_data
= NULL
;
1835 fileio_read_u32(&file
, &tmp
); etm_ctx
->capture_status
= tmp
;
1836 fileio_read_u32(&file
, &tmp
); etm_ctx
->portmode
= tmp
;
1837 fileio_read_u32(&file
, &tmp
); etm_ctx
->tracemode
= tmp
;
1838 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1840 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
1841 if (etm_ctx
->trace_data
== NULL
)
1843 command_print(cmd_ctx
, "not enough memory to perform operation");
1844 fileio_close(&file
);
1848 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1850 uint32_t pipestat
, packet
, flags
;
1851 fileio_read_u32(&file
, &pipestat
);
1852 fileio_read_u32(&file
, &packet
);
1853 fileio_read_u32(&file
, &flags
);
1854 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1855 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1856 etm_ctx
->trace_data
[i
].flags
= flags
;
1859 fileio_close(&file
);
1864 static int handle_etm_trigger_percent_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1867 armv4_5_common_t
*armv4_5
;
1868 arm7_9_common_t
*arm7_9
;
1869 etm_context_t
*etm_ctx
;
1871 target
= get_current_target(cmd_ctx
);
1873 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1875 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1879 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1881 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1888 COMMAND_PARSE_NUMBER(u32
, args
[0], new_value
);
1890 if ((new_value
< 2) || (new_value
> 100))
1892 command_print(cmd_ctx
, "valid settings are 2%% to 100%%");
1896 etm_ctx
->trigger_percent
= new_value
;
1900 command_print(cmd_ctx
, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx
->trigger_percent
)));
1905 static int handle_etm_start_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1908 armv4_5_common_t
*armv4_5
;
1909 arm7_9_common_t
*arm7_9
;
1910 etm_context_t
*etm_ctx
;
1911 reg_t
*etm_ctrl_reg
;
1913 target
= get_current_target(cmd_ctx
);
1915 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1917 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1921 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1923 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1927 /* invalidate old tracing data */
1928 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1929 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1931 free(arm7_9
->etm_ctx
->trace_data
);
1932 arm7_9
->etm_ctx
->trace_data
= NULL
;
1934 arm7_9
->etm_ctx
->trace_depth
= 0;
1936 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1940 etm_get_reg(etm_ctrl_reg
);
1942 /* Clear programming bit (10), set port selection bit (11) */
1943 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1945 etm_store_reg(etm_ctrl_reg
);
1946 jtag_execute_queue();
1948 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1953 static int handle_etm_stop_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1956 armv4_5_common_t
*armv4_5
;
1957 arm7_9_common_t
*arm7_9
;
1958 etm_context_t
*etm_ctx
;
1959 reg_t
*etm_ctrl_reg
;
1961 target
= get_current_target(cmd_ctx
);
1963 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1965 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1969 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1971 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1975 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1979 etm_get_reg(etm_ctrl_reg
);
1981 /* Set programming bit (10), clear port selection bit (11) */
1982 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
1984 etm_store_reg(etm_ctrl_reg
);
1985 jtag_execute_queue();
1987 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
1992 static int handle_etm_analyze_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1995 armv4_5_common_t
*armv4_5
;
1996 arm7_9_common_t
*arm7_9
;
1997 etm_context_t
*etm_ctx
;
2000 target
= get_current_target(cmd_ctx
);
2002 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2004 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2008 if (!(etm_ctx
= arm7_9
->etm_ctx
))
2010 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
2014 if ((retval
= etmv1_analyze_trace(etm_ctx
, cmd_ctx
)) != ERROR_OK
)
2018 case ERROR_ETM_ANALYSIS_FAILED
:
2019 command_print(cmd_ctx
, "further analysis failed (corrupted trace data or just end of data");
2021 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE
:
2022 command_print(cmd_ctx
, "no instruction for current address available, analysis aborted");
2024 case ERROR_TRACE_IMAGE_UNAVAILABLE
:
2025 command_print(cmd_ctx
, "no image available for trace analysis");
2028 command_print(cmd_ctx
, "unknown error: %i", retval
);
2035 int etm_register_commands(struct command_context_s
*cmd_ctx
)
2037 etm_cmd
= register_command(cmd_ctx
, NULL
, "etm", NULL
, COMMAND_ANY
, "Embedded Trace Macrocell");
2039 register_command(cmd_ctx
, etm_cmd
, "config", handle_etm_config_command
,
2040 COMMAND_CONFIG
, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2045 static int etm_register_user_commands(struct command_context_s
*cmd_ctx
)
2047 register_command(cmd_ctx
, etm_cmd
, "tracemode", handle_etm_tracemode_command
,
2048 COMMAND_EXEC
, "configure/display trace mode: "
2049 "<none | data | address | all> "
2050 "<context_id_bits> <cycle_accurate> <branch_output>");
2052 register_command(cmd_ctx
, etm_cmd
, "info", handle_etm_info_command
,
2053 COMMAND_EXEC
, "display info about the current target's ETM");
2055 register_command(cmd_ctx
, etm_cmd
, "trigger_percent", handle_etm_trigger_percent_command
,
2056 COMMAND_EXEC
, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2057 register_command(cmd_ctx
, etm_cmd
, "status", handle_etm_status_command
,
2058 COMMAND_EXEC
, "display current target's ETM status");
2059 register_command(cmd_ctx
, etm_cmd
, "start", handle_etm_start_command
,
2060 COMMAND_EXEC
, "start ETM trace collection");
2061 register_command(cmd_ctx
, etm_cmd
, "stop", handle_etm_stop_command
,
2062 COMMAND_EXEC
, "stop ETM trace collection");
2064 register_command(cmd_ctx
, etm_cmd
, "analyze", handle_etm_analyze_command
,
2065 COMMAND_EXEC
, "anaylze collected ETM trace");
2067 register_command(cmd_ctx
, etm_cmd
, "image", handle_etm_image_command
,
2068 COMMAND_EXEC
, "load image from <file> [base address]");
2070 register_command(cmd_ctx
, etm_cmd
, "dump", handle_etm_dump_command
,
2071 COMMAND_EXEC
, "dump captured trace data <file>");
2072 register_command(cmd_ctx
, etm_cmd
, "load", handle_etm_load_command
,
2073 COMMAND_EXEC
, "load trace data for analysis <file>");
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)