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Zach Welch <zw@superlucidity.net> fix -Werror warnings
[openocd.git] / src / target / etm.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include <string.h>
25
26 #include "etm.h"
27 #include "etb.h"
28
29 #include "armv4_5.h"
30 #include "arm7_9_common.h"
31 #include "arm_disassembler.h"
32 #include "arm_simulator.h"
33
34 #include "log.h"
35 #include "arm_jtag.h"
36 #include "types.h"
37 #include "binarybuffer.h"
38 #include "target.h"
39 #include "register.h"
40 #include "jtag.h"
41 #include "fileio.h"
42
43 #include <stdlib.h>
44
45 /* ETM register access functionality
46 *
47 */
48
49 bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
50 {
51 {"R", 1},
52 {"W", 1},
53 {"reserved", 26},
54 {"version", 4}
55 };
56
57 int etm_reg_arch_info[] =
58 {
59 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
60 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
61 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
62 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
63 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
64 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
65 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
66 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
67 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
68 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
69 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
70 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
71 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
72 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
73 };
74
75 int etm_reg_arch_size_info[] =
76 {
77 32, 32, 17, 8, 3, 9, 32, 16,
78 17, 26, 25, 8, 17, 32, 32, 17,
79 32, 32, 32, 32, 32, 32, 32, 32,
80 32, 32, 32, 32, 32, 32, 32, 32,
81 7, 7, 7, 7, 7, 7, 7, 7,
82 7, 7, 7, 7, 7, 7, 7, 7,
83 32, 32, 32, 32, 32, 32, 32, 32,
84 32, 32, 32, 32, 32, 32, 32, 32,
85 32, 32, 32, 32, 32, 32, 32, 32,
86 32, 32, 32, 32, 32, 32, 32, 32,
87 16, 16, 16, 16, 18, 18, 18, 18,
88 17, 17, 17, 17, 16, 16, 16, 16,
89 17, 17, 17, 17, 17, 17, 2,
90 17, 17, 17, 17, 32, 32, 32, 32
91 };
92
93 char* etm_reg_list[] =
94 {
95 "ETM_CTRL",
96 "ETM_CONFIG",
97 "ETM_TRIG_EVENT",
98 "ETM_MMD_CTRL",
99 "ETM_STATUS",
100 "ETM_SYS_CONFIG",
101 "ETM_TRACE_RESOURCE_CTRL",
102 "ETM_TRACE_EN_CTRL2",
103 "ETM_TRACE_EN_EVENT",
104 "ETM_TRACE_EN_CTRL1",
105 "ETM_FIFOFULL_REGION",
106 "ETM_FIFOFULL_LEVEL",
107 "ETM_VIEWDATA_EVENT",
108 "ETM_VIEWDATA_CTRL1",
109 "ETM_VIEWDATA_CTRL2",
110 "ETM_VIEWDATA_CTRL3",
111 "ETM_ADDR_COMPARATOR_VALUE1",
112 "ETM_ADDR_COMPARATOR_VALUE2",
113 "ETM_ADDR_COMPARATOR_VALUE3",
114 "ETM_ADDR_COMPARATOR_VALUE4",
115 "ETM_ADDR_COMPARATOR_VALUE5",
116 "ETM_ADDR_COMPARATOR_VALUE6",
117 "ETM_ADDR_COMPARATOR_VALUE7",
118 "ETM_ADDR_COMPARATOR_VALUE8",
119 "ETM_ADDR_COMPARATOR_VALUE9",
120 "ETM_ADDR_COMPARATOR_VALUE10",
121 "ETM_ADDR_COMPARATOR_VALUE11",
122 "ETM_ADDR_COMPARATOR_VALUE12",
123 "ETM_ADDR_COMPARATOR_VALUE13",
124 "ETM_ADDR_COMPARATOR_VALUE14",
125 "ETM_ADDR_COMPARATOR_VALUE15",
126 "ETM_ADDR_COMPARATOR_VALUE16",
127 "ETM_ADDR_ACCESS_TYPE1",
128 "ETM_ADDR_ACCESS_TYPE2",
129 "ETM_ADDR_ACCESS_TYPE3",
130 "ETM_ADDR_ACCESS_TYPE4",
131 "ETM_ADDR_ACCESS_TYPE5",
132 "ETM_ADDR_ACCESS_TYPE6",
133 "ETM_ADDR_ACCESS_TYPE7",
134 "ETM_ADDR_ACCESS_TYPE8",
135 "ETM_ADDR_ACCESS_TYPE9",
136 "ETM_ADDR_ACCESS_TYPE10",
137 "ETM_ADDR_ACCESS_TYPE11",
138 "ETM_ADDR_ACCESS_TYPE12",
139 "ETM_ADDR_ACCESS_TYPE13",
140 "ETM_ADDR_ACCESS_TYPE14",
141 "ETM_ADDR_ACCESS_TYPE15",
142 "ETM_ADDR_ACCESS_TYPE16",
143 "ETM_DATA_COMPARATOR_VALUE1",
144 "ETM_DATA_COMPARATOR_VALUE2",
145 "ETM_DATA_COMPARATOR_VALUE3",
146 "ETM_DATA_COMPARATOR_VALUE4",
147 "ETM_DATA_COMPARATOR_VALUE5",
148 "ETM_DATA_COMPARATOR_VALUE6",
149 "ETM_DATA_COMPARATOR_VALUE7",
150 "ETM_DATA_COMPARATOR_VALUE8",
151 "ETM_DATA_COMPARATOR_VALUE9",
152 "ETM_DATA_COMPARATOR_VALUE10",
153 "ETM_DATA_COMPARATOR_VALUE11",
154 "ETM_DATA_COMPARATOR_VALUE12",
155 "ETM_DATA_COMPARATOR_VALUE13",
156 "ETM_DATA_COMPARATOR_VALUE14",
157 "ETM_DATA_COMPARATOR_VALUE15",
158 "ETM_DATA_COMPARATOR_VALUE16",
159 "ETM_DATA_COMPARATOR_MASK1",
160 "ETM_DATA_COMPARATOR_MASK2",
161 "ETM_DATA_COMPARATOR_MASK3",
162 "ETM_DATA_COMPARATOR_MASK4",
163 "ETM_DATA_COMPARATOR_MASK5",
164 "ETM_DATA_COMPARATOR_MASK6",
165 "ETM_DATA_COMPARATOR_MASK7",
166 "ETM_DATA_COMPARATOR_MASK8",
167 "ETM_DATA_COMPARATOR_MASK9",
168 "ETM_DATA_COMPARATOR_MASK10",
169 "ETM_DATA_COMPARATOR_MASK11",
170 "ETM_DATA_COMPARATOR_MASK12",
171 "ETM_DATA_COMPARATOR_MASK13",
172 "ETM_DATA_COMPARATOR_MASK14",
173 "ETM_DATA_COMPARATOR_MASK15",
174 "ETM_DATA_COMPARATOR_MASK16",
175 "ETM_COUNTER_INITAL_VALUE1",
176 "ETM_COUNTER_INITAL_VALUE2",
177 "ETM_COUNTER_INITAL_VALUE3",
178 "ETM_COUNTER_INITAL_VALUE4",
179 "ETM_COUNTER_ENABLE1",
180 "ETM_COUNTER_ENABLE2",
181 "ETM_COUNTER_ENABLE3",
182 "ETM_COUNTER_ENABLE4",
183 "ETM_COUNTER_RELOAD_VALUE1",
184 "ETM_COUNTER_RELOAD_VALUE2",
185 "ETM_COUNTER_RELOAD_VALUE3",
186 "ETM_COUNTER_RELOAD_VALUE4",
187 "ETM_COUNTER_VALUE1",
188 "ETM_COUNTER_VALUE2",
189 "ETM_COUNTER_VALUE3",
190 "ETM_COUNTER_VALUE4",
191 "ETM_SEQUENCER_CTRL1",
192 "ETM_SEQUENCER_CTRL2",
193 "ETM_SEQUENCER_CTRL3",
194 "ETM_SEQUENCER_CTRL4",
195 "ETM_SEQUENCER_CTRL5",
196 "ETM_SEQUENCER_CTRL6",
197 "ETM_SEQUENCER_STATE",
198 "ETM_EXTERNAL_OUTPUT1",
199 "ETM_EXTERNAL_OUTPUT2",
200 "ETM_EXTERNAL_OUTPUT3",
201 "ETM_EXTERNAL_OUTPUT4",
202 "ETM_CONTEXTID_COMPARATOR_VALUE1",
203 "ETM_CONTEXTID_COMPARATOR_VALUE2",
204 "ETM_CONTEXTID_COMPARATOR_VALUE3",
205 "ETM_CONTEXTID_COMPARATOR_MASK"
206 };
207
208 int etm_reg_arch_type = -1;
209
210 int etm_get_reg(reg_t *reg);
211 int etm_set_reg(reg_t *reg, u32 value);
212 int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
213
214 int etm_write_reg(reg_t *reg, u32 value);
215 int etm_read_reg(reg_t *reg);
216
217 command_t *etm_cmd = NULL;
218
219 reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
220 {
221 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
222 reg_t *reg_list = NULL;
223 etm_reg_t *arch_info = NULL;
224 int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
225 int i;
226
227 /* register a register arch-type for etm registers only once */
228 if (etm_reg_arch_type == -1)
229 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
230
231 /* the actual registers are kept in two arrays */
232 reg_list = calloc(num_regs, sizeof(reg_t));
233 arch_info = calloc(num_regs, sizeof(etm_reg_t));
234
235 /* fill in values for the reg cache */
236 reg_cache->name = "etm registers";
237 reg_cache->next = NULL;
238 reg_cache->reg_list = reg_list;
239 reg_cache->num_regs = num_regs;
240
241 /* set up registers */
242 for (i = 0; i < num_regs; i++)
243 {
244 reg_list[i].name = etm_reg_list[i];
245 reg_list[i].size = 32;
246 reg_list[i].dirty = 0;
247 reg_list[i].valid = 0;
248 reg_list[i].bitfield_desc = NULL;
249 reg_list[i].num_bitfields = 0;
250 reg_list[i].value = calloc(1, 4);
251 reg_list[i].arch_info = &arch_info[i];
252 reg_list[i].arch_type = etm_reg_arch_type;
253 reg_list[i].size = etm_reg_arch_size_info[i];
254 arch_info[i].addr = etm_reg_arch_info[i];
255 arch_info[i].jtag_info = jtag_info;
256 }
257
258 /* the ETM might have an ETB connected */
259 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
260 {
261 etb_t *etb = etm_ctx->capture_driver_priv;
262
263 if (!etb)
264 {
265 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
266 return ERROR_OK;
267 }
268
269 reg_cache->next = etb_build_reg_cache(etb);
270
271 etb->reg_cache = reg_cache->next;
272 }
273
274
275 return reg_cache;
276 }
277
278 int etm_setup(target_t *target)
279 {
280 int retval;
281 u32 etm_ctrl_value;
282 armv4_5_common_t *armv4_5 = target->arch_info;
283 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
284 etm_context_t *etm_ctx = arm7_9->etm_ctx;
285 reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
286 /* initialize some ETM control register settings */
287 etm_get_reg(etm_ctrl_reg);
288 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
289
290 /* clear the ETM powerdown bit (0) */
291 etm_ctrl_value &= ~0x1;
292
293 /* configure port width (6:4), mode (17:16) and clocking (13) */
294 etm_ctrl_value = (etm_ctrl_value &
295 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
296 | etm_ctx->portmode;
297
298 buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
299 etm_store_reg(etm_ctrl_reg);
300
301 if ((retval=jtag_execute_queue())!=ERROR_OK)
302 return retval;
303
304 if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
305 {
306 LOG_ERROR("ETM capture driver initialization failed");
307 return retval;
308 }
309 return ERROR_OK;
310 }
311
312 int etm_get_reg(reg_t *reg)
313 {
314 int retval;
315 if ((retval = etm_read_reg(reg)) != ERROR_OK)
316 {
317 LOG_ERROR("BUG: error scheduling etm register read");
318 return retval;
319 }
320
321 if ((retval = jtag_execute_queue()) != ERROR_OK)
322 {
323 LOG_ERROR("register read failed");
324 return retval;
325 }
326
327 return ERROR_OK;
328 }
329
330 int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
331 {
332 etm_reg_t *etm_reg = reg->arch_info;
333 u8 reg_addr = etm_reg->addr & 0x7f;
334 scan_field_t fields[3];
335
336 LOG_DEBUG("%i", etm_reg->addr);
337
338 jtag_add_end_state(TAP_IDLE);
339 arm_jtag_scann(etm_reg->jtag_info, 0x6);
340 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
341
342 fields[0].tap = etm_reg->jtag_info->tap;
343 fields[0].num_bits = 32;
344 fields[0].out_value = reg->value;
345 fields[0].out_mask = NULL;
346 fields[0].in_value = NULL;
347 fields[0].in_check_value = NULL;
348 fields[0].in_check_mask = NULL;
349 fields[0].in_handler = NULL;
350 fields[0].in_handler_priv = NULL;
351
352 fields[1].tap = etm_reg->jtag_info->tap;
353 fields[1].num_bits = 7;
354 fields[1].out_value = malloc(1);
355 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
356 fields[1].out_mask = NULL;
357 fields[1].in_value = NULL;
358 fields[1].in_check_value = NULL;
359 fields[1].in_check_mask = NULL;
360 fields[1].in_handler = NULL;
361 fields[1].in_handler_priv = NULL;
362
363 fields[2].tap = etm_reg->jtag_info->tap;
364 fields[2].num_bits = 1;
365 fields[2].out_value = malloc(1);
366 buf_set_u32(fields[2].out_value, 0, 1, 0);
367 fields[2].out_mask = NULL;
368 fields[2].in_value = NULL;
369 fields[2].in_check_value = NULL;
370 fields[2].in_check_mask = NULL;
371 fields[2].in_handler = NULL;
372 fields[2].in_handler_priv = NULL;
373
374 jtag_add_dr_scan(3, fields, TAP_INVALID);
375
376 fields[0].in_value = reg->value;
377 jtag_set_check_value(fields+0, check_value, check_mask, NULL);
378
379 jtag_add_dr_scan(3, fields, TAP_INVALID);
380
381 free(fields[1].out_value);
382 free(fields[2].out_value);
383
384 return ERROR_OK;
385 }
386
387 int etm_read_reg(reg_t *reg)
388 {
389 return etm_read_reg_w_check(reg, NULL, NULL);
390 }
391
392 int etm_set_reg(reg_t *reg, u32 value)
393 {
394 int retval;
395 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
396 {
397 LOG_ERROR("BUG: error scheduling etm register write");
398 return retval;
399 }
400
401 buf_set_u32(reg->value, 0, reg->size, value);
402 reg->valid = 1;
403 reg->dirty = 0;
404
405 return ERROR_OK;
406 }
407
408 int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
409 {
410 int retval;
411 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
412
413 if ((retval = jtag_execute_queue()) != ERROR_OK)
414 {
415 LOG_ERROR("register write failed");
416 return retval;
417 }
418 return ERROR_OK;
419 }
420
421 int etm_write_reg(reg_t *reg, u32 value)
422 {
423 etm_reg_t *etm_reg = reg->arch_info;
424 u8 reg_addr = etm_reg->addr & 0x7f;
425 scan_field_t fields[3];
426
427 LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
428
429 jtag_add_end_state(TAP_IDLE);
430 arm_jtag_scann(etm_reg->jtag_info, 0x6);
431 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
432
433 fields[0].tap = etm_reg->jtag_info->tap;
434 fields[0].num_bits = 32;
435 fields[0].out_value = malloc(4);
436 buf_set_u32(fields[0].out_value, 0, 32, value);
437 fields[0].out_mask = NULL;
438 fields[0].in_value = NULL;
439 fields[0].in_check_value = NULL;
440 fields[0].in_check_mask = NULL;
441 fields[0].in_handler = NULL;
442 fields[0].in_handler_priv = NULL;
443
444 fields[1].tap = etm_reg->jtag_info->tap;
445 fields[1].num_bits = 7;
446 fields[1].out_value = malloc(1);
447 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
448 fields[1].out_mask = NULL;
449 fields[1].in_value = NULL;
450 fields[1].in_check_value = NULL;
451 fields[1].in_check_mask = NULL;
452 fields[1].in_handler = NULL;
453 fields[1].in_handler_priv = NULL;
454
455 fields[2].tap = etm_reg->jtag_info->tap;
456 fields[2].num_bits = 1;
457 fields[2].out_value = malloc(1);
458 buf_set_u32(fields[2].out_value, 0, 1, 1);
459 fields[2].out_mask = NULL;
460 fields[2].in_value = NULL;
461 fields[2].in_check_value = NULL;
462 fields[2].in_check_mask = NULL;
463 fields[2].in_handler = NULL;
464 fields[2].in_handler_priv = NULL;
465
466 jtag_add_dr_scan(3, fields, TAP_INVALID);
467
468 free(fields[0].out_value);
469 free(fields[1].out_value);
470 free(fields[2].out_value);
471
472 return ERROR_OK;
473 }
474
475 int etm_store_reg(reg_t *reg)
476 {
477 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
478 }
479
480 /* ETM trace analysis functionality
481 *
482 */
483 extern etm_capture_driver_t etb_capture_driver;
484 extern etm_capture_driver_t etm_dummy_capture_driver;
485 #if BUILD_OOCD_TRACE == 1
486 extern etm_capture_driver_t oocd_trace_capture_driver;
487 #endif
488
489 etm_capture_driver_t *etm_capture_drivers[] =
490 {
491 &etb_capture_driver,
492 &etm_dummy_capture_driver,
493 #if BUILD_OOCD_TRACE == 1
494 &oocd_trace_capture_driver,
495 #endif
496 NULL
497 };
498
499 char *etmv1v1_branch_reason_strings[] =
500 {
501 "normal PC change",
502 "tracing enabled",
503 "trace restarted after overflow",
504 "exit from debug",
505 "periodic synchronization",
506 "reserved",
507 "reserved",
508 "reserved",
509 };
510
511 int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
512 {
513 int i;
514 int section = -1;
515 u32 size_read;
516 u32 opcode;
517 int retval;
518
519 if (!ctx->image)
520 return ERROR_TRACE_IMAGE_UNAVAILABLE;
521
522 /* search for the section the current instruction belongs to */
523 for (i = 0; i < ctx->image->num_sections; i++)
524 {
525 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
526 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
527 {
528 section = i;
529 break;
530 }
531 }
532
533 if (section == -1)
534 {
535 /* current instruction couldn't be found in the image */
536 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
537 }
538
539 if (ctx->core_state == ARMV4_5_STATE_ARM)
540 {
541 u8 buf[4];
542 if ((retval = image_read_section(ctx->image, section,
543 ctx->current_pc - ctx->image->sections[section].base_address,
544 4, buf, &size_read)) != ERROR_OK)
545 {
546 LOG_ERROR("error while reading instruction: %i", retval);
547 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
548 }
549 opcode = target_buffer_get_u32(ctx->target, buf);
550 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
551 }
552 else if (ctx->core_state == ARMV4_5_STATE_THUMB)
553 {
554 u8 buf[2];
555 if ((retval = image_read_section(ctx->image, section,
556 ctx->current_pc - ctx->image->sections[section].base_address,
557 2, buf, &size_read)) != ERROR_OK)
558 {
559 LOG_ERROR("error while reading instruction: %i", retval);
560 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
561 }
562 opcode = target_buffer_get_u16(ctx->target, buf);
563 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
564 }
565 else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
566 {
567 LOG_ERROR("BUG: tracing of jazelle code not supported");
568 exit(-1);
569 }
570 else
571 {
572 LOG_ERROR("BUG: unknown core state encountered");
573 exit(-1);
574 }
575
576 return ERROR_OK;
577 }
578
579 int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo)
580 {
581 while (ctx->data_index < ctx->trace_depth)
582 {
583 /* if the caller specified an address packet offset, skip until the
584 * we reach the n-th cycle marked with tracesync */
585 if (apo > 0)
586 {
587 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
588 apo--;
589
590 if (apo > 0)
591 {
592 ctx->data_index++;
593 ctx->data_half = 0;
594 }
595 continue;
596 }
597
598 /* no tracedata output during a TD cycle
599 * or in a trigger cycle */
600 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
601 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
602 {
603 ctx->data_index++;
604 ctx->data_half = 0;
605 continue;
606 }
607
608 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
609 {
610 if (ctx->data_half == 0)
611 {
612 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
613 ctx->data_half = 1;
614 }
615 else
616 {
617 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
618 ctx->data_half = 0;
619 ctx->data_index++;
620 }
621 }
622 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
623 {
624 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
625 ctx->data_index++;
626 }
627 else
628 {
629 /* on a 4-bit port, a packet will be output during two consecutive cycles */
630 if (ctx->data_index > (ctx->trace_depth - 2))
631 return -1;
632
633 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
634 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
635 ctx->data_index += 2;
636 }
637
638 return 0;
639 }
640
641 return -1;
642 }
643
644 int etmv1_branch_address(etm_context_t *ctx)
645 {
646 int retval;
647 u8 packet;
648 int shift = 0;
649 int apo;
650 u32 i;
651
652 /* quit analysis if less than two cycles are left in the trace
653 * because we can't extract the APO */
654 if (ctx->data_index > (ctx->trace_depth - 2))
655 return -1;
656
657 /* a BE could be output during an APO cycle, skip the current
658 * and continue with the new one */
659 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
660 return 1;
661 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
662 return 2;
663
664 /* address packet offset encoded in the next two cycles' pipestat bits */
665 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
666 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
667
668 /* count number of tracesync cycles between current pipe_index and data_index
669 * i.e. the number of tracesyncs that data_index already passed by
670 * to subtract them from the APO */
671 for (i = ctx->pipe_index; i < ctx->data_index; i++)
672 {
673 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
674 apo--;
675 }
676
677 /* extract up to four 7-bit packets */
678 do {
679 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
680 return -1;
681 ctx->last_branch &= ~(0x7f << shift);
682 ctx->last_branch |= (packet & 0x7f) << shift;
683 shift += 7;
684 } while ((packet & 0x80) && (shift < 28));
685
686 /* one last packet holding 4 bits of the address, plus the branch reason code */
687 if ((shift == 28) && (packet & 0x80))
688 {
689 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
690 return -1;
691 ctx->last_branch &= 0x0fffffff;
692 ctx->last_branch |= (packet & 0x0f) << 28;
693 ctx->last_branch_reason = (packet & 0x70) >> 4;
694 shift += 4;
695 }
696 else
697 {
698 ctx->last_branch_reason = 0;
699 }
700
701 if (shift == 32)
702 {
703 ctx->pc_ok = 1;
704 }
705
706 /* if a full address was output, we might have branched into Jazelle state */
707 if ((shift == 32) && (packet & 0x80))
708 {
709 ctx->core_state = ARMV4_5_STATE_JAZELLE;
710 }
711 else
712 {
713 /* if we didn't branch into Jazelle state, the current processor state is
714 * encoded in bit 0 of the branch target address */
715 if (ctx->last_branch & 0x1)
716 {
717 ctx->core_state = ARMV4_5_STATE_THUMB;
718 ctx->last_branch &= ~0x1;
719 }
720 else
721 {
722 ctx->core_state = ARMV4_5_STATE_ARM;
723 ctx->last_branch &= ~0x3;
724 }
725 }
726
727 return 0;
728 }
729
730 int etmv1_data(etm_context_t *ctx, int size, u32 *data)
731 {
732 int j;
733 u8 buf[4];
734 int retval;
735
736 for (j = 0; j < size; j++)
737 {
738 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
739 return -1;
740 }
741
742 if (size == 8)
743 {
744 LOG_ERROR("TODO: add support for 64-bit values");
745 return -1;
746 }
747 else if (size == 4)
748 *data = target_buffer_get_u32(ctx->target, buf);
749 else if (size == 2)
750 *data = target_buffer_get_u16(ctx->target, buf);
751 else if (size == 1)
752 *data = buf[0];
753 else
754 return -1;
755
756 return 0;
757 }
758
759 int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
760 {
761 int retval;
762 arm_instruction_t instruction;
763
764 /* read the trace data if it wasn't read already */
765 if (ctx->trace_depth == 0)
766 ctx->capture_driver->read_trace(ctx);
767
768 /* start at the beginning of the captured trace */
769 ctx->pipe_index = 0;
770 ctx->data_index = 0;
771 ctx->data_half = 0;
772
773 /* neither the PC nor the data pointer are valid */
774 ctx->pc_ok = 0;
775 ctx->ptr_ok = 0;
776
777 while (ctx->pipe_index < ctx->trace_depth)
778 {
779 u8 pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
780 u32 next_pc = ctx->current_pc;
781 u32 old_data_index = ctx->data_index;
782 u32 old_data_half = ctx->data_half;
783 u32 old_index = ctx->pipe_index;
784 u32 last_instruction = ctx->last_instruction;
785 u32 cycles = 0;
786 int current_pc_ok = ctx->pc_ok;
787
788 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
789 {
790 command_print(cmd_ctx, "--- trigger ---");
791 }
792
793 /* instructions execute in IE/D or BE/D cycles */
794 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
795 ctx->last_instruction = ctx->pipe_index;
796
797 /* if we don't have a valid pc skip until we reach an indirect branch */
798 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
799 {
800 ctx->pipe_index++;
801 continue;
802 }
803
804 /* any indirect branch could have interrupted instruction flow
805 * - the branch reason code could indicate a trace discontinuity
806 * - a branch to the exception vectors indicates an exception
807 */
808 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
809 {
810 /* backup current data index, to be able to consume the branch address
811 * before examining data address and values
812 */
813 old_data_index = ctx->data_index;
814 old_data_half = ctx->data_half;
815
816 ctx->last_instruction = ctx->pipe_index;
817
818 if ((retval = etmv1_branch_address(ctx)) != 0)
819 {
820 /* negative return value from etmv1_branch_address means we ran out of packets,
821 * quit analysing the trace */
822 if (retval < 0)
823 break;
824
825 /* a positive return values means the current branch was abandoned,
826 * and a new branch was encountered in cycle ctx->pipe_index + retval;
827 */
828 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
829 ctx->pipe_index += retval;
830 continue;
831 }
832
833 /* skip over APO cycles */
834 ctx->pipe_index += 2;
835
836 switch (ctx->last_branch_reason)
837 {
838 case 0x0: /* normal PC change */
839 next_pc = ctx->last_branch;
840 break;
841 case 0x1: /* tracing enabled */
842 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
843 ctx->current_pc = ctx->last_branch;
844 ctx->pipe_index++;
845 continue;
846 break;
847 case 0x2: /* trace restarted after FIFO overflow */
848 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
849 ctx->current_pc = ctx->last_branch;
850 ctx->pipe_index++;
851 continue;
852 break;
853 case 0x3: /* exit from debug state */
854 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
855 ctx->current_pc = ctx->last_branch;
856 ctx->pipe_index++;
857 continue;
858 break;
859 case 0x4: /* periodic synchronization point */
860 next_pc = ctx->last_branch;
861 /* if we had no valid PC prior to this synchronization point,
862 * we have to move on with the next trace cycle
863 */
864 if (!current_pc_ok)
865 {
866 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8x ---", next_pc);
867 ctx->current_pc = next_pc;
868 ctx->pipe_index++;
869 continue;
870 }
871 break;
872 default: /* reserved */
873 LOG_ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
874 exit(-1);
875 break;
876 }
877
878 /* if we got here the branch was a normal PC change
879 * (or a periodic synchronization point, which means the same for that matter)
880 * if we didn't accquire a complete PC continue with the next cycle
881 */
882 if (!ctx->pc_ok)
883 continue;
884
885 /* indirect branch to the exception vector means an exception occured */
886 if ((ctx->last_branch <= 0x20)
887 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
888 {
889 if ((ctx->last_branch & 0xff) == 0x10)
890 {
891 command_print(cmd_ctx, "data abort");
892 }
893 else
894 {
895 command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
896 ctx->current_pc = ctx->last_branch;
897 ctx->pipe_index++;
898 continue;
899 }
900 }
901 }
902
903 /* an instruction was executed (or not, depending on the condition flags)
904 * retrieve it from the image for displaying */
905 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
906 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
907 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
908 {
909 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
910 {
911 /* can't continue tracing with no image available */
912 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
913 {
914 return retval;
915 }
916 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
917 {
918 /* TODO: handle incomplete images
919 * for now we just quit the analsysis*/
920 return retval;
921 }
922 }
923
924 cycles = old_index - last_instruction;
925 }
926
927 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
928 {
929 u32 new_data_index = ctx->data_index;
930 u32 new_data_half = ctx->data_half;
931
932 /* in case of a branch with data, the branch target address was consumed before
933 * we temporarily go back to the saved data index */
934 if (pipestat == STAT_BD)
935 {
936 ctx->data_index = old_data_index;
937 ctx->data_half = old_data_half;
938 }
939
940 if (ctx->tracemode & ETMV1_TRACE_ADDR)
941 {
942 u8 packet;
943 int shift = 0;
944
945 do {
946 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
947 return ERROR_ETM_ANALYSIS_FAILED;
948 ctx->last_ptr &= ~(0x7f << shift);
949 ctx->last_ptr |= (packet & 0x7f) << shift;
950 shift += 7;
951 } while ((packet & 0x80) && (shift < 32));
952
953 if (shift >= 32)
954 ctx->ptr_ok = 1;
955
956 if (ctx->ptr_ok)
957 {
958 command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
959 }
960 }
961
962 if (ctx->tracemode & ETMV1_TRACE_DATA)
963 {
964 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
965 {
966 int i;
967 for (i = 0; i < 16; i++)
968 {
969 if (instruction.info.load_store_multiple.register_list & (1 << i))
970 {
971 u32 data;
972 if (etmv1_data(ctx, 4, &data) != 0)
973 return ERROR_ETM_ANALYSIS_FAILED;
974 command_print(cmd_ctx, "data: 0x%8.8x", data);
975 }
976 }
977 }
978 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
979 {
980 u32 data;
981 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
982 return ERROR_ETM_ANALYSIS_FAILED;
983 command_print(cmd_ctx, "data: 0x%8.8x", data);
984 }
985 }
986
987 /* restore data index after consuming BD address and data */
988 if (pipestat == STAT_BD)
989 {
990 ctx->data_index = new_data_index;
991 ctx->data_half = new_data_half;
992 }
993 }
994
995 /* adjust PC */
996 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
997 {
998 if (((instruction.type == ARM_B) ||
999 (instruction.type == ARM_BL) ||
1000 (instruction.type == ARM_BLX)) &&
1001 (instruction.info.b_bl_bx_blx.target_address != ~0UL))
1002 {
1003 next_pc = instruction.info.b_bl_bx_blx.target_address;
1004 }
1005 else
1006 {
1007 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1008 }
1009 }
1010 else if (pipestat == STAT_IN)
1011 {
1012 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1013 }
1014
1015 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1016 {
1017 char cycles_text[32] = "";
1018
1019 /* if the trace was captured with cycle accurate tracing enabled,
1020 * output the number of cycles since the last executed instruction
1021 */
1022 if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1023 {
1024 snprintf(cycles_text, 32, " (%i %s)",
1025 cycles,
1026 (cycles == 1) ? "cycle" : "cycles");
1027 }
1028
1029 command_print(cmd_ctx, "%s%s%s",
1030 instruction.text,
1031 (pipestat == STAT_IN) ? " (not executed)" : "",
1032 cycles_text);
1033
1034 ctx->current_pc = next_pc;
1035
1036 /* packets for an instruction don't start on or before the preceding
1037 * functional pipestat (i.e. other than WT or TD)
1038 */
1039 if (ctx->data_index <= ctx->pipe_index)
1040 {
1041 ctx->data_index = ctx->pipe_index + 1;
1042 ctx->data_half = 0;
1043 }
1044 }
1045
1046 ctx->pipe_index += 1;
1047 }
1048
1049 return ERROR_OK;
1050 }
1051
1052 int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1053 {
1054 target_t *target;
1055 armv4_5_common_t *armv4_5;
1056 arm7_9_common_t *arm7_9;
1057 etmv1_tracemode_t tracemode;
1058
1059 target = get_current_target(cmd_ctx);
1060
1061 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1062 {
1063 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1064 return ERROR_OK;
1065 }
1066
1067 if (!arm7_9->etm_ctx)
1068 {
1069 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1070 return ERROR_OK;
1071 }
1072
1073 tracemode = arm7_9->etm_ctx->tracemode;
1074
1075 if (argc == 4)
1076 {
1077 if (strcmp(args[0], "none") == 0)
1078 {
1079 tracemode = ETMV1_TRACE_NONE;
1080 }
1081 else if (strcmp(args[0], "data") == 0)
1082 {
1083 tracemode = ETMV1_TRACE_DATA;
1084 }
1085 else if (strcmp(args[0], "address") == 0)
1086 {
1087 tracemode = ETMV1_TRACE_ADDR;
1088 }
1089 else if (strcmp(args[0], "all") == 0)
1090 {
1091 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1092 }
1093 else
1094 {
1095 command_print(cmd_ctx, "invalid option '%s'", args[0]);
1096 return ERROR_OK;
1097 }
1098
1099 switch (strtol(args[1], NULL, 0))
1100 {
1101 case 0:
1102 tracemode |= ETMV1_CONTEXTID_NONE;
1103 break;
1104 case 8:
1105 tracemode |= ETMV1_CONTEXTID_8;
1106 break;
1107 case 16:
1108 tracemode |= ETMV1_CONTEXTID_16;
1109 break;
1110 case 32:
1111 tracemode |= ETMV1_CONTEXTID_32;
1112 break;
1113 default:
1114 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1115 return ERROR_OK;
1116 }
1117
1118 if (strcmp(args[2], "enable") == 0)
1119 {
1120 tracemode |= ETMV1_CYCLE_ACCURATE;
1121 }
1122 else if (strcmp(args[2], "disable") == 0)
1123 {
1124 tracemode |= 0;
1125 }
1126 else
1127 {
1128 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1129 return ERROR_OK;
1130 }
1131
1132 if (strcmp(args[3], "enable") == 0)
1133 {
1134 tracemode |= ETMV1_BRANCH_OUTPUT;
1135 }
1136 else if (strcmp(args[3], "disable") == 0)
1137 {
1138 tracemode |= 0;
1139 }
1140 else
1141 {
1142 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1143 return ERROR_OK;
1144 }
1145 }
1146 else if (argc != 0)
1147 {
1148 command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
1149 return ERROR_OK;
1150 }
1151
1152 command_print(cmd_ctx, "current tracemode configuration:");
1153
1154 switch (tracemode & ETMV1_TRACE_MASK)
1155 {
1156 case ETMV1_TRACE_NONE:
1157 command_print(cmd_ctx, "data tracing: none");
1158 break;
1159 case ETMV1_TRACE_DATA:
1160 command_print(cmd_ctx, "data tracing: data only");
1161 break;
1162 case ETMV1_TRACE_ADDR:
1163 command_print(cmd_ctx, "data tracing: address only");
1164 break;
1165 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1166 command_print(cmd_ctx, "data tracing: address and data");
1167 break;
1168 }
1169
1170 switch (tracemode & ETMV1_CONTEXTID_MASK)
1171 {
1172 case ETMV1_CONTEXTID_NONE:
1173 command_print(cmd_ctx, "contextid tracing: none");
1174 break;
1175 case ETMV1_CONTEXTID_8:
1176 command_print(cmd_ctx, "contextid tracing: 8 bit");
1177 break;
1178 case ETMV1_CONTEXTID_16:
1179 command_print(cmd_ctx, "contextid tracing: 16 bit");
1180 break;
1181 case ETMV1_CONTEXTID_32:
1182 command_print(cmd_ctx, "contextid tracing: 32 bit");
1183 break;
1184 }
1185
1186 if (tracemode & ETMV1_CYCLE_ACCURATE)
1187 {
1188 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1189 }
1190 else
1191 {
1192 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1193 }
1194
1195 if (tracemode & ETMV1_BRANCH_OUTPUT)
1196 {
1197 command_print(cmd_ctx, "full branch address output enabled");
1198 }
1199 else
1200 {
1201 command_print(cmd_ctx, "full branch address output disabled");
1202 }
1203
1204 /* only update ETM_CTRL register if tracemode changed */
1205 if (arm7_9->etm_ctx->tracemode != tracemode)
1206 {
1207 reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1208
1209 etm_get_reg(etm_ctrl_reg);
1210
1211 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1212 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1213 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1214 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1215 etm_store_reg(etm_ctrl_reg);
1216
1217 arm7_9->etm_ctx->tracemode = tracemode;
1218
1219 /* invalidate old trace data */
1220 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1221 if (arm7_9->etm_ctx->trace_depth > 0)
1222 {
1223 free(arm7_9->etm_ctx->trace_data);
1224 arm7_9->etm_ctx->trace_data = NULL;
1225 }
1226 arm7_9->etm_ctx->trace_depth = 0;
1227 }
1228
1229 return ERROR_OK;
1230 }
1231
1232 int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1233 {
1234 target_t *target;
1235 armv4_5_common_t *armv4_5;
1236 arm7_9_common_t *arm7_9;
1237 etm_portmode_t portmode = 0x0;
1238 etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1239 int i;
1240
1241 if (argc != 5)
1242 {
1243 return ERROR_COMMAND_SYNTAX_ERROR;
1244 }
1245
1246 target = get_target_by_num(strtoul(args[0], NULL, 0));
1247
1248 if (!target)
1249 {
1250 LOG_ERROR("target number '%s' not defined", args[0]);
1251 return ERROR_FAIL;
1252 }
1253
1254 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1255 {
1256 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1257 return ERROR_FAIL;
1258 }
1259
1260 switch (strtoul(args[1], NULL, 0))
1261 {
1262 case 4:
1263 portmode |= ETM_PORT_4BIT;
1264 break;
1265 case 8:
1266 portmode |= ETM_PORT_8BIT;
1267 break;
1268 case 16:
1269 portmode |= ETM_PORT_16BIT;
1270 break;
1271 default:
1272 command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1273 return ERROR_FAIL;
1274 }
1275
1276 if (strcmp("normal", args[2]) == 0)
1277 {
1278 portmode |= ETM_PORT_NORMAL;
1279 }
1280 else if (strcmp("multiplexed", args[2]) == 0)
1281 {
1282 portmode |= ETM_PORT_MUXED;
1283 }
1284 else if (strcmp("demultiplexed", args[2]) == 0)
1285 {
1286 portmode |= ETM_PORT_DEMUXED;
1287 }
1288 else
1289 {
1290 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1291 return ERROR_FAIL;
1292 }
1293
1294 if (strcmp("half", args[3]) == 0)
1295 {
1296 portmode |= ETM_PORT_HALF_CLOCK;
1297 }
1298 else if (strcmp("full", args[3]) == 0)
1299 {
1300 portmode |= ETM_PORT_FULL_CLOCK;
1301 }
1302 else
1303 {
1304 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1305 return ERROR_FAIL;
1306 }
1307
1308 for (i=0; etm_capture_drivers[i]; i++)
1309 {
1310 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1311 {
1312 int retval;
1313 if ((retval=etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1314 {
1315 free(etm_ctx);
1316 return retval;
1317 }
1318
1319 etm_ctx->capture_driver = etm_capture_drivers[i];
1320
1321 break;
1322 }
1323 }
1324
1325 if (!etm_capture_drivers[i])
1326 {
1327 /* no supported capture driver found, don't register an ETM */
1328 free(etm_ctx);
1329 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1330 return ERROR_FAIL;
1331 }
1332
1333 etm_ctx->target = target;
1334 etm_ctx->trigger_percent = 50;
1335 etm_ctx->trace_data = NULL;
1336 etm_ctx->trace_depth = 0;
1337 etm_ctx->portmode = portmode;
1338 etm_ctx->tracemode = 0x0;
1339 etm_ctx->core_state = ARMV4_5_STATE_ARM;
1340 etm_ctx->image = NULL;
1341 etm_ctx->pipe_index = 0;
1342 etm_ctx->data_index = 0;
1343 etm_ctx->current_pc = 0x0;
1344 etm_ctx->pc_ok = 0;
1345 etm_ctx->last_branch = 0x0;
1346 etm_ctx->last_branch_reason = 0x0;
1347 etm_ctx->last_ptr = 0x0;
1348 etm_ctx->ptr_ok = 0x0;
1349 etm_ctx->context_id = 0x0;
1350 etm_ctx->last_instruction = 0;
1351
1352 arm7_9->etm_ctx = etm_ctx;
1353
1354 return etm_register_user_commands(cmd_ctx);
1355 }
1356
1357 int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1358 {
1359 target_t *target;
1360 armv4_5_common_t *armv4_5;
1361 arm7_9_common_t *arm7_9;
1362 reg_t *etm_config_reg;
1363 reg_t *etm_sys_config_reg;
1364
1365 int max_port_size;
1366
1367 target = get_current_target(cmd_ctx);
1368
1369 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1370 {
1371 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1372 return ERROR_OK;
1373 }
1374
1375 if (!arm7_9->etm_ctx)
1376 {
1377 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1378 return ERROR_OK;
1379 }
1380
1381 etm_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CONFIG];
1382 etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
1383
1384 etm_get_reg(etm_config_reg);
1385 command_print(cmd_ctx, "pairs of address comparators: %i", buf_get_u32(etm_config_reg->value, 0, 4));
1386 command_print(cmd_ctx, "pairs of data comparators: %i", buf_get_u32(etm_config_reg->value, 4, 4));
1387 command_print(cmd_ctx, "memory map decoders: %i", buf_get_u32(etm_config_reg->value, 8, 5));
1388 command_print(cmd_ctx, "number of counters: %i", buf_get_u32(etm_config_reg->value, 13, 3));
1389 command_print(cmd_ctx, "sequencer %spresent",
1390 (buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
1391 command_print(cmd_ctx, "number of ext. inputs: %i", buf_get_u32(etm_config_reg->value, 17, 3));
1392 command_print(cmd_ctx, "number of ext. outputs: %i", buf_get_u32(etm_config_reg->value, 20, 3));
1393 command_print(cmd_ctx, "FIFO full %spresent",
1394 (buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
1395 command_print(cmd_ctx, "protocol version: %i", buf_get_u32(etm_config_reg->value, 28, 3));
1396
1397 etm_get_reg(etm_sys_config_reg);
1398
1399 switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1400 {
1401 case 0:
1402 max_port_size = 4;
1403 break;
1404 case 1:
1405 max_port_size = 8;
1406 break;
1407 case 2:
1408 max_port_size = 16;
1409 break;
1410 default:
1411 LOG_ERROR("Illegal max_port_size");
1412 exit(-1);
1413 }
1414 command_print(cmd_ctx, "max. port size: %i", max_port_size);
1415
1416 command_print(cmd_ctx, "half-rate clocking %ssupported",
1417 (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1418 command_print(cmd_ctx, "full-rate clocking %ssupported",
1419 (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1420 command_print(cmd_ctx, "normal trace format %ssupported",
1421 (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1422 command_print(cmd_ctx, "multiplex trace format %ssupported",
1423 (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1424 command_print(cmd_ctx, "demultiplex trace format %ssupported",
1425 (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1426 command_print(cmd_ctx, "FIFO full %ssupported",
1427 (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1428
1429 return ERROR_OK;
1430 }
1431
1432 int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1433 {
1434 target_t *target;
1435 armv4_5_common_t *armv4_5;
1436 arm7_9_common_t *arm7_9;
1437 trace_status_t trace_status;
1438
1439 target = get_current_target(cmd_ctx);
1440
1441 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1442 {
1443 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1444 return ERROR_OK;
1445 }
1446
1447 if (!arm7_9->etm_ctx)
1448 {
1449 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1450 return ERROR_OK;
1451 }
1452
1453 trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1454
1455 if (trace_status == TRACE_IDLE)
1456 {
1457 command_print(cmd_ctx, "tracing is idle");
1458 }
1459 else
1460 {
1461 static char *completed = " completed";
1462 static char *running = " is running";
1463 static char *overflowed = ", trace overflowed";
1464 static char *triggered = ", trace triggered";
1465
1466 command_print(cmd_ctx, "trace collection%s%s%s",
1467 (trace_status & TRACE_RUNNING) ? running : completed,
1468 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1469 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1470
1471 if (arm7_9->etm_ctx->trace_depth > 0)
1472 {
1473 command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
1474 }
1475 }
1476
1477 return ERROR_OK;
1478 }
1479
1480 int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1481 {
1482 target_t *target;
1483 armv4_5_common_t *armv4_5;
1484 arm7_9_common_t *arm7_9;
1485 etm_context_t *etm_ctx;
1486
1487 if (argc < 1)
1488 {
1489 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1490 return ERROR_OK;
1491 }
1492
1493 target = get_current_target(cmd_ctx);
1494
1495 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1496 {
1497 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1498 return ERROR_OK;
1499 }
1500
1501 if (!(etm_ctx = arm7_9->etm_ctx))
1502 {
1503 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1504 return ERROR_OK;
1505 }
1506
1507 if (etm_ctx->image)
1508 {
1509 image_close(etm_ctx->image);
1510 free(etm_ctx->image);
1511 command_print(cmd_ctx, "previously loaded image found and closed");
1512 }
1513
1514 etm_ctx->image = malloc(sizeof(image_t));
1515 etm_ctx->image->base_address_set = 0;
1516 etm_ctx->image->start_address_set = 0;
1517
1518 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1519 if (argc >= 2)
1520 {
1521 etm_ctx->image->base_address_set = 1;
1522 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1523 }
1524 else
1525 {
1526 etm_ctx->image->base_address_set = 0;
1527 }
1528
1529 if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1530 {
1531 free(etm_ctx->image);
1532 etm_ctx->image = NULL;
1533 return ERROR_OK;
1534 }
1535
1536 return ERROR_OK;
1537 }
1538
1539 int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1540 {
1541 fileio_t file;
1542 target_t *target;
1543 armv4_5_common_t *armv4_5;
1544 arm7_9_common_t *arm7_9;
1545 etm_context_t *etm_ctx;
1546 u32 i;
1547
1548 if (argc != 1)
1549 {
1550 command_print(cmd_ctx, "usage: etm dump <file>");
1551 return ERROR_OK;
1552 }
1553
1554 target = get_current_target(cmd_ctx);
1555
1556 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1557 {
1558 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1559 return ERROR_OK;
1560 }
1561
1562 if (!(etm_ctx = arm7_9->etm_ctx))
1563 {
1564 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1565 return ERROR_OK;
1566 }
1567
1568 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1569 {
1570 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1571 return ERROR_OK;
1572 }
1573
1574 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1575 {
1576 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1577 command_print(cmd_ctx, "trace capture not completed");
1578 return ERROR_OK;
1579 }
1580
1581 /* read the trace data if it wasn't read already */
1582 if (etm_ctx->trace_depth == 0)
1583 etm_ctx->capture_driver->read_trace(etm_ctx);
1584
1585 if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1586 {
1587 return ERROR_OK;
1588 }
1589
1590 fileio_write_u32(&file, etm_ctx->capture_status);
1591 fileio_write_u32(&file, etm_ctx->portmode);
1592 fileio_write_u32(&file, etm_ctx->tracemode);
1593 fileio_write_u32(&file, etm_ctx->trace_depth);
1594
1595 for (i = 0; i < etm_ctx->trace_depth; i++)
1596 {
1597 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1598 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1599 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1600 }
1601
1602 fileio_close(&file);
1603
1604 return ERROR_OK;
1605 }
1606
1607 int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1608 {
1609 fileio_t file;
1610 target_t *target;
1611 armv4_5_common_t *armv4_5;
1612 arm7_9_common_t *arm7_9;
1613 etm_context_t *etm_ctx;
1614 u32 i;
1615
1616 if (argc != 1)
1617 {
1618 command_print(cmd_ctx, "usage: etm load <file>");
1619 return ERROR_OK;
1620 }
1621
1622 target = get_current_target(cmd_ctx);
1623
1624 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1625 {
1626 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1627 return ERROR_OK;
1628 }
1629
1630 if (!(etm_ctx = arm7_9->etm_ctx))
1631 {
1632 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1633 return ERROR_OK;
1634 }
1635
1636 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1637 {
1638 command_print(cmd_ctx, "trace capture running, stop first");
1639 return ERROR_OK;
1640 }
1641
1642 if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1643 {
1644 return ERROR_OK;
1645 }
1646
1647 if (file.size % 4)
1648 {
1649 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1650 fileio_close(&file);
1651 return ERROR_OK;
1652 }
1653
1654 if (etm_ctx->trace_depth > 0)
1655 {
1656 free(etm_ctx->trace_data);
1657 etm_ctx->trace_data = NULL;
1658 }
1659
1660 fileio_read_u32(&file, &etm_ctx->capture_status);
1661 fileio_read_u32(&file, &etm_ctx->portmode);
1662 fileio_read_u32(&file, &etm_ctx->tracemode);
1663 fileio_read_u32(&file, &etm_ctx->trace_depth);
1664
1665 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1666 if(etm_ctx->trace_data == NULL)
1667 {
1668 command_print(cmd_ctx, "not enough memory to perform operation");
1669 fileio_close(&file);
1670 return ERROR_OK;
1671 }
1672
1673 for (i = 0; i < etm_ctx->trace_depth; i++)
1674 {
1675 u32 pipestat, packet, flags;
1676 fileio_read_u32(&file, &pipestat);
1677 fileio_read_u32(&file, &packet);
1678 fileio_read_u32(&file, &flags);
1679 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1680 etm_ctx->trace_data[i].packet = packet & 0xffff;
1681 etm_ctx->trace_data[i].flags = flags;
1682 }
1683
1684 fileio_close(&file);
1685
1686 return ERROR_OK;
1687 }
1688
1689 int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1690 {
1691 target_t *target;
1692 armv4_5_common_t *armv4_5;
1693 arm7_9_common_t *arm7_9;
1694 etm_context_t *etm_ctx;
1695
1696 target = get_current_target(cmd_ctx);
1697
1698 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1699 {
1700 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1701 return ERROR_OK;
1702 }
1703
1704 if (!(etm_ctx = arm7_9->etm_ctx))
1705 {
1706 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1707 return ERROR_OK;
1708 }
1709
1710 if (argc > 0)
1711 {
1712 u32 new_value = strtoul(args[0], NULL, 0);
1713
1714 if ((new_value < 2) || (new_value > 100))
1715 {
1716 command_print(cmd_ctx, "valid settings are 2% to 100%");
1717 }
1718 else
1719 {
1720 etm_ctx->trigger_percent = new_value;
1721 }
1722 }
1723
1724 command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx->trigger_percent);
1725
1726 return ERROR_OK;
1727 }
1728
1729 int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1730 {
1731 target_t *target;
1732 armv4_5_common_t *armv4_5;
1733 arm7_9_common_t *arm7_9;
1734 etm_context_t *etm_ctx;
1735 reg_t *etm_ctrl_reg;
1736
1737 target = get_current_target(cmd_ctx);
1738
1739 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1740 {
1741 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1742 return ERROR_OK;
1743 }
1744
1745 if (!(etm_ctx = arm7_9->etm_ctx))
1746 {
1747 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1748 return ERROR_OK;
1749 }
1750
1751 /* invalidate old tracing data */
1752 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1753 if (arm7_9->etm_ctx->trace_depth > 0)
1754 {
1755 free(arm7_9->etm_ctx->trace_data);
1756 arm7_9->etm_ctx->trace_data = NULL;
1757 }
1758 arm7_9->etm_ctx->trace_depth = 0;
1759
1760 etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1761 etm_get_reg(etm_ctrl_reg);
1762
1763 /* Clear programming bit (10), set port selection bit (11) */
1764 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1765
1766 etm_store_reg(etm_ctrl_reg);
1767 jtag_execute_queue();
1768
1769 etm_ctx->capture_driver->start_capture(etm_ctx);
1770
1771 return ERROR_OK;
1772 }
1773
1774 int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1775 {
1776 target_t *target;
1777 armv4_5_common_t *armv4_5;
1778 arm7_9_common_t *arm7_9;
1779 etm_context_t *etm_ctx;
1780 reg_t *etm_ctrl_reg;
1781
1782 target = get_current_target(cmd_ctx);
1783
1784 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1785 {
1786 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1787 return ERROR_OK;
1788 }
1789
1790 if (!(etm_ctx = arm7_9->etm_ctx))
1791 {
1792 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1793 return ERROR_OK;
1794 }
1795
1796 etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1797 etm_get_reg(etm_ctrl_reg);
1798
1799 /* Set programming bit (10), clear port selection bit (11) */
1800 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1801
1802 etm_store_reg(etm_ctrl_reg);
1803 jtag_execute_queue();
1804
1805 etm_ctx->capture_driver->stop_capture(etm_ctx);
1806
1807 return ERROR_OK;
1808 }
1809
1810 int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1811 {
1812 target_t *target;
1813 armv4_5_common_t *armv4_5;
1814 arm7_9_common_t *arm7_9;
1815 etm_context_t *etm_ctx;
1816 int retval;
1817
1818 target = get_current_target(cmd_ctx);
1819
1820 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1821 {
1822 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1823 return ERROR_OK;
1824 }
1825
1826 if (!(etm_ctx = arm7_9->etm_ctx))
1827 {
1828 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1829 return ERROR_OK;
1830 }
1831
1832 if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
1833 {
1834 switch(retval)
1835 {
1836 case ERROR_ETM_ANALYSIS_FAILED:
1837 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
1838 break;
1839 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1840 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
1841 break;
1842 case ERROR_TRACE_IMAGE_UNAVAILABLE:
1843 command_print(cmd_ctx, "no image available for trace analysis");
1844 break;
1845 default:
1846 command_print(cmd_ctx, "unknown error: %i", retval);
1847 }
1848 }
1849
1850 return ERROR_OK;
1851 }
1852
1853 int etm_register_commands(struct command_context_s *cmd_ctx)
1854 {
1855 etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1856
1857 register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
1858
1859 return ERROR_OK;
1860 }
1861
1862 int etm_register_user_commands(struct command_context_s *cmd_ctx)
1863 {
1864 register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
1865 COMMAND_EXEC, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
1866
1867 register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
1868 COMMAND_EXEC, "display info about the current target's ETM");
1869
1870 register_command(cmd_ctx, etm_cmd, "trigger_percent <percent>", handle_etm_trigger_percent_command,
1871 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1872 register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
1873 COMMAND_EXEC, "display current target's ETM status");
1874 register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
1875 COMMAND_EXEC, "start ETM trace collection");
1876 register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
1877 COMMAND_EXEC, "stop ETM trace collection");
1878
1879 register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
1880 COMMAND_EXEC, "anaylze collected ETM trace");
1881
1882 register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
1883 COMMAND_EXEC, "load image from <file> [base address]");
1884
1885 register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
1886 COMMAND_EXEC, "dump captured trace data <file>");
1887 register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
1888 COMMAND_EXEC, "load trace data for analysis <file>");
1889
1890 return ERROR_OK;
1891 }
Open On-Chip Debugger