1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm7_9_common.h"
28 static char* etb_reg_list
[] =
35 "ETB_ram_read_pointer",
36 "ETB_ram_write_pointer",
37 "ETB_trigger_counter",
41 static int etb_reg_arch_type
= -1;
43 static int etb_get_reg(reg_t
*reg
);
45 static int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
47 static int etb_set_instr(etb_t
*etb
, uint32_t new_instr
)
55 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
60 field
.num_bits
= tap
->ir_length
;
61 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
62 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
64 field
.in_value
= NULL
;
66 jtag_add_ir_scan(1, &field
, jtag_get_end_state());
68 free(field
.out_value
);
74 static int etb_scann(etb_t
*etb
, uint32_t new_scan_chain
)
76 if (etb
->cur_scan_chain
!= new_scan_chain
)
82 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
83 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_scan_chain
);
85 field
.in_value
= NULL
;
87 /* select INTEST instruction */
88 etb_set_instr(etb
, 0x2);
89 jtag_add_dr_scan(1, &field
, jtag_get_end_state());
91 etb
->cur_scan_chain
= new_scan_chain
;
93 free(field
.out_value
);
99 static int etb_read_reg_w_check(reg_t
*, uint8_t *, uint8_t *);
100 static int etb_set_reg_w_exec(reg_t
*, uint8_t *);
102 static int etb_read_reg(reg_t
*reg
)
104 return etb_read_reg_w_check(reg
, NULL
, NULL
);
107 static int etb_get_reg(reg_t
*reg
)
111 if ((retval
= etb_read_reg(reg
)) != ERROR_OK
)
113 LOG_ERROR("BUG: error scheduling etm register read");
117 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
119 LOG_ERROR("register read failed");
126 reg_cache_t
* etb_build_reg_cache(etb_t
*etb
)
128 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
129 reg_t
*reg_list
= NULL
;
130 etb_reg_t
*arch_info
= NULL
;
134 /* register a register arch-type for etm registers only once */
135 if (etb_reg_arch_type
== -1)
136 etb_reg_arch_type
= register_reg_arch_type(etb_get_reg
, etb_set_reg_w_exec
);
138 /* the actual registers are kept in two arrays */
139 reg_list
= calloc(num_regs
, sizeof(reg_t
));
140 arch_info
= calloc(num_regs
, sizeof(etb_reg_t
));
142 /* fill in values for the reg cache */
143 reg_cache
->name
= "etb registers";
144 reg_cache
->next
= NULL
;
145 reg_cache
->reg_list
= reg_list
;
146 reg_cache
->num_regs
= num_regs
;
148 /* set up registers */
149 for (i
= 0; i
< num_regs
; i
++)
151 reg_list
[i
].name
= etb_reg_list
[i
];
152 reg_list
[i
].size
= 32;
153 reg_list
[i
].dirty
= 0;
154 reg_list
[i
].valid
= 0;
155 reg_list
[i
].bitfield_desc
= NULL
;
156 reg_list
[i
].num_bitfields
= 0;
157 reg_list
[i
].value
= calloc(1, 4);
158 reg_list
[i
].arch_info
= &arch_info
[i
];
159 reg_list
[i
].arch_type
= etb_reg_arch_type
;
160 reg_list
[i
].size
= 32;
161 arch_info
[i
].addr
= i
;
162 arch_info
[i
].etb
= etb
;
168 static void etb_getbuf(jtag_callback_data_t arg
)
170 uint8_t *in
= (uint8_t *)arg
;
172 *((uint32_t *)in
) = buf_get_u32(in
, 0, 32);
176 static int etb_read_ram(etb_t
*etb
, uint32_t *data
, int num_frames
)
178 scan_field_t fields
[3];
181 jtag_set_end_state(TAP_IDLE
);
183 etb_set_instr(etb
, 0xc);
185 fields
[0].tap
= etb
->tap
;
186 fields
[0].num_bits
= 32;
187 fields
[0].out_value
= NULL
;
188 fields
[0].in_value
= NULL
;
190 fields
[1].tap
= etb
->tap
;
191 fields
[1].num_bits
= 7;
192 fields
[1].out_value
= malloc(1);
193 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
194 fields
[1].in_value
= NULL
;
196 fields
[2].tap
= etb
->tap
;
197 fields
[2].num_bits
= 1;
198 fields
[2].out_value
= malloc(1);
199 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
200 fields
[2].in_value
= NULL
;
202 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
204 for (i
= 0; i
< num_frames
; i
++)
206 /* ensure nR/W reamins set to read */
207 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
209 /* address remains set to 0x4 (RAM data) until we read the last frame */
210 if (i
< num_frames
- 1)
211 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
213 buf_set_u32(fields
[1].out_value
, 0, 7, 0);
215 fields
[0].in_value
= (uint8_t *)(data
+ i
);
216 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
218 jtag_add_callback(etb_getbuf
, (jtag_callback_data_t
)(data
+ i
));
221 jtag_execute_queue();
223 free(fields
[1].out_value
);
224 free(fields
[2].out_value
);
229 static int etb_read_reg_w_check(reg_t
*reg
,
230 uint8_t* check_value
, uint8_t* check_mask
)
232 etb_reg_t
*etb_reg
= reg
->arch_info
;
233 uint8_t reg_addr
= etb_reg
->addr
& 0x7f;
234 scan_field_t fields
[3];
236 LOG_DEBUG("%i", (int)(etb_reg
->addr
));
238 jtag_set_end_state(TAP_IDLE
);
239 etb_scann(etb_reg
->etb
, 0x0);
240 etb_set_instr(etb_reg
->etb
, 0xc);
242 fields
[0].tap
= etb_reg
->etb
->tap
;
243 fields
[0].num_bits
= 32;
244 fields
[0].out_value
= reg
->value
;
245 fields
[0].in_value
= NULL
;
246 fields
[0].check_value
= NULL
;
247 fields
[0].check_mask
= NULL
;
249 fields
[1].tap
= etb_reg
->etb
->tap
;
250 fields
[1].num_bits
= 7;
251 fields
[1].out_value
= malloc(1);
252 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
253 fields
[1].in_value
= NULL
;
254 fields
[1].check_value
= NULL
;
255 fields
[1].check_mask
= NULL
;
257 fields
[2].tap
= etb_reg
->etb
->tap
;
258 fields
[2].num_bits
= 1;
259 fields
[2].out_value
= malloc(1);
260 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
261 fields
[2].in_value
= NULL
;
262 fields
[2].check_value
= NULL
;
263 fields
[2].check_mask
= NULL
;
265 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
267 /* read the identification register in the second run, to make sure we
268 * don't read the ETB data register twice, skipping every second entry
270 buf_set_u32(fields
[1].out_value
, 0, 7, 0x0);
271 fields
[0].in_value
= reg
->value
;
272 fields
[0].check_value
= check_value
;
273 fields
[0].check_mask
= check_mask
;
275 jtag_add_dr_scan_check(3, fields
, jtag_get_end_state());
277 free(fields
[1].out_value
);
278 free(fields
[2].out_value
);
283 static int etb_write_reg(reg_t
*, uint32_t);
285 static int etb_set_reg(reg_t
*reg
, uint32_t value
)
289 if ((retval
= etb_write_reg(reg
, value
)) != ERROR_OK
)
291 LOG_ERROR("BUG: error scheduling etm register write");
295 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
302 static int etb_set_reg_w_exec(reg_t
*reg
, uint8_t *buf
)
306 etb_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
308 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
310 LOG_ERROR("register write failed");
316 static int etb_write_reg(reg_t
*reg
, uint32_t value
)
318 etb_reg_t
*etb_reg
= reg
->arch_info
;
319 uint8_t reg_addr
= etb_reg
->addr
& 0x7f;
320 scan_field_t fields
[3];
322 LOG_DEBUG("%i: 0x%8.8" PRIx32
"", (int)(etb_reg
->addr
), value
);
324 jtag_set_end_state(TAP_IDLE
);
325 etb_scann(etb_reg
->etb
, 0x0);
326 etb_set_instr(etb_reg
->etb
, 0xc);
328 fields
[0].tap
= etb_reg
->etb
->tap
;
329 fields
[0].num_bits
= 32;
330 fields
[0].out_value
= malloc(4);
331 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
332 fields
[0].in_value
= NULL
;
334 fields
[1].tap
= etb_reg
->etb
->tap
;
335 fields
[1].num_bits
= 7;
336 fields
[1].out_value
= malloc(1);
337 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
338 fields
[1].in_value
= NULL
;
340 fields
[2].tap
= etb_reg
->etb
->tap
;
341 fields
[2].num_bits
= 1;
342 fields
[2].out_value
= malloc(1);
343 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
345 fields
[2].in_value
= NULL
;
347 free(fields
[0].out_value
);
348 free(fields
[1].out_value
);
349 free(fields
[2].out_value
);
354 static int etb_register_commands(struct command_context_s
*cmd_ctx
)
358 etb_cmd
= register_command(cmd_ctx
, NULL
, "etb", NULL
, COMMAND_ANY
, "Embedded Trace Buffer");
360 register_command(cmd_ctx
, etb_cmd
, "config", handle_etb_config_command
, COMMAND_CONFIG
, NULL
);
365 static int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
369 armv4_5_common_t
*armv4_5
;
370 arm7_9_common_t
*arm7_9
;
374 return ERROR_COMMAND_SYNTAX_ERROR
;
377 target
= get_target(args
[0]);
381 LOG_ERROR("target '%s' not defined", args
[0]);
385 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
387 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
391 tap
= jtag_tap_by_string(args
[1]);
394 command_print(cmd_ctx
, "Tap: %s does not exist", args
[1]);
400 etb_t
*etb
= malloc(sizeof(etb_t
));
402 arm7_9
->etm_ctx
->capture_driver_priv
= etb
;
405 etb
->cur_scan_chain
= 0xffffffff;
406 etb
->reg_cache
= NULL
;
412 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
419 static int etb_init(etm_context_t
*etm_ctx
)
421 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
423 etb
->etm_ctx
= etm_ctx
;
425 /* identify ETB RAM depth and width */
426 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
]);
427 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
]);
428 jtag_execute_queue();
430 etb
->ram_depth
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
].value
, 0, 32);
431 etb
->ram_width
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
].value
, 0, 32);
436 static trace_status_t
etb_status(etm_context_t
*etm_ctx
)
438 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
440 etb
->etm_ctx
= etm_ctx
;
442 /* if tracing is currently idle, return this information */
443 if (etm_ctx
->capture_status
== TRACE_IDLE
)
445 return etm_ctx
->capture_status
;
447 else if (etm_ctx
->capture_status
& TRACE_RUNNING
)
449 reg_t
*etb_status_reg
= &etb
->reg_cache
->reg_list
[ETB_STATUS
];
450 int etb_timeout
= 100;
452 /* trace is running, check the ETB status flags */
453 etb_get_reg(etb_status_reg
);
455 /* check Full bit to identify an overflow */
456 if (buf_get_u32(etb_status_reg
->value
, 0, 1) == 1)
457 etm_ctx
->capture_status
|= TRACE_OVERFLOWED
;
459 /* check Triggered bit to identify trigger condition */
460 if (buf_get_u32(etb_status_reg
->value
, 1, 1) == 1)
461 etm_ctx
->capture_status
|= TRACE_TRIGGERED
;
463 /* check AcqComp to identify trace completion */
464 if (buf_get_u32(etb_status_reg
->value
, 2, 1) == 1)
466 while (etb_timeout
-- && (buf_get_u32(etb_status_reg
->value
, 3, 1) == 0))
468 /* wait for data formatter idle */
469 etb_get_reg(etb_status_reg
);
472 if (etb_timeout
== 0)
474 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%" PRIx32
"",
475 buf_get_u32(etb_status_reg
->value
, 0, etb_status_reg
->size
));
478 if (!(etm_ctx
->capture_status
&& TRACE_TRIGGERED
))
480 LOG_ERROR("trace completed, but no trigger condition detected");
483 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
484 etm_ctx
->capture_status
|= TRACE_COMPLETED
;
488 return etm_ctx
->capture_status
;
491 static int etb_read_trace(etm_context_t
*etm_ctx
)
493 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
495 int num_frames
= etb
->ram_depth
;
496 uint32_t *trace_data
= NULL
;
499 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_STATUS
]);
500 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
]);
501 jtag_execute_queue();
503 /* check if we overflowed, and adjust first frame of the trace accordingly
504 * if we didn't overflow, read only up to the frame that would be written next,
505 * i.e. don't read invalid entries
507 if (buf_get_u32(etb
->reg_cache
->reg_list
[ETB_STATUS
].value
, 0, 1))
509 first_frame
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
513 num_frames
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
516 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_READ_POINTER
], first_frame
);
518 /* read data into temporary array for unpacking */
519 trace_data
= malloc(sizeof(uint32_t) * num_frames
);
520 etb_read_ram(etb
, trace_data
, num_frames
);
522 if (etm_ctx
->trace_depth
> 0)
524 free(etm_ctx
->trace_data
);
527 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
528 etm_ctx
->trace_depth
= num_frames
* 3;
529 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
530 etm_ctx
->trace_depth
= num_frames
* 2;
532 etm_ctx
->trace_depth
= num_frames
;
534 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
536 for (i
= 0, j
= 0; i
< num_frames
; i
++)
538 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
541 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
542 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x78) >> 3;
543 etm_ctx
->trace_data
[j
].flags
= 0;
544 if ((trace_data
[i
] & 0x80) >> 7)
546 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
548 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
550 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
551 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
554 /* trace word j + 1 */
555 etm_ctx
->trace_data
[j
+ 1].pipestat
= (trace_data
[i
] & 0x100) >> 8;
556 etm_ctx
->trace_data
[j
+ 1].packet
= (trace_data
[i
] & 0x7800) >> 11;
557 etm_ctx
->trace_data
[j
+ 1].flags
= 0;
558 if ((trace_data
[i
] & 0x8000) >> 15)
560 etm_ctx
->trace_data
[j
+ 1].flags
|= ETMV1_TRACESYNC_CYCLE
;
562 if (etm_ctx
->trace_data
[j
+ 1].pipestat
== STAT_TR
)
564 etm_ctx
->trace_data
[j
+ 1].pipestat
= etm_ctx
->trace_data
[j
+ 1].packet
& 0x7;
565 etm_ctx
->trace_data
[j
+ 1].flags
|= ETMV1_TRIGGER_CYCLE
;
568 /* trace word j + 2 */
569 etm_ctx
->trace_data
[j
+ 2].pipestat
= (trace_data
[i
] & 0x10000) >> 16;
570 etm_ctx
->trace_data
[j
+ 2].packet
= (trace_data
[i
] & 0x780000) >> 19;
571 etm_ctx
->trace_data
[j
+ 2].flags
= 0;
572 if ((trace_data
[i
] & 0x800000) >> 23)
574 etm_ctx
->trace_data
[j
+ 2].flags
|= ETMV1_TRACESYNC_CYCLE
;
576 if (etm_ctx
->trace_data
[j
+ 2].pipestat
== STAT_TR
)
578 etm_ctx
->trace_data
[j
+ 2].pipestat
= etm_ctx
->trace_data
[j
+ 2].packet
& 0x7;
579 etm_ctx
->trace_data
[j
+ 2].flags
|= ETMV1_TRIGGER_CYCLE
;
584 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
587 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
588 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7f8) >> 3;
589 etm_ctx
->trace_data
[j
].flags
= 0;
590 if ((trace_data
[i
] & 0x800) >> 11)
592 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
594 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
596 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
597 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
600 /* trace word j + 1 */
601 etm_ctx
->trace_data
[j
+ 1].pipestat
= (trace_data
[i
] & 0x7000) >> 12;
602 etm_ctx
->trace_data
[j
+ 1].packet
= (trace_data
[i
] & 0x7f8000) >> 15;
603 etm_ctx
->trace_data
[j
+ 1].flags
= 0;
604 if ((trace_data
[i
] & 0x800000) >> 23)
606 etm_ctx
->trace_data
[j
+ 1].flags
|= ETMV1_TRACESYNC_CYCLE
;
608 if (etm_ctx
->trace_data
[j
+ 1].pipestat
== STAT_TR
)
610 etm_ctx
->trace_data
[j
+ 1].pipestat
= etm_ctx
->trace_data
[j
+ 1].packet
& 0x7;
611 etm_ctx
->trace_data
[j
+ 1].flags
|= ETMV1_TRIGGER_CYCLE
;
619 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
620 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7fff8) >> 3;
621 etm_ctx
->trace_data
[j
].flags
= 0;
622 if ((trace_data
[i
] & 0x80000) >> 19)
624 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
626 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
628 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
629 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
641 static int etb_start_capture(etm_context_t
*etm_ctx
)
643 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
644 uint32_t etb_ctrl_value
= 0x1;
645 uint32_t trigger_count
;
647 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_DEMUXED
)
649 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) != ETM_PORT_8BIT
)
651 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
652 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
654 etb_ctrl_value
|= 0x2;
657 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_MUXED
)
658 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
660 trigger_count
= (etb
->ram_depth
* etm_ctx
->trigger_percent
) / 100;
662 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_TRIGGER_COUNTER
], trigger_count
);
663 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
], 0x0);
664 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_CTRL
], etb_ctrl_value
);
665 jtag_execute_queue();
667 /* we're starting a new trace, initialize capture status */
668 etm_ctx
->capture_status
= TRACE_RUNNING
;
673 static int etb_stop_capture(etm_context_t
*etm_ctx
)
675 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
676 reg_t
*etb_ctrl_reg
= &etb
->reg_cache
->reg_list
[ETB_CTRL
];
678 etb_write_reg(etb_ctrl_reg
, 0x0);
679 jtag_execute_queue();
681 /* trace stopped, just clear running flag, but preserve others */
682 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
687 etm_capture_driver_t etb_capture_driver
=
690 .register_commands
= etb_register_commands
,
692 .status
= etb_status
,
693 .start_capture
= etb_start_capture
,
694 .stop_capture
= etb_stop_capture
,
695 .read_trace
= etb_read_trace
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)