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jtag: retire jtag_get/set_end_state()
[openocd.git] / src / target / etb.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm.h"
25 #include "etm.h"
26 #include "etb.h"
27 #include "register.h"
28
29
30 static char* etb_reg_list[] =
31 {
32 "ETB_identification",
33 "ETB_ram_depth",
34 "ETB_ram_width",
35 "ETB_status",
36 "ETB_ram_data",
37 "ETB_ram_read_pointer",
38 "ETB_ram_write_pointer",
39 "ETB_trigger_counter",
40 "ETB_control",
41 };
42
43 static int etb_get_reg(struct reg *reg);
44
45 static int etb_set_instr(struct etb *etb, uint32_t new_instr)
46 {
47 struct jtag_tap *tap;
48
49 tap = etb->tap;
50 if (tap == NULL)
51 return ERROR_FAIL;
52
53 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
54 {
55 struct scan_field field;
56
57 field.num_bits = tap->ir_length;
58 field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
59 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
60
61 field.in_value = NULL;
62
63 jtag_add_ir_scan(tap, &field, TAP_IDLE);
64
65 free(field.out_value);
66 }
67
68 return ERROR_OK;
69 }
70
71 static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
72 {
73 if (etb->cur_scan_chain != new_scan_chain)
74 {
75 struct scan_field field;
76
77 field.num_bits = 5;
78 field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
79 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
80
81 field.in_value = NULL;
82
83 /* select INTEST instruction */
84 etb_set_instr(etb, 0x2);
85 jtag_add_dr_scan(etb->tap, 1, &field, TAP_IDLE);
86
87 etb->cur_scan_chain = new_scan_chain;
88
89 free(field.out_value);
90 }
91
92 return ERROR_OK;
93 }
94
95 static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *);
96 static int etb_set_reg_w_exec(struct reg *, uint8_t *);
97
98 static int etb_read_reg(struct reg *reg)
99 {
100 return etb_read_reg_w_check(reg, NULL, NULL);
101 }
102
103 static int etb_get_reg(struct reg *reg)
104 {
105 int retval;
106
107 if ((retval = etb_read_reg(reg)) != ERROR_OK)
108 {
109 LOG_ERROR("BUG: error scheduling ETB register read");
110 return retval;
111 }
112
113 if ((retval = jtag_execute_queue()) != ERROR_OK)
114 {
115 LOG_ERROR("ETB register read failed");
116 return retval;
117 }
118
119 return ERROR_OK;
120 }
121
122 static const struct reg_arch_type etb_reg_type = {
123 .get = etb_get_reg,
124 .set = etb_set_reg_w_exec,
125 };
126
127 struct reg_cache* etb_build_reg_cache(struct etb *etb)
128 {
129 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
130 struct reg *reg_list = NULL;
131 struct etb_reg *arch_info = NULL;
132 int num_regs = 9;
133 int i;
134
135 /* the actual registers are kept in two arrays */
136 reg_list = calloc(num_regs, sizeof(struct reg));
137 arch_info = calloc(num_regs, sizeof(struct etb_reg));
138
139 /* fill in values for the reg cache */
140 reg_cache->name = "etb registers";
141 reg_cache->next = NULL;
142 reg_cache->reg_list = reg_list;
143 reg_cache->num_regs = num_regs;
144
145 /* set up registers */
146 for (i = 0; i < num_regs; i++)
147 {
148 reg_list[i].name = etb_reg_list[i];
149 reg_list[i].size = 32;
150 reg_list[i].dirty = 0;
151 reg_list[i].valid = 0;
152 reg_list[i].value = calloc(1, 4);
153 reg_list[i].arch_info = &arch_info[i];
154 reg_list[i].type = &etb_reg_type;
155 reg_list[i].size = 32;
156 arch_info[i].addr = i;
157 arch_info[i].etb = etb;
158 }
159
160 return reg_cache;
161 }
162
163 static void etb_getbuf(jtag_callback_data_t arg)
164 {
165 uint8_t *in = (uint8_t *)arg;
166
167 *((uint32_t *)in) = buf_get_u32(in, 0, 32);
168 }
169
170
171 static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
172 {
173 struct scan_field fields[3];
174 int i;
175
176 etb_scann(etb, 0x0);
177 etb_set_instr(etb, 0xc);
178
179 fields[0].num_bits = 32;
180 fields[0].out_value = NULL;
181 fields[0].in_value = NULL;
182
183 fields[1].num_bits = 7;
184 fields[1].out_value = malloc(1);
185 buf_set_u32(fields[1].out_value, 0, 7, 4);
186 fields[1].in_value = NULL;
187
188 fields[2].num_bits = 1;
189 fields[2].out_value = malloc(1);
190 buf_set_u32(fields[2].out_value, 0, 1, 0);
191 fields[2].in_value = NULL;
192
193 jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
194
195 for (i = 0; i < num_frames; i++)
196 {
197 /* ensure nR/W reamins set to read */
198 buf_set_u32(fields[2].out_value, 0, 1, 0);
199
200 /* address remains set to 0x4 (RAM data) until we read the last frame */
201 if (i < num_frames - 1)
202 buf_set_u32(fields[1].out_value, 0, 7, 4);
203 else
204 buf_set_u32(fields[1].out_value, 0, 7, 0);
205
206 fields[0].in_value = (uint8_t *)(data + i);
207 jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
208
209 jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
210 }
211
212 jtag_execute_queue();
213
214 free(fields[1].out_value);
215 free(fields[2].out_value);
216
217 return ERROR_OK;
218 }
219
220 static int etb_read_reg_w_check(struct reg *reg,
221 uint8_t* check_value, uint8_t* check_mask)
222 {
223 struct etb_reg *etb_reg = reg->arch_info;
224 uint8_t reg_addr = etb_reg->addr & 0x7f;
225 struct scan_field fields[3];
226
227 LOG_DEBUG("%i", (int)(etb_reg->addr));
228
229 etb_scann(etb_reg->etb, 0x0);
230 etb_set_instr(etb_reg->etb, 0xc);
231
232 fields[0].num_bits = 32;
233 fields[0].out_value = reg->value;
234 fields[0].in_value = NULL;
235 fields[0].check_value = NULL;
236 fields[0].check_mask = NULL;
237
238 fields[1].num_bits = 7;
239 fields[1].out_value = malloc(1);
240 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
241 fields[1].in_value = NULL;
242 fields[1].check_value = NULL;
243 fields[1].check_mask = NULL;
244
245 fields[2].num_bits = 1;
246 fields[2].out_value = malloc(1);
247 buf_set_u32(fields[2].out_value, 0, 1, 0);
248 fields[2].in_value = NULL;
249 fields[2].check_value = NULL;
250 fields[2].check_mask = NULL;
251
252 jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE);
253
254 /* read the identification register in the second run, to make sure we
255 * don't read the ETB data register twice, skipping every second entry
256 */
257 buf_set_u32(fields[1].out_value, 0, 7, 0x0);
258 fields[0].in_value = reg->value;
259 fields[0].check_value = check_value;
260 fields[0].check_mask = check_mask;
261
262 jtag_add_dr_scan_check(etb_reg->etb->tap, 3, fields, TAP_IDLE);
263
264 free(fields[1].out_value);
265 free(fields[2].out_value);
266
267 return ERROR_OK;
268 }
269
270 static int etb_write_reg(struct reg *, uint32_t);
271
272 static int etb_set_reg(struct reg *reg, uint32_t value)
273 {
274 int retval;
275
276 if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
277 {
278 LOG_ERROR("BUG: error scheduling ETB register write");
279 return retval;
280 }
281
282 buf_set_u32(reg->value, 0, reg->size, value);
283 reg->valid = 1;
284 reg->dirty = 0;
285
286 return ERROR_OK;
287 }
288
289 static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf)
290 {
291 int retval;
292
293 etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
294
295 if ((retval = jtag_execute_queue()) != ERROR_OK)
296 {
297 LOG_ERROR("ETB: register write failed");
298 return retval;
299 }
300 return ERROR_OK;
301 }
302
303 static int etb_write_reg(struct reg *reg, uint32_t value)
304 {
305 struct etb_reg *etb_reg = reg->arch_info;
306 uint8_t reg_addr = etb_reg->addr & 0x7f;
307 struct scan_field fields[3];
308
309 LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
310
311 etb_scann(etb_reg->etb, 0x0);
312 etb_set_instr(etb_reg->etb, 0xc);
313
314 fields[0].num_bits = 32;
315 fields[0].out_value = malloc(4);
316 buf_set_u32(fields[0].out_value, 0, 32, value);
317 fields[0].in_value = NULL;
318
319 fields[1].num_bits = 7;
320 fields[1].out_value = malloc(1);
321 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
322 fields[1].in_value = NULL;
323
324 fields[2].num_bits = 1;
325 fields[2].out_value = malloc(1);
326 buf_set_u32(fields[2].out_value, 0, 1, 1);
327
328 fields[2].in_value = NULL;
329
330 free(fields[0].out_value);
331 free(fields[1].out_value);
332 free(fields[2].out_value);
333
334 return ERROR_OK;
335 }
336
337 COMMAND_HANDLER(handle_etb_config_command)
338 {
339 struct target *target;
340 struct jtag_tap *tap;
341 struct arm *arm;
342
343 if (CMD_ARGC != 2)
344 {
345 return ERROR_COMMAND_SYNTAX_ERROR;
346 }
347
348 target = get_target(CMD_ARGV[0]);
349
350 if (!target)
351 {
352 LOG_ERROR("ETB: target '%s' not defined", CMD_ARGV[0]);
353 return ERROR_FAIL;
354 }
355
356 arm = target_to_arm(target);
357 if (!is_arm(arm))
358 {
359 command_print(CMD_CTX, "ETB: '%s' isn't an ARM", CMD_ARGV[0]);
360 return ERROR_FAIL;
361 }
362
363 tap = jtag_tap_by_string(CMD_ARGV[1]);
364 if (tap == NULL)
365 {
366 command_print(CMD_CTX, "ETB: TAP %s does not exist", CMD_ARGV[1]);
367 return ERROR_FAIL;
368 }
369
370 if (arm->etm)
371 {
372 struct etb *etb = malloc(sizeof(struct etb));
373
374 arm->etm->capture_driver_priv = etb;
375
376 etb->tap = tap;
377 etb->cur_scan_chain = 0xffffffff;
378 etb->reg_cache = NULL;
379 etb->ram_width = 0;
380 etb->ram_depth = 0;
381 }
382 else
383 {
384 LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
385 return ERROR_FAIL;
386 }
387
388 return ERROR_OK;
389 }
390
391 COMMAND_HANDLER(handle_etb_trigger_percent_command)
392 {
393 struct target *target;
394 struct arm *arm;
395 struct etm_context *etm;
396 struct etb *etb;
397
398 target = get_current_target(CMD_CTX);
399 arm = target_to_arm(target);
400 if (!is_arm(arm))
401 {
402 command_print(CMD_CTX, "ETB: current target isn't an ARM");
403 return ERROR_FAIL;
404 }
405
406 etm = arm->etm;
407 if (!etm) {
408 command_print(CMD_CTX, "ETB: target has no ETM configured");
409 return ERROR_FAIL;
410 }
411 if (etm->capture_driver != &etb_capture_driver) {
412 command_print(CMD_CTX, "ETB: target not using ETB");
413 return ERROR_FAIL;
414 }
415 etb = arm->etm->capture_driver_priv;
416
417 if (CMD_ARGC > 0) {
418 uint32_t new_value;
419
420 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
421 if ((new_value < 2) || (new_value > 100))
422 command_print(CMD_CTX,
423 "valid percentages are 2%% to 100%%");
424 else
425 etb->trigger_percent = (unsigned) new_value;
426 }
427
428 command_print(CMD_CTX, "%d percent of tracebuffer fills after trigger",
429 etb->trigger_percent);
430
431 return ERROR_OK;
432 }
433
434 static const struct command_registration etb_config_command_handlers[] = {
435 {
436 /* NOTE: with ADIv5, ETBs are accessed using DAP operations,
437 * possibly over SWD, not through separate TAPs...
438 */
439 .name = "config",
440 .handler = handle_etb_config_command,
441 .mode = COMMAND_CONFIG,
442 .help = "Associate ETB with target and JTAG TAP.",
443 .usage = "target tap",
444 },
445 {
446 .name = "trigger_percent",
447 .handler = handle_etb_trigger_percent_command,
448 .mode = COMMAND_EXEC,
449 .help = "Set percent of trace buffer to be filled "
450 "after the trigger occurs (2..100).",
451 .usage = "[percent]",
452 },
453 COMMAND_REGISTRATION_DONE
454 };
455 static const struct command_registration etb_command_handlers[] = {
456 {
457 .name = "etb",
458 .mode = COMMAND_ANY,
459 .help = "Emebdded Trace Buffer command group",
460 .chain = etb_config_command_handlers,
461 },
462 COMMAND_REGISTRATION_DONE
463 };
464
465 static int etb_init(struct etm_context *etm_ctx)
466 {
467 struct etb *etb = etm_ctx->capture_driver_priv;
468
469 etb->etm_ctx = etm_ctx;
470
471 /* identify ETB RAM depth and width */
472 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
473 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
474 jtag_execute_queue();
475
476 etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
477 etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
478
479 etb->trigger_percent = 50;
480
481 return ERROR_OK;
482 }
483
484 static trace_status_t etb_status(struct etm_context *etm_ctx)
485 {
486 struct etb *etb = etm_ctx->capture_driver_priv;
487 struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
488 struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
489 trace_status_t retval = 0;
490 int etb_timeout = 100;
491
492 etb->etm_ctx = etm_ctx;
493
494 /* read control and status registers */
495 etb_read_reg(control);
496 etb_read_reg(status);
497 jtag_execute_queue();
498
499 /* See if it's (still) active */
500 retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE;
501
502 /* check Full bit to identify wraparound/overflow */
503 if (buf_get_u32(status->value, 0, 1) == 1)
504 retval |= TRACE_OVERFLOWED;
505
506 /* check Triggered bit to identify trigger condition */
507 if (buf_get_u32(status->value, 1, 1) == 1)
508 retval |= TRACE_TRIGGERED;
509
510 /* check AcqComp to see if trigger counter dropped to zero */
511 if (buf_get_u32(status->value, 2, 1) == 1) {
512 /* wait for DFEmpty */
513 while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0)
514 etb_get_reg(status);
515
516 if (etb_timeout == 0)
517 LOG_ERROR("ETB: DFEmpty won't go high, status 0x%02x",
518 (unsigned) buf_get_u32(status->value, 0, 4));
519
520 if (!(etm_ctx->capture_status & TRACE_TRIGGERED))
521 LOG_WARNING("ETB: trace complete without triggering?");
522
523 retval |= TRACE_COMPLETED;
524 }
525
526 /* NOTE: using a trigger is optional; and at least ETB11 has a mode
527 * where it can ignore the trigger counter.
528 */
529
530 /* update recorded state */
531 etm_ctx->capture_status = retval;
532
533 return retval;
534 }
535
536 static int etb_read_trace(struct etm_context *etm_ctx)
537 {
538 struct etb *etb = etm_ctx->capture_driver_priv;
539 int first_frame = 0;
540 int num_frames = etb->ram_depth;
541 uint32_t *trace_data = NULL;
542 int i, j;
543
544 etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
545 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
546 jtag_execute_queue();
547
548 /* check if we overflowed, and adjust first frame of the trace accordingly
549 * if we didn't overflow, read only up to the frame that would be written next,
550 * i.e. don't read invalid entries
551 */
552 if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
553 {
554 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
555 }
556 else
557 {
558 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
559 }
560
561 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
562
563 /* read data into temporary array for unpacking */
564 trace_data = malloc(sizeof(uint32_t) * num_frames);
565 etb_read_ram(etb, trace_data, num_frames);
566
567 if (etm_ctx->trace_depth > 0)
568 {
569 free(etm_ctx->trace_data);
570 }
571
572 if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
573 etm_ctx->trace_depth = num_frames * 3;
574 else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
575 etm_ctx->trace_depth = num_frames * 2;
576 else
577 etm_ctx->trace_depth = num_frames;
578
579 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
580
581 for (i = 0, j = 0; i < num_frames; i++)
582 {
583 if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
584 {
585 /* trace word j */
586 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
587 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
588 etm_ctx->trace_data[j].flags = 0;
589 if ((trace_data[i] & 0x80) >> 7)
590 {
591 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
592 }
593 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
594 {
595 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
596 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
597 }
598
599 /* trace word j + 1 */
600 etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
601 etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
602 etm_ctx->trace_data[j + 1].flags = 0;
603 if ((trace_data[i] & 0x8000) >> 15)
604 {
605 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
606 }
607 if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
608 {
609 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
610 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
611 }
612
613 /* trace word j + 2 */
614 etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
615 etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
616 etm_ctx->trace_data[j + 2].flags = 0;
617 if ((trace_data[i] & 0x800000) >> 23)
618 {
619 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
620 }
621 if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
622 {
623 etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
624 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
625 }
626
627 j += 3;
628 }
629 else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
630 {
631 /* trace word j */
632 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
633 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
634 etm_ctx->trace_data[j].flags = 0;
635 if ((trace_data[i] & 0x800) >> 11)
636 {
637 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
638 }
639 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
640 {
641 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
642 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
643 }
644
645 /* trace word j + 1 */
646 etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
647 etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
648 etm_ctx->trace_data[j + 1].flags = 0;
649 if ((trace_data[i] & 0x800000) >> 23)
650 {
651 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
652 }
653 if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
654 {
655 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
656 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
657 }
658
659 j += 2;
660 }
661 else
662 {
663 /* trace word j */
664 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
665 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
666 etm_ctx->trace_data[j].flags = 0;
667 if ((trace_data[i] & 0x80000) >> 19)
668 {
669 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
670 }
671 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
672 {
673 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
674 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
675 }
676
677 j += 1;
678 }
679 }
680
681 free(trace_data);
682
683 return ERROR_OK;
684 }
685
686 static int etb_start_capture(struct etm_context *etm_ctx)
687 {
688 struct etb *etb = etm_ctx->capture_driver_priv;
689 uint32_t etb_ctrl_value = 0x1;
690 uint32_t trigger_count;
691
692 if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
693 {
694 if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
695 {
696 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
697 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
698 }
699 etb_ctrl_value |= 0x2;
700 }
701
702 if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
703 LOG_ERROR("ETB: can't run in multiplexed mode");
704 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
705 }
706
707 trigger_count = (etb->ram_depth * etb->trigger_percent) / 100;
708
709 etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
710 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
711 etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
712 jtag_execute_queue();
713
714 /* we're starting a new trace, initialize capture status */
715 etm_ctx->capture_status = TRACE_RUNNING;
716
717 return ERROR_OK;
718 }
719
720 static int etb_stop_capture(struct etm_context *etm_ctx)
721 {
722 struct etb *etb = etm_ctx->capture_driver_priv;
723 struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
724
725 etb_write_reg(etb_ctrl_reg, 0x0);
726 jtag_execute_queue();
727
728 /* trace stopped, just clear running flag, but preserve others */
729 etm_ctx->capture_status &= ~TRACE_RUNNING;
730
731 return ERROR_OK;
732 }
733
734 struct etm_capture_driver etb_capture_driver =
735 {
736 .name = "etb",
737 .commands = etb_command_handlers,
738 .init = etb_init,
739 .status = etb_status,
740 .start_capture = etb_start_capture,
741 .stop_capture = etb_stop_capture,
742 .read_trace = etb_read_trace,
743 };
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