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Audit and eliminate redundant #include directives in other target files.
[openocd.git] / src / target / etb.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm7_9_common.h"
25 #include "etb.h"
26
27
28 static char* etb_reg_list[] =
29 {
30 "ETB_identification",
31 "ETB_ram_depth",
32 "ETB_ram_width",
33 "ETB_status",
34 "ETB_ram_data",
35 "ETB_ram_read_pointer",
36 "ETB_ram_write_pointer",
37 "ETB_trigger_counter",
38 "ETB_control",
39 };
40
41 static int etb_reg_arch_type = -1;
42
43 static int etb_get_reg(reg_t *reg);
44
45 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46
47 static int etb_set_instr(etb_t *etb, u32 new_instr)
48 {
49 jtag_tap_t *tap;
50
51 tap = etb->tap;
52 if (tap==NULL)
53 return ERROR_FAIL;
54
55 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
56 {
57 scan_field_t field;
58
59 field.tap = tap;
60 field.num_bits = tap->ir_length;
61 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
62 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
63
64 field.in_value = NULL;
65
66 jtag_add_ir_scan(1, &field, TAP_INVALID);
67
68 free(field.out_value);
69 }
70
71 return ERROR_OK;
72 }
73
74 static int etb_scann(etb_t *etb, u32 new_scan_chain)
75 {
76 if (etb->cur_scan_chain != new_scan_chain)
77 {
78 scan_field_t field;
79
80 field.tap = etb->tap;
81 field.num_bits = 5;
82 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
83 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
84
85 field.in_value = NULL;
86
87 /* select INTEST instruction */
88 etb_set_instr(etb, 0x2);
89 jtag_add_dr_scan(1, &field, TAP_INVALID);
90
91 etb->cur_scan_chain = new_scan_chain;
92
93 free(field.out_value);
94 }
95
96 return ERROR_OK;
97 }
98
99 reg_cache_t* etb_build_reg_cache(etb_t *etb)
100 {
101 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
102 reg_t *reg_list = NULL;
103 etb_reg_t *arch_info = NULL;
104 int num_regs = 9;
105 int i;
106
107 /* register a register arch-type for etm registers only once */
108 if (etb_reg_arch_type == -1)
109 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
110
111 /* the actual registers are kept in two arrays */
112 reg_list = calloc(num_regs, sizeof(reg_t));
113 arch_info = calloc(num_regs, sizeof(etb_reg_t));
114
115 /* fill in values for the reg cache */
116 reg_cache->name = "etb registers";
117 reg_cache->next = NULL;
118 reg_cache->reg_list = reg_list;
119 reg_cache->num_regs = num_regs;
120
121 /* set up registers */
122 for (i = 0; i < num_regs; i++)
123 {
124 reg_list[i].name = etb_reg_list[i];
125 reg_list[i].size = 32;
126 reg_list[i].dirty = 0;
127 reg_list[i].valid = 0;
128 reg_list[i].bitfield_desc = NULL;
129 reg_list[i].num_bitfields = 0;
130 reg_list[i].value = calloc(1, 4);
131 reg_list[i].arch_info = &arch_info[i];
132 reg_list[i].arch_type = etb_reg_arch_type;
133 reg_list[i].size = 32;
134 arch_info[i].addr = i;
135 arch_info[i].etb = etb;
136 }
137
138 return reg_cache;
139 }
140
141 static int etb_get_reg(reg_t *reg)
142 {
143 int retval;
144
145 if ((retval = etb_read_reg(reg)) != ERROR_OK)
146 {
147 LOG_ERROR("BUG: error scheduling etm register read");
148 return retval;
149 }
150
151 if ((retval = jtag_execute_queue()) != ERROR_OK)
152 {
153 LOG_ERROR("register read failed");
154 return retval;
155 }
156
157 return ERROR_OK;
158 }
159
160 static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
161 {
162 scan_field_t fields[3];
163 int i;
164
165 jtag_add_end_state(TAP_IDLE);
166 etb_scann(etb, 0x0);
167 etb_set_instr(etb, 0xc);
168
169 fields[0].tap = etb->tap;
170 fields[0].num_bits = 32;
171 fields[0].out_value = NULL;
172 u8 tmp[4];
173 fields[0].in_value = tmp;
174
175 fields[1].tap = etb->tap;
176 fields[1].num_bits = 7;
177 fields[1].out_value = malloc(1);
178 buf_set_u32(fields[1].out_value, 0, 7, 4);
179 fields[1].in_value = NULL;
180
181 fields[2].tap = etb->tap;
182 fields[2].num_bits = 1;
183 fields[2].out_value = malloc(1);
184 buf_set_u32(fields[2].out_value, 0, 1, 0);
185 fields[2].in_value = NULL;
186
187 jtag_add_dr_scan(3, fields, TAP_INVALID);
188
189 for (i = 0; i < num_frames; i++)
190 {
191 /* ensure nR/W reamins set to read */
192 buf_set_u32(fields[2].out_value, 0, 1, 0);
193
194 /* address remains set to 0x4 (RAM data) until we read the last frame */
195 if (i < num_frames - 1)
196 buf_set_u32(fields[1].out_value, 0, 7, 4);
197 else
198 buf_set_u32(fields[1].out_value, 0, 7, 0);
199
200 jtag_add_dr_scan_now(3, fields, TAP_INVALID);
201
202 data[i]=buf_get_u32(tmp, 0, 32);
203 }
204
205 jtag_execute_queue();
206
207 free(fields[1].out_value);
208 free(fields[2].out_value);
209
210 return ERROR_OK;
211 }
212
213 int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
214 {
215 etb_reg_t *etb_reg = reg->arch_info;
216 u8 reg_addr = etb_reg->addr & 0x7f;
217 scan_field_t fields[3];
218
219 LOG_DEBUG("%i", etb_reg->addr);
220
221 jtag_add_end_state(TAP_IDLE);
222 etb_scann(etb_reg->etb, 0x0);
223 etb_set_instr(etb_reg->etb, 0xc);
224
225 fields[0].tap = etb_reg->etb->tap;
226 fields[0].num_bits = 32;
227 fields[0].out_value = reg->value;
228 fields[0].in_value = NULL;
229
230 fields[1].tap = etb_reg->etb->tap;
231 fields[1].num_bits = 7;
232 fields[1].out_value = malloc(1);
233 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
234 fields[1].in_value = NULL;
235
236 fields[2].tap = etb_reg->etb->tap;
237 fields[2].num_bits = 1;
238 fields[2].out_value = malloc(1);
239 buf_set_u32(fields[2].out_value, 0, 1, 0);
240 fields[2].in_value = NULL;
241
242 jtag_add_dr_scan(3, fields, TAP_INVALID);
243
244 /* read the identification register in the second run, to make sure we
245 * don't read the ETB data register twice, skipping every second entry
246 */
247 buf_set_u32(fields[1].out_value, 0, 7, 0x0);
248 fields[0].in_value = reg->value;
249
250 jtag_add_dr_scan(3, fields, TAP_INVALID);
251
252 jtag_check_value_mask(fields+0, check_value, check_mask);
253
254 free(fields[1].out_value);
255 free(fields[2].out_value);
256
257 return ERROR_OK;
258 }
259
260 int etb_read_reg(reg_t *reg)
261 {
262 return etb_read_reg_w_check(reg, NULL, NULL);
263 }
264
265 int etb_set_reg(reg_t *reg, u32 value)
266 {
267 int retval;
268
269 if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
270 {
271 LOG_ERROR("BUG: error scheduling etm register write");
272 return retval;
273 }
274
275 buf_set_u32(reg->value, 0, reg->size, value);
276 reg->valid = 1;
277 reg->dirty = 0;
278
279 return ERROR_OK;
280 }
281
282 int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
283 {
284 int retval;
285
286 etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
287
288 if ((retval = jtag_execute_queue()) != ERROR_OK)
289 {
290 LOG_ERROR("register write failed");
291 return retval;
292 }
293 return ERROR_OK;
294 }
295
296 int etb_write_reg(reg_t *reg, u32 value)
297 {
298 etb_reg_t *etb_reg = reg->arch_info;
299 u8 reg_addr = etb_reg->addr & 0x7f;
300 scan_field_t fields[3];
301
302 LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
303
304 jtag_add_end_state(TAP_IDLE);
305 etb_scann(etb_reg->etb, 0x0);
306 etb_set_instr(etb_reg->etb, 0xc);
307
308 fields[0].tap = etb_reg->etb->tap;
309 fields[0].num_bits = 32;
310 fields[0].out_value = malloc(4);
311 buf_set_u32(fields[0].out_value, 0, 32, value);
312 fields[0].in_value = NULL;
313
314 fields[1].tap = etb_reg->etb->tap;
315 fields[1].num_bits = 7;
316 fields[1].out_value = malloc(1);
317 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
318 fields[1].in_value = NULL;
319
320 fields[2].tap = etb_reg->etb->tap;
321 fields[2].num_bits = 1;
322 fields[2].out_value = malloc(1);
323 buf_set_u32(fields[2].out_value, 0, 1, 1);
324
325 fields[2].in_value = NULL;
326
327 free(fields[0].out_value);
328 free(fields[1].out_value);
329 free(fields[2].out_value);
330
331 return ERROR_OK;
332 }
333
334 int etb_store_reg(reg_t *reg)
335 {
336 return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
337 }
338
339 static int etb_register_commands(struct command_context_s *cmd_ctx)
340 {
341 command_t *etb_cmd;
342
343 etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
344
345 register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
346
347 return ERROR_OK;
348 }
349
350 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
351 {
352 target_t *target;
353 jtag_tap_t *tap;
354 armv4_5_common_t *armv4_5;
355 arm7_9_common_t *arm7_9;
356
357 if (argc != 2)
358 {
359 return ERROR_COMMAND_SYNTAX_ERROR;
360 }
361
362 target = get_target_by_num(strtoul(args[0], NULL, 0));
363
364 if (!target)
365 {
366 LOG_ERROR("target number '%s' not defined", args[0]);
367 return ERROR_FAIL;
368 }
369
370 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
371 {
372 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
373 return ERROR_FAIL;
374 }
375
376 tap = jtag_TapByString( args[1] );
377 if (tap == NULL)
378 {
379 command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
380 return ERROR_FAIL;
381 }
382
383 if (arm7_9->etm_ctx)
384 {
385 etb_t *etb = malloc(sizeof(etb_t));
386
387 arm7_9->etm_ctx->capture_driver_priv = etb;
388
389 etb->tap = tap;
390 etb->cur_scan_chain = 0xffffffff;
391 etb->reg_cache = NULL;
392 etb->ram_width = 0;
393 etb->ram_depth = 0;
394 }
395 else
396 {
397 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
398 return ERROR_FAIL;
399 }
400
401 return ERROR_OK;
402 }
403
404 static int etb_init(etm_context_t *etm_ctx)
405 {
406 etb_t *etb = etm_ctx->capture_driver_priv;
407
408 etb->etm_ctx = etm_ctx;
409
410 /* identify ETB RAM depth and width */
411 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
412 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
413 jtag_execute_queue();
414
415 etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
416 etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
417
418 return ERROR_OK;
419 }
420
421 static trace_status_t etb_status(etm_context_t *etm_ctx)
422 {
423 etb_t *etb = etm_ctx->capture_driver_priv;
424
425 etb->etm_ctx = etm_ctx;
426
427 /* if tracing is currently idle, return this information */
428 if (etm_ctx->capture_status == TRACE_IDLE)
429 {
430 return etm_ctx->capture_status;
431 }
432 else if (etm_ctx->capture_status & TRACE_RUNNING)
433 {
434 reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
435 int etb_timeout = 100;
436
437 /* trace is running, check the ETB status flags */
438 etb_get_reg(etb_status_reg);
439
440 /* check Full bit to identify an overflow */
441 if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
442 etm_ctx->capture_status |= TRACE_OVERFLOWED;
443
444 /* check Triggered bit to identify trigger condition */
445 if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
446 etm_ctx->capture_status |= TRACE_TRIGGERED;
447
448 /* check AcqComp to identify trace completion */
449 if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
450 {
451 while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
452 {
453 /* wait for data formatter idle */
454 etb_get_reg(etb_status_reg);
455 }
456
457 if (etb_timeout == 0)
458 {
459 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
460 buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
461 }
462
463 if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
464 {
465 LOG_ERROR("trace completed, but no trigger condition detected");
466 }
467
468 etm_ctx->capture_status &= ~TRACE_RUNNING;
469 etm_ctx->capture_status |= TRACE_COMPLETED;
470 }
471 }
472
473 return etm_ctx->capture_status;
474 }
475
476 static int etb_read_trace(etm_context_t *etm_ctx)
477 {
478 etb_t *etb = etm_ctx->capture_driver_priv;
479 int first_frame = 0;
480 int num_frames = etb->ram_depth;
481 u32 *trace_data = NULL;
482 int i, j;
483
484 etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
485 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
486 jtag_execute_queue();
487
488 /* check if we overflowed, and adjust first frame of the trace accordingly
489 * if we didn't overflow, read only up to the frame that would be written next,
490 * i.e. don't read invalid entries
491 */
492 if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
493 {
494 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
495 }
496 else
497 {
498 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
499 }
500
501 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
502
503 /* read data into temporary array for unpacking */
504 trace_data = malloc(sizeof(u32) * num_frames);
505 etb_read_ram(etb, trace_data, num_frames);
506
507 if (etm_ctx->trace_depth > 0)
508 {
509 free(etm_ctx->trace_data);
510 }
511
512 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
513 etm_ctx->trace_depth = num_frames * 3;
514 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
515 etm_ctx->trace_depth = num_frames * 2;
516 else
517 etm_ctx->trace_depth = num_frames;
518
519 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
520
521 for (i = 0, j = 0; i < num_frames; i++)
522 {
523 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
524 {
525 /* trace word j */
526 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
527 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
528 etm_ctx->trace_data[j].flags = 0;
529 if ((trace_data[i] & 0x80) >> 7)
530 {
531 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
532 }
533 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
534 {
535 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
536 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
537 }
538
539 /* trace word j+1 */
540 etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
541 etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
542 etm_ctx->trace_data[j+1].flags = 0;
543 if ((trace_data[i] & 0x8000) >> 15)
544 {
545 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
546 }
547 if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
548 {
549 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
550 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
551 }
552
553 /* trace word j+2 */
554 etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
555 etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
556 etm_ctx->trace_data[j+2].flags = 0;
557 if ((trace_data[i] & 0x800000) >> 23)
558 {
559 etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
560 }
561 if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
562 {
563 etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
564 etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
565 }
566
567 j += 3;
568 }
569 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
570 {
571 /* trace word j */
572 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
573 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
574 etm_ctx->trace_data[j].flags = 0;
575 if ((trace_data[i] & 0x800) >> 11)
576 {
577 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
578 }
579 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
580 {
581 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
582 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
583 }
584
585 /* trace word j+1 */
586 etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
587 etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
588 etm_ctx->trace_data[j+1].flags = 0;
589 if ((trace_data[i] & 0x800000) >> 23)
590 {
591 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
592 }
593 if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
594 {
595 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
596 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
597 }
598
599 j += 2;
600 }
601 else
602 {
603 /* trace word j */
604 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
605 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
606 etm_ctx->trace_data[j].flags = 0;
607 if ((trace_data[i] & 0x80000) >> 19)
608 {
609 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
610 }
611 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
612 {
613 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
614 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
615 }
616
617 j += 1;
618 }
619 }
620
621 free(trace_data);
622
623 return ERROR_OK;
624 }
625
626 static int etb_start_capture(etm_context_t *etm_ctx)
627 {
628 etb_t *etb = etm_ctx->capture_driver_priv;
629 u32 etb_ctrl_value = 0x1;
630 u32 trigger_count;
631
632 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
633 {
634 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
635 {
636 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
637 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
638 }
639 etb_ctrl_value |= 0x2;
640 }
641
642 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
643 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
644
645 trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
646
647 etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
648 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
649 etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
650 jtag_execute_queue();
651
652 /* we're starting a new trace, initialize capture status */
653 etm_ctx->capture_status = TRACE_RUNNING;
654
655 return ERROR_OK;
656 }
657
658 static int etb_stop_capture(etm_context_t *etm_ctx)
659 {
660 etb_t *etb = etm_ctx->capture_driver_priv;
661 reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
662
663 etb_write_reg(etb_ctrl_reg, 0x0);
664 jtag_execute_queue();
665
666 /* trace stopped, just clear running flag, but preserve others */
667 etm_ctx->capture_status &= ~TRACE_RUNNING;
668
669 return ERROR_OK;
670 }
671
672 etm_capture_driver_t etb_capture_driver =
673 {
674 .name = "etb",
675 .register_commands = etb_register_commands,
676 .init = etb_init,
677 .status = etb_status,
678 .start_capture = etb_start_capture,
679 .stop_capture = etb_stop_capture,
680 .read_trace = etb_read_trace,
681 };
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