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05d970d53d699a9bda62953c7edfdaa81857eeff
[openocd.git] / src / target / etb.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include <string.h>
25
26 #include "arm7_9_common.h"
27 #include "etb.h"
28 #include "etm.h"
29
30 #include "log.h"
31 #include "types.h"
32 #include "binarybuffer.h"
33 #include "target.h"
34 #include "register.h"
35 #include "jtag.h"
36
37 #include <stdlib.h>
38
39 char* etb_reg_list[] =
40 {
41 "ETB_identification",
42 "ETB_ram_depth",
43 "ETB_ram_width",
44 "ETB_status",
45 "ETB_ram_data",
46 "ETB_ram_read_pointer",
47 "ETB_ram_write_pointer",
48 "ETB_trigger_counter",
49 "ETB_control",
50 };
51
52 int etb_reg_arch_type = -1;
53
54 int etb_get_reg(reg_t *reg);
55 int etb_set_reg(reg_t *reg, u32 value);
56 int etb_set_reg_w_exec(reg_t *reg, u8 *buf);
57
58 int etb_write_reg(reg_t *reg, u32 value);
59 int etb_read_reg(reg_t *reg);
60
61 int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
62
63 int etb_set_instr(etb_t *etb, u32 new_instr)
64 {
65 jtag_device_t *device = jtag_get_device(etb->chain_pos);
66 if (device==NULL)
67 return ERROR_FAIL;
68
69 if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
70 {
71 scan_field_t field;
72
73 field.device = etb->chain_pos;
74 field.num_bits = device->ir_length;
75 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
76 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
77 field.out_mask = NULL;
78 field.in_value = NULL;
79 field.in_check_value = NULL;
80 field.in_check_mask = NULL;
81 field.in_handler = NULL;
82 field.in_handler_priv = NULL;
83
84 jtag_add_ir_scan(1, &field, -1);
85
86 free(field.out_value);
87 }
88
89 return ERROR_OK;
90 }
91
92 int etb_scann(etb_t *etb, u32 new_scan_chain)
93 {
94 if(etb->cur_scan_chain != new_scan_chain)
95 {
96 scan_field_t field;
97
98 field.device = etb->chain_pos;
99 field.num_bits = 5;
100 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
101 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
102 field.out_mask = NULL;
103 field.in_value = NULL;
104 field.in_check_value = NULL;
105 field.in_check_mask = NULL;
106 field.in_handler = NULL;
107 field.in_handler_priv = NULL;
108
109 /* select INTEST instruction */
110 etb_set_instr(etb, 0x2);
111 jtag_add_dr_scan(1, &field, -1);
112
113 etb->cur_scan_chain = new_scan_chain;
114
115 free(field.out_value);
116 }
117
118 return ERROR_OK;
119 }
120
121 reg_cache_t* etb_build_reg_cache(etb_t *etb)
122 {
123 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
124 reg_t *reg_list = NULL;
125 etb_reg_t *arch_info = NULL;
126 int num_regs = 9;
127 int i;
128
129 /* register a register arch-type for etm registers only once */
130 if (etb_reg_arch_type == -1)
131 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
132
133 /* the actual registers are kept in two arrays */
134 reg_list = calloc(num_regs, sizeof(reg_t));
135 arch_info = calloc(num_regs, sizeof(etb_reg_t));
136
137 /* fill in values for the reg cache */
138 reg_cache->name = "etb registers";
139 reg_cache->next = NULL;
140 reg_cache->reg_list = reg_list;
141 reg_cache->num_regs = num_regs;
142
143 /* set up registers */
144 for (i = 0; i < num_regs; i++)
145 {
146 reg_list[i].name = etb_reg_list[i];
147 reg_list[i].size = 32;
148 reg_list[i].dirty = 0;
149 reg_list[i].valid = 0;
150 reg_list[i].bitfield_desc = NULL;
151 reg_list[i].num_bitfields = 0;
152 reg_list[i].value = calloc(1, 4);
153 reg_list[i].arch_info = &arch_info[i];
154 reg_list[i].arch_type = etb_reg_arch_type;
155 reg_list[i].size = 32;
156 arch_info[i].addr = i;
157 arch_info[i].etb = etb;
158 }
159
160 return reg_cache;
161 }
162
163 int etb_get_reg(reg_t *reg)
164 {
165 int retval;
166 if ((retval = etb_read_reg(reg)) != ERROR_OK)
167 {
168 LOG_ERROR("BUG: error scheduling etm register read");
169 return retval;
170 }
171
172 if ((retval = jtag_execute_queue()) != ERROR_OK)
173 {
174 LOG_ERROR("register read failed");
175 return retval;
176 }
177
178 return ERROR_OK;
179 }
180
181 int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
182 {
183 scan_field_t fields[3];
184 int i;
185
186 jtag_add_end_state(TAP_RTI);
187 etb_scann(etb, 0x0);
188 etb_set_instr(etb, 0xc);
189
190 fields[0].device = etb->chain_pos;
191 fields[0].num_bits = 32;
192 fields[0].out_value = NULL;
193 fields[0].out_mask = NULL;
194 fields[0].in_value = NULL;
195 fields[0].in_check_value = NULL;
196 fields[0].in_check_mask = NULL;
197 fields[0].in_handler = NULL;
198 fields[0].in_handler_priv = NULL;
199
200 fields[1].device = etb->chain_pos;
201 fields[1].num_bits = 7;
202 fields[1].out_value = malloc(1);
203 buf_set_u32(fields[1].out_value, 0, 7, 4);
204 fields[1].out_mask = NULL;
205 fields[1].in_value = NULL;
206 fields[1].in_check_value = NULL;
207 fields[1].in_check_mask = NULL;
208 fields[1].in_handler = NULL;
209 fields[1].in_handler_priv = NULL;
210
211 fields[2].device = etb->chain_pos;
212 fields[2].num_bits = 1;
213 fields[2].out_value = malloc(1);
214 buf_set_u32(fields[2].out_value, 0, 1, 0);
215 fields[2].out_mask = NULL;
216 fields[2].in_value = NULL;
217 fields[2].in_check_value = NULL;
218 fields[2].in_check_mask = NULL;
219 fields[2].in_handler = NULL;
220 fields[2].in_handler_priv = NULL;
221
222 jtag_add_dr_scan(3, fields, -1);
223
224 fields[0].in_handler = buf_to_u32_handler;
225
226 for (i = 0; i < num_frames; i++)
227 {
228 /* ensure nR/W reamins set to read */
229 buf_set_u32(fields[2].out_value, 0, 1, 0);
230
231 /* address remains set to 0x4 (RAM data) until we read the last frame */
232 if (i < num_frames - 1)
233 buf_set_u32(fields[1].out_value, 0, 7, 4);
234 else
235 buf_set_u32(fields[1].out_value, 0, 7, 0);
236
237 fields[0].in_handler_priv = &data[i];
238 jtag_add_dr_scan(3, fields, -1);
239 }
240
241 jtag_execute_queue();
242
243 free(fields[1].out_value);
244 free(fields[2].out_value);
245
246 return ERROR_OK;
247 }
248
249 int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
250 {
251 etb_reg_t *etb_reg = reg->arch_info;
252 u8 reg_addr = etb_reg->addr & 0x7f;
253 scan_field_t fields[3];
254
255 LOG_DEBUG("%i", etb_reg->addr);
256
257 jtag_add_end_state(TAP_RTI);
258 etb_scann(etb_reg->etb, 0x0);
259 etb_set_instr(etb_reg->etb, 0xc);
260
261 fields[0].device = etb_reg->etb->chain_pos;
262 fields[0].num_bits = 32;
263 fields[0].out_value = reg->value;
264 fields[0].out_mask = NULL;
265 fields[0].in_value = NULL;
266 fields[0].in_check_value = NULL;
267 fields[0].in_check_mask = NULL;
268 fields[0].in_handler = NULL;
269 fields[0].in_handler_priv = NULL;
270
271 fields[1].device = etb_reg->etb->chain_pos;
272 fields[1].num_bits = 7;
273 fields[1].out_value = malloc(1);
274 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
275 fields[1].out_mask = NULL;
276 fields[1].in_value = NULL;
277 fields[1].in_check_value = NULL;
278 fields[1].in_check_mask = NULL;
279 fields[1].in_handler = NULL;
280 fields[1].in_handler_priv = NULL;
281
282 fields[2].device = etb_reg->etb->chain_pos;
283 fields[2].num_bits = 1;
284 fields[2].out_value = malloc(1);
285 buf_set_u32(fields[2].out_value, 0, 1, 0);
286 fields[2].out_mask = NULL;
287 fields[2].in_value = NULL;
288 fields[2].in_check_value = NULL;
289 fields[2].in_check_mask = NULL;
290 fields[2].in_handler = NULL;
291 fields[2].in_handler_priv = NULL;
292
293 jtag_add_dr_scan(3, fields, -1);
294
295 /* read the identification register in the second run, to make sure we
296 * don't read the ETB data register twice, skipping every second entry
297 */
298 buf_set_u32(fields[1].out_value, 0, 7, 0x0);
299 fields[0].in_value = reg->value;
300
301 jtag_set_check_value(fields+0, check_value, check_mask, NULL);
302
303 jtag_add_dr_scan(3, fields, -1);
304
305 free(fields[1].out_value);
306 free(fields[2].out_value);
307
308 return ERROR_OK;
309 }
310
311 int etb_read_reg(reg_t *reg)
312 {
313 return etb_read_reg_w_check(reg, NULL, NULL);
314 }
315
316 int etb_set_reg(reg_t *reg, u32 value)
317 {
318 int retval;
319 if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
320 {
321 LOG_ERROR("BUG: error scheduling etm register write");
322 return retval;
323 }
324
325 buf_set_u32(reg->value, 0, reg->size, value);
326 reg->valid = 1;
327 reg->dirty = 0;
328
329 return ERROR_OK;
330 }
331
332 int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
333 {
334 int retval;
335 etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
336
337 if ((retval = jtag_execute_queue()) != ERROR_OK)
338 {
339 LOG_ERROR("register write failed");
340 return retval;
341 }
342 return ERROR_OK;
343 }
344
345 int etb_write_reg(reg_t *reg, u32 value)
346 {
347 etb_reg_t *etb_reg = reg->arch_info;
348 u8 reg_addr = etb_reg->addr & 0x7f;
349 scan_field_t fields[3];
350
351 LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
352
353 jtag_add_end_state(TAP_RTI);
354 etb_scann(etb_reg->etb, 0x0);
355 etb_set_instr(etb_reg->etb, 0xc);
356
357 fields[0].device = etb_reg->etb->chain_pos;
358 fields[0].num_bits = 32;
359 fields[0].out_value = malloc(4);
360 buf_set_u32(fields[0].out_value, 0, 32, value);
361 fields[0].out_mask = NULL;
362 fields[0].in_value = NULL;
363 fields[0].in_check_value = NULL;
364 fields[0].in_check_mask = NULL;
365 fields[0].in_handler = NULL;
366 fields[0].in_handler_priv = NULL;
367
368 fields[1].device = etb_reg->etb->chain_pos;
369 fields[1].num_bits = 7;
370 fields[1].out_value = malloc(1);
371 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
372 fields[1].out_mask = NULL;
373 fields[1].in_value = NULL;
374 fields[1].in_check_value = NULL;
375 fields[1].in_check_mask = NULL;
376 fields[1].in_handler = NULL;
377 fields[1].in_handler_priv = NULL;
378
379 fields[2].device = etb_reg->etb->chain_pos;
380 fields[2].num_bits = 1;
381 fields[2].out_value = malloc(1);
382 buf_set_u32(fields[2].out_value, 0, 1, 1);
383 fields[2].out_mask = NULL;
384 fields[2].in_value = NULL;
385 fields[2].in_check_value = NULL;
386 fields[2].in_check_mask = NULL;
387 fields[2].in_handler = NULL;
388 fields[2].in_handler_priv = NULL;
389
390 jtag_add_dr_scan(3, fields, -1);
391
392 free(fields[0].out_value);
393 free(fields[1].out_value);
394 free(fields[2].out_value);
395
396 return ERROR_OK;
397 }
398
399 int etb_store_reg(reg_t *reg)
400 {
401 return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
402 }
403
404 int etb_register_commands(struct command_context_s *cmd_ctx)
405 {
406 command_t *etb_cmd;
407
408 etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
409
410 register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
411
412 return ERROR_OK;
413 }
414
415 int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
416 {
417 target_t *target;
418 jtag_device_t *jtag_device;
419 armv4_5_common_t *armv4_5;
420 arm7_9_common_t *arm7_9;
421
422 if (argc != 2)
423 {
424 return ERROR_COMMAND_SYNTAX_ERROR;
425 }
426
427 target = get_target_by_num(strtoul(args[0], NULL, 0));
428
429 if (!target)
430 {
431 LOG_ERROR("target number '%s' not defined", args[0]);
432 return ERROR_FAIL;
433 }
434
435 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
436 {
437 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
438 return ERROR_FAIL;
439 }
440
441 jtag_device = jtag_get_device(strtoul(args[1], NULL, 0));
442
443 if (!jtag_device)
444 {
445 return ERROR_FAIL;
446 }
447
448 if (arm7_9->etm_ctx)
449 {
450 etb_t *etb = malloc(sizeof(etb_t));
451
452 arm7_9->etm_ctx->capture_driver_priv = etb;
453
454 etb->chain_pos = strtoul(args[1], NULL, 0);
455 etb->cur_scan_chain = -1;
456 etb->reg_cache = NULL;
457 etb->ram_width = 0;
458 etb->ram_depth = 0;
459 }
460 else
461 {
462 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
463 return ERROR_FAIL;
464 }
465
466 return ERROR_OK;
467 }
468
469 int etb_init(etm_context_t *etm_ctx)
470 {
471 etb_t *etb = etm_ctx->capture_driver_priv;
472
473 etb->etm_ctx = etm_ctx;
474
475 /* identify ETB RAM depth and width */
476 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
477 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
478 jtag_execute_queue();
479
480 etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
481 etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
482
483 return ERROR_OK;
484 }
485
486 trace_status_t etb_status(etm_context_t *etm_ctx)
487 {
488 etb_t *etb = etm_ctx->capture_driver_priv;
489
490 etb->etm_ctx = etm_ctx;
491
492 /* if tracing is currently idle, return this information */
493 if (etm_ctx->capture_status == TRACE_IDLE)
494 {
495 return etm_ctx->capture_status;
496 }
497 else if (etm_ctx->capture_status & TRACE_RUNNING)
498 {
499 reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
500 int etb_timeout = 100;
501
502 /* trace is running, check the ETB status flags */
503 etb_get_reg(etb_status_reg);
504
505 /* check Full bit to identify an overflow */
506 if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
507 etm_ctx->capture_status |= TRACE_OVERFLOWED;
508
509 /* check Triggered bit to identify trigger condition */
510 if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
511 etm_ctx->capture_status |= TRACE_TRIGGERED;
512
513 /* check AcqComp to identify trace completion */
514 if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
515 {
516 while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
517 {
518 /* wait for data formatter idle */
519 etb_get_reg(etb_status_reg);
520 }
521
522 if (etb_timeout == 0)
523 {
524 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
525 buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
526 }
527
528 if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
529 {
530 LOG_ERROR("trace completed, but no trigger condition detected");
531 }
532
533 etm_ctx->capture_status &= ~TRACE_RUNNING;
534 etm_ctx->capture_status |= TRACE_COMPLETED;
535 }
536 }
537
538 return etm_ctx->capture_status;
539 }
540
541 int etb_read_trace(etm_context_t *etm_ctx)
542 {
543 etb_t *etb = etm_ctx->capture_driver_priv;
544 int first_frame = 0;
545 int num_frames = etb->ram_depth;
546 u32 *trace_data = NULL;
547 int i, j;
548
549 etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
550 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
551 jtag_execute_queue();
552
553 /* check if we overflowed, and adjust first frame of the trace accordingly
554 * if we didn't overflow, read only up to the frame that would be written next,
555 * i.e. don't read invalid entries
556 */
557 if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
558 {
559 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
560 }
561 else
562 {
563 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
564 }
565
566 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
567
568 /* read data into temporary array for unpacking */
569 trace_data = malloc(sizeof(u32) * num_frames);
570 etb_read_ram(etb, trace_data, num_frames);
571
572 if (etm_ctx->trace_depth > 0)
573 {
574 free(etm_ctx->trace_data);
575 }
576
577 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
578 etm_ctx->trace_depth = num_frames * 3;
579 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
580 etm_ctx->trace_depth = num_frames * 2;
581 else
582 etm_ctx->trace_depth = num_frames;
583
584 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
585
586 for (i = 0, j = 0; i < num_frames; i++)
587 {
588 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
589 {
590 /* trace word j */
591 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
592 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
593 etm_ctx->trace_data[j].flags = 0;
594 if ((trace_data[i] & 0x80) >> 7)
595 {
596 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
597 }
598 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
599 {
600 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
601 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
602 }
603
604 /* trace word j+1 */
605 etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
606 etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
607 etm_ctx->trace_data[j+1].flags = 0;
608 if ((trace_data[i] & 0x8000) >> 15)
609 {
610 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
611 }
612 if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
613 {
614 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
615 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
616 }
617
618 /* trace word j+2 */
619 etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
620 etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
621 etm_ctx->trace_data[j+2].flags = 0;
622 if ((trace_data[i] & 0x800000) >> 23)
623 {
624 etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
625 }
626 if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
627 {
628 etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
629 etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
630 }
631
632 j += 3;
633 }
634 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
635 {
636 /* trace word j */
637 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
638 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
639 etm_ctx->trace_data[j].flags = 0;
640 if ((trace_data[i] & 0x800) >> 11)
641 {
642 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
643 }
644 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
645 {
646 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
647 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
648 }
649
650 /* trace word j+1 */
651 etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
652 etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
653 etm_ctx->trace_data[j+1].flags = 0;
654 if ((trace_data[i] & 0x800000) >> 23)
655 {
656 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
657 }
658 if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
659 {
660 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
661 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
662 }
663
664 j += 2;
665 }
666 else
667 {
668 /* trace word j */
669 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
670 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
671 etm_ctx->trace_data[j].flags = 0;
672 if ((trace_data[i] & 0x80000) >> 19)
673 {
674 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
675 }
676 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
677 {
678 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
679 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
680 }
681
682 j += 1;
683 }
684 }
685
686 free(trace_data);
687
688 return ERROR_OK;
689 }
690
691 int etb_start_capture(etm_context_t *etm_ctx)
692 {
693 etb_t *etb = etm_ctx->capture_driver_priv;
694 u32 etb_ctrl_value = 0x1;
695 u32 trigger_count;
696
697 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
698 {
699 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
700 {
701 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
702 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
703 }
704 etb_ctrl_value |= 0x2;
705 }
706
707 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
708 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
709
710 trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
711
712 etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
713 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
714 etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
715 jtag_execute_queue();
716
717 /* we're starting a new trace, initialize capture status */
718 etm_ctx->capture_status = TRACE_RUNNING;
719
720 return ERROR_OK;
721 }
722
723 int etb_stop_capture(etm_context_t *etm_ctx)
724 {
725 etb_t *etb = etm_ctx->capture_driver_priv;
726 reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
727
728 etb_write_reg(etb_ctrl_reg, 0x0);
729 jtag_execute_queue();
730
731 /* trace stopped, just clear running flag, but preserve others */
732 etm_ctx->capture_status &= ~TRACE_RUNNING;
733
734 return ERROR_OK;
735 }
736
737 etm_capture_driver_t etb_capture_driver =
738 {
739 .name = "etb",
740 .register_commands = etb_register_commands,
741 .init = etb_init,
742 .status = etb_status,
743 .start_capture = etb_start_capture,
744 .stop_capture = etb_stop_capture,
745 .read_trace = etb_read_trace,
746 };
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