1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "embeddedice.h"
27 #include "arm7_9_common.h"
32 #include "binarybuffer.h"
39 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc
[] =
47 int embeddedice_reg_arch_info
[] =
50 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
51 0x10, 0x11, 0x12, 0x13, 0x14, 0x15
54 char* embeddedice_reg_list
[] =
66 "watch 0 control value",
67 "watch 0 control mask",
73 "watch 1 control value",
74 "watch 1 control mask"
77 int embeddedice_reg_arch_type
= -1;
79 int embeddedice_get_reg(reg_t
*reg
);
80 int embeddedice_set_reg(reg_t
*reg
, u32 value
);
81 int embeddedice_set_reg_w_exec(reg_t
*reg
, u8
*buf
);
83 int embeddedice_write_reg(reg_t
*reg
, u32 value
);
84 int embeddedice_read_reg(reg_t
*reg
);
86 reg_cache_t
* embeddedice_build_reg_cache(target_t
*target
, arm_jtag_t
*jtag_info
, int extra_reg
)
88 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
89 reg_t
*reg_list
= NULL
;
90 embeddedice_reg_t
*arch_info
= NULL
;
91 int num_regs
= 16 + extra_reg
;
94 /* register a register arch-type for EmbeddedICE registers only once */
95 if (embeddedice_reg_arch_type
== -1)
96 embeddedice_reg_arch_type
= register_reg_arch_type(embeddedice_get_reg
, embeddedice_set_reg_w_exec
);
98 /* the actual registers are kept in two arrays */
99 reg_list
= calloc(num_regs
, sizeof(reg_t
));
100 arch_info
= calloc(num_regs
, sizeof(embeddedice_reg_t
));
102 /* fill in values for the reg cache */
103 reg_cache
->name
= "EmbeddedICE registers";
104 reg_cache
->next
= NULL
;
105 reg_cache
->reg_list
= reg_list
;
106 reg_cache
->num_regs
= num_regs
;
108 /* set up registers */
109 for (i
= 0; i
< num_regs
- extra_reg
; i
++)
111 reg_list
[i
].name
= embeddedice_reg_list
[i
];
112 reg_list
[i
].size
= 32;
113 reg_list
[i
].dirty
= 0;
114 reg_list
[i
].valid
= 0;
115 reg_list
[i
].bitfield_desc
= NULL
;
116 reg_list
[i
].num_bitfields
= 0;
117 reg_list
[i
].value
= calloc(1, 4);
118 reg_list
[i
].arch_info
= &arch_info
[i
];
119 reg_list
[i
].arch_type
= embeddedice_reg_arch_type
;
120 arch_info
[i
].addr
= embeddedice_reg_arch_info
[i
];
121 arch_info
[i
].jtag_info
= jtag_info
;
124 /* there may be one extra reg (Abort status (ARM7 rev4) or Vector catch (ARM9)) */
127 reg_list
[num_regs
- 1].arch_info
= &arch_info
[num_regs
- 1];
128 reg_list
[num_regs
- 1].arch_type
= embeddedice_reg_arch_type
;
129 arch_info
[num_regs
- 1].jtag_info
= jtag_info
;
135 int embeddedice_get_reg(reg_t
*reg
)
137 if (embeddedice_read_reg(reg
) != ERROR_OK
)
139 ERROR("BUG: error scheduling EmbeddedICE register read");
143 if (jtag_execute_queue() != ERROR_OK
)
145 ERROR("register read failed");
151 int embeddedice_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
153 embeddedice_reg_t
*ice_reg
= reg
->arch_info
;
154 u8 reg_addr
= ice_reg
->addr
& 0x1f;
155 scan_field_t fields
[3];
157 DEBUG("%i", ice_reg
->addr
);
159 jtag_add_end_state(TAP_RTI
);
160 arm_jtag_scann(ice_reg
->jtag_info
, 0x2);
161 arm_jtag_set_instr(ice_reg
->jtag_info
, ice_reg
->jtag_info
->intest_instr
);
163 fields
[0].device
= ice_reg
->jtag_info
->chain_pos
;
164 fields
[0].num_bits
= 32;
165 fields
[0].out_value
= reg
->value
;
166 fields
[0].out_mask
= NULL
;
167 fields
[0].in_value
= NULL
;
168 fields
[0].in_check_value
= NULL
;
169 fields
[0].in_check_mask
= NULL
;
170 fields
[0].in_handler
= NULL
;
171 fields
[0].in_handler_priv
= NULL
;
173 fields
[1].device
= ice_reg
->jtag_info
->chain_pos
;
174 fields
[1].num_bits
= 5;
175 fields
[1].out_value
= malloc(1);
176 buf_set_u32(fields
[1].out_value
, 0, 5, reg_addr
);
177 fields
[1].out_mask
= NULL
;
178 fields
[1].in_value
= NULL
;
179 fields
[1].in_check_value
= NULL
;
180 fields
[1].in_check_mask
= NULL
;
181 fields
[1].in_handler
= NULL
;
182 fields
[1].in_handler_priv
= NULL
;
184 fields
[2].device
= ice_reg
->jtag_info
->chain_pos
;
185 fields
[2].num_bits
= 1;
186 fields
[2].out_value
= malloc(1);
187 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
188 fields
[2].out_mask
= NULL
;
189 fields
[2].in_value
= NULL
;
190 fields
[2].in_check_value
= NULL
;
191 fields
[2].in_check_mask
= NULL
;
192 fields
[2].in_handler
= NULL
;
193 fields
[2].in_handler_priv
= NULL
;
195 jtag_add_dr_scan(3, fields
, -1);
197 fields
[0].in_value
= reg
->value
;
198 fields
[0].in_check_value
= check_value
;
199 fields
[0].in_check_mask
= check_mask
;
201 /* when reading the DCC data register, leaving the address field set to
202 * EICE_COMMS_DATA would read the register twice
203 * reading the control register is safe
205 buf_set_u32(fields
[1].out_value
, 0, 5, embeddedice_reg_arch_info
[EICE_COMMS_CTRL
]);
207 jtag_add_dr_scan(3, fields
, -1);
209 free(fields
[1].out_value
);
210 free(fields
[2].out_value
);
215 int embeddedice_read_reg(reg_t
*reg
)
217 return embeddedice_read_reg_w_check(reg
, NULL
, NULL
);
220 int embeddedice_set_reg(reg_t
*reg
, u32 value
)
222 if (embeddedice_write_reg(reg
, value
) != ERROR_OK
)
224 ERROR("BUG: error scheduling EmbeddedICE register write");
228 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
235 int embeddedice_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
237 embeddedice_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
239 if (jtag_execute_queue() != ERROR_OK
)
241 ERROR("register write failed");
247 int embeddedice_write_reg(reg_t
*reg
, u32 value
)
249 embeddedice_reg_t
*ice_reg
= reg
->arch_info
;
250 u8 reg_addr
= ice_reg
->addr
& 0x1f;
251 scan_field_t fields
[3];
253 DEBUG("%i: 0x%8.8x", ice_reg
->addr
, value
);
255 jtag_add_end_state(TAP_RTI
);
256 arm_jtag_scann(ice_reg
->jtag_info
, 0x2);
257 arm_jtag_set_instr(ice_reg
->jtag_info
, ice_reg
->jtag_info
->intest_instr
);
259 fields
[0].device
= ice_reg
->jtag_info
->chain_pos
;
260 fields
[0].num_bits
= 32;
261 fields
[0].out_value
= malloc(4);
262 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
263 fields
[0].out_mask
= NULL
;
264 fields
[0].in_value
= NULL
;
265 fields
[0].in_check_value
= NULL
;
266 fields
[0].in_check_mask
= NULL
;
267 fields
[0].in_handler
= NULL
;
268 fields
[0].in_handler_priv
= NULL
;
270 fields
[1].device
= ice_reg
->jtag_info
->chain_pos
;
271 fields
[1].num_bits
= 5;
272 fields
[1].out_value
= malloc(1);
273 buf_set_u32(fields
[1].out_value
, 0, 5, reg_addr
);
274 fields
[1].out_mask
= NULL
;
275 fields
[1].in_value
= NULL
;
276 fields
[1].in_check_value
= NULL
;
277 fields
[1].in_check_mask
= NULL
;
278 fields
[1].in_handler
= NULL
;
279 fields
[1].in_handler_priv
= NULL
;
281 fields
[2].device
= ice_reg
->jtag_info
->chain_pos
;
282 fields
[2].num_bits
= 1;
283 fields
[2].out_value
= malloc(1);
284 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
285 fields
[2].out_mask
= NULL
;
286 fields
[2].in_value
= NULL
;
287 fields
[2].in_check_value
= NULL
;
288 fields
[2].in_check_mask
= NULL
;
289 fields
[2].in_handler
= NULL
;
290 fields
[2].in_handler_priv
= NULL
;
292 jtag_add_dr_scan(3, fields
, -1);
294 free(fields
[0].out_value
);
295 free(fields
[1].out_value
);
296 free(fields
[2].out_value
);
301 int embeddedice_store_reg(reg_t
*reg
)
303 return embeddedice_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)