1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "embeddedice.h"
27 #include "arm7_9_common.h"
32 #include "binarybuffer.h"
39 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc
[] =
47 int embeddedice_reg_arch_info
[] =
50 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
51 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
55 char* embeddedice_reg_list
[] =
67 "watch 0 control value",
68 "watch 0 control mask",
74 "watch 1 control value",
75 "watch 1 control mask",
80 int embeddedice_reg_arch_type
= -1;
82 int embeddedice_get_reg(reg_t
*reg
);
83 int embeddedice_set_reg(reg_t
*reg
, u32 value
);
84 int embeddedice_set_reg_w_exec(reg_t
*reg
, u8
*buf
);
86 int embeddedice_write_reg(reg_t
*reg
, u32 value
);
87 int embeddedice_read_reg(reg_t
*reg
);
89 reg_cache_t
* embeddedice_build_reg_cache(target_t
*target
, arm7_9_common_t
*arm7_9
)
91 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
92 reg_t
*reg_list
= NULL
;
93 embeddedice_reg_t
*arch_info
= NULL
;
94 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
99 /* register a register arch-type for EmbeddedICE registers only once */
100 if (embeddedice_reg_arch_type
== -1)
101 embeddedice_reg_arch_type
= register_reg_arch_type(embeddedice_get_reg
, embeddedice_set_reg_w_exec
);
103 if (arm7_9
->has_vector_catch
)
108 /* the actual registers are kept in two arrays */
109 reg_list
= calloc(num_regs
, sizeof(reg_t
));
110 arch_info
= calloc(num_regs
, sizeof(embeddedice_reg_t
));
112 /* fill in values for the reg cache */
113 reg_cache
->name
= "EmbeddedICE registers";
114 reg_cache
->next
= NULL
;
115 reg_cache
->reg_list
= reg_list
;
116 reg_cache
->num_regs
= num_regs
;
118 /* set up registers */
119 for (i
= 0; i
< num_regs
; i
++)
121 reg_list
[i
].name
= embeddedice_reg_list
[i
];
122 reg_list
[i
].size
= 32;
123 reg_list
[i
].dirty
= 0;
124 reg_list
[i
].valid
= 0;
125 reg_list
[i
].bitfield_desc
= NULL
;
126 reg_list
[i
].num_bitfields
= 0;
127 reg_list
[i
].value
= calloc(1, 4);
128 reg_list
[i
].arch_info
= &arch_info
[i
];
129 reg_list
[i
].arch_type
= embeddedice_reg_arch_type
;
130 arch_info
[i
].addr
= embeddedice_reg_arch_info
[i
];
131 arch_info
[i
].jtag_info
= jtag_info
;
134 /* identify EmbeddedICE version by reading DCC control register */
135 embeddedice_read_reg(®_list
[EICE_COMMS_CTRL
]);
136 jtag_execute_queue();
138 eice_version
= buf_get_u32(reg_list
[EICE_COMMS_CTRL
].value
, 28, 4);
140 switch (eice_version
)
143 reg_list
[EICE_DBG_CTRL
].size
= 3;
144 reg_list
[EICE_DBG_STAT
].size
= 5;
147 reg_list
[EICE_DBG_CTRL
].size
= 4;
148 reg_list
[EICE_DBG_STAT
].size
= 5;
149 arm7_9
->has_single_step
= 1;
152 ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
153 reg_list
[EICE_DBG_CTRL
].size
= 6;
154 reg_list
[EICE_DBG_STAT
].size
= 5;
155 arm7_9
->has_single_step
= 1;
156 arm7_9
->has_monitor_mode
= 1;
159 reg_list
[EICE_DBG_CTRL
].size
= 6;
160 reg_list
[EICE_DBG_STAT
].size
= 5;
161 arm7_9
->has_monitor_mode
= 1;
164 reg_list
[EICE_DBG_CTRL
].size
= 6;
165 reg_list
[EICE_DBG_STAT
].size
= 5;
166 arm7_9
->has_single_step
= 1;
167 arm7_9
->has_monitor_mode
= 1;
170 reg_list
[EICE_DBG_CTRL
].size
= 6;
171 reg_list
[EICE_DBG_STAT
].size
= 10;
172 arm7_9
->has_monitor_mode
= 1;
175 WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
176 reg_list
[EICE_DBG_CTRL
].size
= 6;
177 reg_list
[EICE_DBG_STAT
].size
= 5;
178 arm7_9
->has_monitor_mode
= 1;
181 ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list
[EICE_COMMS_CTRL
].value
, 0, 32));
184 /* explicitly disable monitor mode */
185 if (arm7_9
->has_monitor_mode
)
187 embeddedice_read_reg(®_list
[EICE_DBG_CTRL
]);
188 jtag_execute_queue();
189 buf_set_u32(reg_list
[EICE_DBG_CTRL
].value
, 4, 1, 0);
190 embeddedice_set_reg_w_exec(®_list
[EICE_DBG_CTRL
], reg_list
[EICE_DBG_CTRL
].value
);
196 int embeddedice_get_reg(reg_t
*reg
)
198 if (embeddedice_read_reg(reg
) != ERROR_OK
)
200 ERROR("BUG: error scheduling EmbeddedICE register read");
204 if (jtag_execute_queue() != ERROR_OK
)
206 ERROR("register read failed");
212 int embeddedice_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
214 embeddedice_reg_t
*ice_reg
= reg
->arch_info
;
215 u8 reg_addr
= ice_reg
->addr
& 0x1f;
216 scan_field_t fields
[3];
218 DEBUG("%i", ice_reg
->addr
);
220 jtag_add_end_state(TAP_RTI
);
221 arm_jtag_scann(ice_reg
->jtag_info
, 0x2);
223 arm_jtag_set_instr(ice_reg
->jtag_info
, ice_reg
->jtag_info
->intest_instr
, NULL
);
225 fields
[0].device
= ice_reg
->jtag_info
->chain_pos
;
226 fields
[0].num_bits
= 32;
227 fields
[0].out_value
= reg
->value
;
228 fields
[0].out_mask
= NULL
;
229 fields
[0].in_value
= NULL
;
230 fields
[0].in_check_value
= NULL
;
231 fields
[0].in_check_mask
= NULL
;
232 fields
[0].in_handler
= NULL
;
233 fields
[0].in_handler_priv
= NULL
;
235 fields
[1].device
= ice_reg
->jtag_info
->chain_pos
;
236 fields
[1].num_bits
= 5;
237 fields
[1].out_value
= malloc(1);
238 buf_set_u32(fields
[1].out_value
, 0, 5, reg_addr
);
239 fields
[1].out_mask
= NULL
;
240 fields
[1].in_value
= NULL
;
241 fields
[1].in_check_value
= NULL
;
242 fields
[1].in_check_mask
= NULL
;
243 fields
[1].in_handler
= NULL
;
244 fields
[1].in_handler_priv
= NULL
;
246 fields
[2].device
= ice_reg
->jtag_info
->chain_pos
;
247 fields
[2].num_bits
= 1;
248 fields
[2].out_value
= malloc(1);
249 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
250 fields
[2].out_mask
= NULL
;
251 fields
[2].in_value
= NULL
;
252 fields
[2].in_check_value
= NULL
;
253 fields
[2].in_check_mask
= NULL
;
254 fields
[2].in_handler
= NULL
;
255 fields
[2].in_handler_priv
= NULL
;
257 jtag_add_dr_scan(3, fields
, -1, NULL
);
259 fields
[0].in_value
= reg
->value
;
260 fields
[0].in_check_value
= check_value
;
261 fields
[0].in_check_mask
= check_mask
;
263 /* when reading the DCC data register, leaving the address field set to
264 * EICE_COMMS_DATA would read the register twice
265 * reading the control register is safe
267 buf_set_u32(fields
[1].out_value
, 0, 5, embeddedice_reg_arch_info
[EICE_COMMS_CTRL
]);
269 jtag_add_dr_scan(3, fields
, -1, NULL
);
271 free(fields
[1].out_value
);
272 free(fields
[2].out_value
);
277 /* receive <size> words of 32 bit from the DCC
278 * we pretend the target is always going to be fast enough
279 * (relative to the JTAG clock), so we don't need to handshake
281 int embeddedice_receive(arm_jtag_t
*jtag_info
, u32
*data
, u32 size
)
284 scan_field_t fields
[3];
286 jtag_add_end_state(TAP_RTI
);
287 arm_jtag_scann(jtag_info
, 0x2);
288 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
290 fields
[0].device
= jtag_info
->chain_pos
;
291 fields
[0].num_bits
= 32;
292 fields
[0].out_value
= NULL
;
293 fields
[0].out_mask
= NULL
;
294 fields
[0].in_value
= NULL
;
295 fields
[0].in_check_value
= NULL
;
296 fields
[0].in_check_mask
= NULL
;
297 fields
[0].in_handler
= NULL
;
298 fields
[0].in_handler_priv
= NULL
;
300 fields
[1].device
= jtag_info
->chain_pos
;
301 fields
[1].num_bits
= 5;
302 fields
[1].out_value
= malloc(1);
303 buf_set_u32(fields
[1].out_value
, 0, 5, reg_addr
);
304 fields
[1].out_mask
= NULL
;
305 fields
[1].in_value
= NULL
;
306 fields
[1].in_check_value
= NULL
;
307 fields
[1].in_check_mask
= NULL
;
308 fields
[1].in_handler
= NULL
;
309 fields
[1].in_handler_priv
= NULL
;
311 fields
[2].device
= jtag_info
->chain_pos
;
312 fields
[2].num_bits
= 1;
313 fields
[2].out_value
= malloc(1);
314 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
315 fields
[2].out_mask
= NULL
;
316 fields
[2].in_value
= NULL
;
317 fields
[2].in_check_value
= NULL
;
318 fields
[2].in_check_mask
= NULL
;
319 fields
[2].in_handler
= NULL
;
320 fields
[2].in_handler_priv
= NULL
;
322 jtag_add_dr_scan(3, fields
, -1, NULL
);
326 /* when reading the last item, set the register address to the DCC control reg,
327 * to avoid reading additional data from the DCC data reg
330 buf_set_u32(fields
[1].out_value
, 0, 5, embeddedice_reg_arch_info
[EICE_COMMS_CTRL
]);
332 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
333 fields
[0].in_handler_priv
= data
;
334 jtag_add_dr_scan(3, fields
, -1, NULL
);
340 free(fields
[1].out_value
);
341 free(fields
[2].out_value
);
343 return jtag_execute_queue();
346 int embeddedice_read_reg(reg_t
*reg
)
348 return embeddedice_read_reg_w_check(reg
, NULL
, NULL
);
351 int embeddedice_set_reg(reg_t
*reg
, u32 value
)
353 if (embeddedice_write_reg(reg
, value
) != ERROR_OK
)
355 ERROR("BUG: error scheduling EmbeddedICE register write");
359 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
366 int embeddedice_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
368 embeddedice_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
370 if (jtag_execute_queue() != ERROR_OK
)
372 ERROR("register write failed");
378 int embeddedice_write_reg(reg_t
*reg
, u32 value
)
380 embeddedice_reg_t
*ice_reg
= reg
->arch_info
;
381 u8 reg_addr
= ice_reg
->addr
& 0x1f;
382 scan_field_t fields
[3];
384 DEBUG("%i: 0x%8.8x", ice_reg
->addr
, value
);
386 jtag_add_end_state(TAP_RTI
);
387 arm_jtag_scann(ice_reg
->jtag_info
, 0x2);
389 arm_jtag_set_instr(ice_reg
->jtag_info
, ice_reg
->jtag_info
->intest_instr
, NULL
);
391 fields
[0].device
= ice_reg
->jtag_info
->chain_pos
;
392 fields
[0].num_bits
= 32;
393 fields
[0].out_value
= malloc(4);
394 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
395 fields
[0].out_mask
= NULL
;
396 fields
[0].in_value
= NULL
;
397 fields
[0].in_check_value
= NULL
;
398 fields
[0].in_check_mask
= NULL
;
399 fields
[0].in_handler
= NULL
;
400 fields
[0].in_handler_priv
= NULL
;
402 fields
[1].device
= ice_reg
->jtag_info
->chain_pos
;
403 fields
[1].num_bits
= 5;
404 fields
[1].out_value
= malloc(1);
405 buf_set_u32(fields
[1].out_value
, 0, 5, reg_addr
);
406 fields
[1].out_mask
= NULL
;
407 fields
[1].in_value
= NULL
;
408 fields
[1].in_check_value
= NULL
;
409 fields
[1].in_check_mask
= NULL
;
410 fields
[1].in_handler
= NULL
;
411 fields
[1].in_handler_priv
= NULL
;
413 fields
[2].device
= ice_reg
->jtag_info
->chain_pos
;
414 fields
[2].num_bits
= 1;
415 fields
[2].out_value
= malloc(1);
416 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
417 fields
[2].out_mask
= NULL
;
418 fields
[2].in_value
= NULL
;
419 fields
[2].in_check_value
= NULL
;
420 fields
[2].in_check_mask
= NULL
;
421 fields
[2].in_handler
= NULL
;
422 fields
[2].in_handler_priv
= NULL
;
424 jtag_add_dr_scan(3, fields
, -1, NULL
);
426 free(fields
[0].out_value
);
427 free(fields
[1].out_value
);
428 free(fields
[2].out_value
);
433 int embeddedice_store_reg(reg_t
*reg
)
435 return embeddedice_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
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