cfe4ed7c8a74194bd806264935d5dc1acc123084
[openocd.git] / src / target / embeddedice.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 √ėyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "embeddedice.h"
31
32 #include "armv4_5.h"
33 #include "arm7_9_common.h"
34
35 #include "log.h"
36 #include "arm_jtag.h"
37 #include "types.h"
38 #include "binarybuffer.h"
39 #include "target.h"
40 #include "register.h"
41 #include "jtag.h"
42
43 #include <stdlib.h>
44
45 #if 0
46 static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
47 {
48 {"R", 1},
49 {"W", 1},
50 {"reserved", 26},
51 {"version", 4}
52 };
53 #endif
54
55 static int embeddedice_reg_arch_info[] =
56 {
57 0x0, 0x1, 0x4, 0x5,
58 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
59 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
60 0x2
61 };
62
63 static char* embeddedice_reg_list[] =
64 {
65 "debug_ctrl",
66 "debug_status",
67
68 "comms_ctrl",
69 "comms_data",
70
71 "watch 0 addr value",
72 "watch 0 addr mask",
73 "watch 0 data value",
74 "watch 0 data mask",
75 "watch 0 control value",
76 "watch 0 control mask",
77
78 "watch 1 addr value",
79 "watch 1 addr mask",
80 "watch 1 data value",
81 "watch 1 data mask",
82 "watch 1 control value",
83 "watch 1 control mask",
84
85 "vector catch"
86 };
87
88 static int embeddedice_reg_arch_type = -1;
89
90 static int embeddedice_get_reg(reg_t *reg);
91
92 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
93 {
94 int retval;
95 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
96 reg_t *reg_list = NULL;
97 embeddedice_reg_t *arch_info = NULL;
98 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
99 int num_regs;
100 int i;
101 int eice_version = 0;
102
103 /* register a register arch-type for EmbeddedICE registers only once */
104 if (embeddedice_reg_arch_type == -1)
105 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
106
107 if (arm7_9->has_vector_catch)
108 num_regs = 17;
109 else
110 num_regs = 16;
111
112 /* the actual registers are kept in two arrays */
113 reg_list = calloc(num_regs, sizeof(reg_t));
114 arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
115
116 /* fill in values for the reg cache */
117 reg_cache->name = "EmbeddedICE registers";
118 reg_cache->next = NULL;
119 reg_cache->reg_list = reg_list;
120 reg_cache->num_regs = num_regs;
121
122 /* set up registers */
123 for (i = 0; i < num_regs; i++)
124 {
125 reg_list[i].name = embeddedice_reg_list[i];
126 reg_list[i].size = 32;
127 reg_list[i].dirty = 0;
128 reg_list[i].valid = 0;
129 reg_list[i].bitfield_desc = NULL;
130 reg_list[i].num_bitfields = 0;
131 reg_list[i].value = calloc(1, 4);
132 reg_list[i].arch_info = &arch_info[i];
133 reg_list[i].arch_type = embeddedice_reg_arch_type;
134 arch_info[i].addr = embeddedice_reg_arch_info[i];
135 arch_info[i].jtag_info = jtag_info;
136 }
137
138 /* identify EmbeddedICE version by reading DCC control register */
139 embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
140 if ((retval=jtag_execute_queue())!=ERROR_OK)
141 {
142 for (i = 0; i < num_regs; i++)
143 {
144 free(reg_list[i].value);
145 }
146 free(reg_list);
147 free(arch_info);
148 return NULL;
149 }
150
151 eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
152
153 switch (eice_version)
154 {
155 case 1:
156 reg_list[EICE_DBG_CTRL].size = 3;
157 reg_list[EICE_DBG_STAT].size = 5;
158 break;
159 case 2:
160 reg_list[EICE_DBG_CTRL].size = 4;
161 reg_list[EICE_DBG_STAT].size = 5;
162 arm7_9->has_single_step = 1;
163 break;
164 case 3:
165 LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
166 reg_list[EICE_DBG_CTRL].size = 6;
167 reg_list[EICE_DBG_STAT].size = 5;
168 arm7_9->has_single_step = 1;
169 arm7_9->has_monitor_mode = 1;
170 break;
171 case 4:
172 reg_list[EICE_DBG_CTRL].size = 6;
173 reg_list[EICE_DBG_STAT].size = 5;
174 arm7_9->has_monitor_mode = 1;
175 break;
176 case 5:
177 reg_list[EICE_DBG_CTRL].size = 6;
178 reg_list[EICE_DBG_STAT].size = 5;
179 arm7_9->has_single_step = 1;
180 arm7_9->has_monitor_mode = 1;
181 break;
182 case 6:
183 reg_list[EICE_DBG_CTRL].size = 6;
184 reg_list[EICE_DBG_STAT].size = 10;
185 arm7_9->has_monitor_mode = 1;
186 break;
187 case 7:
188 LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
189 reg_list[EICE_DBG_CTRL].size = 6;
190 reg_list[EICE_DBG_STAT].size = 5;
191 arm7_9->has_monitor_mode = 1;
192 break;
193 default:
194 LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
195 }
196
197 return reg_cache;
198 }
199
200 int embeddedice_setup(target_t *target)
201 {
202 int retval;
203 armv4_5_common_t *armv4_5 = target->arch_info;
204 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
205
206 /* explicitly disable monitor mode */
207 if (arm7_9->has_monitor_mode)
208 {
209 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
210
211 embeddedice_read_reg(dbg_ctrl);
212 if ((retval=jtag_execute_queue())!=ERROR_OK)
213 return retval;
214 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
215 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
216 }
217 return jtag_execute_queue();
218 }
219
220 static int embeddedice_get_reg(reg_t *reg)
221 {
222 int retval;
223 if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
224 {
225 LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
226 return retval;
227 }
228
229 if ((retval = jtag_execute_queue()) != ERROR_OK)
230 {
231 LOG_ERROR("register read failed");
232 return retval;
233 }
234
235 return ERROR_OK;
236 }
237
238 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
239 {
240 embeddedice_reg_t *ice_reg = reg->arch_info;
241 u8 reg_addr = ice_reg->addr & 0x1f;
242 scan_field_t fields[3];
243 u8 field1_out[1];
244 u8 field2_out[1];
245
246 jtag_add_end_state(TAP_IDLE);
247 arm_jtag_scann(ice_reg->jtag_info, 0x2);
248
249 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
250
251 fields[0].tap = ice_reg->jtag_info->tap;
252 fields[0].num_bits = 32;
253 fields[0].out_value = reg->value;
254
255 fields[0].in_value = NULL;
256
257
258 fields[0].in_handler = NULL;
259
260
261 fields[1].tap = ice_reg->jtag_info->tap;
262 fields[1].num_bits = 5;
263 fields[1].out_value = field1_out;
264 buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
265
266 fields[1].in_value = NULL;
267
268
269 fields[1].in_handler = NULL;
270
271
272 fields[2].tap = ice_reg->jtag_info->tap;
273 fields[2].num_bits = 1;
274 fields[2].out_value = field2_out;
275 buf_set_u32(fields[2].out_value, 0, 1, 0);
276
277 fields[2].in_value = NULL;
278
279
280 fields[2].in_handler = NULL;
281
282
283 jtag_add_dr_scan(3, fields, TAP_INVALID);
284
285 fields[0].in_value = reg->value;
286 jtag_set_check_value(fields+0, check_value, check_mask, NULL);
287
288 /* when reading the DCC data register, leaving the address field set to
289 * EICE_COMMS_DATA would read the register twice
290 * reading the control register is safe
291 */
292 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
293
294 jtag_add_dr_scan(3, fields, TAP_INVALID);
295
296 return ERROR_OK;
297 }
298
299 /* receive <size> words of 32 bit from the DCC
300 * we pretend the target is always going to be fast enough
301 * (relative to the JTAG clock), so we don't need to handshake
302 */
303 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
304 {
305 scan_field_t fields[3];
306 u8 field1_out[1];
307 u8 field2_out[1];
308
309 jtag_add_end_state(TAP_IDLE);
310 arm_jtag_scann(jtag_info, 0x2);
311 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
312
313 fields[0].tap = jtag_info->tap;
314 fields[0].num_bits = 32;
315 fields[0].out_value = NULL;
316
317 fields[0].in_value = NULL;
318
319
320 fields[0].in_handler = NULL;
321
322
323 fields[1].tap = jtag_info->tap;
324 fields[1].num_bits = 5;
325 fields[1].out_value = field1_out;
326 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
327
328 fields[1].in_value = NULL;
329
330
331 fields[1].in_handler = NULL;
332
333
334 fields[2].tap = jtag_info->tap;
335 fields[2].num_bits = 1;
336 fields[2].out_value = field2_out;
337 buf_set_u32(fields[2].out_value, 0, 1, 0);
338
339 fields[2].in_value = NULL;
340
341
342 fields[2].in_handler = NULL;
343
344
345 jtag_add_dr_scan(3, fields, TAP_INVALID);
346
347 while (size > 0)
348 {
349 /* when reading the last item, set the register address to the DCC control reg,
350 * to avoid reading additional data from the DCC data reg
351 */
352 if (size == 1)
353 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
354
355 fields[0].in_handler = arm_jtag_buf_to_u32; /* deprecated! invoke this from user code! */
356 fields[0].in_handler_priv = data;
357 jtag_add_dr_scan(3, fields, TAP_INVALID);
358
359 data++;
360 size--;
361 }
362
363 return jtag_execute_queue();
364 }
365
366 int embeddedice_read_reg(reg_t *reg)
367 {
368 return embeddedice_read_reg_w_check(reg, NULL, NULL);
369 }
370
371 void embeddedice_set_reg(reg_t *reg, u32 value)
372 {
373 embeddedice_write_reg(reg, value);
374
375 buf_set_u32(reg->value, 0, reg->size, value);
376 reg->valid = 1;
377 reg->dirty = 0;
378
379 }
380
381 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
382 {
383 int retval;
384 embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
385
386 if ((retval = jtag_execute_queue()) != ERROR_OK)
387 {
388 LOG_ERROR("register write failed");
389 return retval;
390 }
391 return ERROR_OK;
392 }
393
394 void embeddedice_write_reg(reg_t *reg, u32 value)
395 {
396 embeddedice_reg_t *ice_reg = reg->arch_info;
397
398 LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
399
400 jtag_add_end_state(TAP_IDLE);
401 arm_jtag_scann(ice_reg->jtag_info, 0x2);
402
403 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
404
405 u8 reg_addr = ice_reg->addr & 0x1f;
406 embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
407
408 }
409
410 void embeddedice_store_reg(reg_t *reg)
411 {
412 embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
413 }
414
415 /* send <size> words of 32 bit to the DCC
416 * we pretend the target is always going to be fast enough
417 * (relative to the JTAG clock), so we don't need to handshake
418 */
419 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
420 {
421 scan_field_t fields[3];
422 u8 field0_out[4];
423 u8 field1_out[1];
424 u8 field2_out[1];
425
426 jtag_add_end_state(TAP_IDLE);
427 arm_jtag_scann(jtag_info, 0x2);
428 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
429
430 fields[0].tap = jtag_info->tap;
431 fields[0].num_bits = 32;
432 fields[0].out_value = field0_out;
433
434 fields[0].in_value = NULL;
435
436
437 fields[0].in_handler = NULL;
438
439
440 fields[1].tap = jtag_info->tap;
441 fields[1].num_bits = 5;
442 fields[1].out_value = field1_out;
443 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
444
445 fields[1].in_value = NULL;
446
447
448 fields[1].in_handler = NULL;
449
450
451 fields[2].tap = jtag_info->tap;
452 fields[2].num_bits = 1;
453 fields[2].out_value = field2_out;
454 buf_set_u32(fields[2].out_value, 0, 1, 1);
455
456 fields[2].in_value = NULL;
457
458
459 fields[2].in_handler = NULL;
460
461
462 while (size > 0)
463 {
464 buf_set_u32(fields[0].out_value, 0, 32, *data);
465 jtag_add_dr_scan(3, fields, TAP_INVALID);
466
467 data++;
468 size--;
469 }
470
471 /* call to jtag_execute_queue() intentionally omitted */
472 return ERROR_OK;
473 }
474
475 /* wait for DCC control register R/W handshake bit to become active
476 */
477 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
478 {
479 scan_field_t fields[3];
480 u8 field0_in[4];
481 u8 field1_out[1];
482 u8 field2_out[1];
483 int retval;
484 u32 hsact;
485 struct timeval lap;
486 struct timeval now;
487
488 if (hsbit == EICE_COMM_CTRL_WBIT)
489 hsact = 1;
490 else if (hsbit == EICE_COMM_CTRL_RBIT)
491 hsact = 0;
492 else
493 return ERROR_INVALID_ARGUMENTS;
494
495 jtag_add_end_state(TAP_IDLE);
496 arm_jtag_scann(jtag_info, 0x2);
497 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
498
499 fields[0].tap = jtag_info->tap;
500 fields[0].num_bits = 32;
501 fields[0].out_value = NULL;
502
503 fields[0].in_value = field0_in;
504
505
506 fields[0].in_handler = NULL;
507
508
509 fields[1].tap = jtag_info->tap;
510 fields[1].num_bits = 5;
511 fields[1].out_value = field1_out;
512 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
513
514 fields[1].in_value = NULL;
515
516
517 fields[1].in_handler = NULL;
518
519
520 fields[2].tap = jtag_info->tap;
521 fields[2].num_bits = 1;
522 fields[2].out_value = field2_out;
523 buf_set_u32(fields[2].out_value, 0, 1, 0);
524
525 fields[2].in_value = NULL;
526
527
528 fields[2].in_handler = NULL;
529
530
531 jtag_add_dr_scan(3, fields, TAP_INVALID);
532 gettimeofday(&lap, NULL);
533 do
534 {
535 jtag_add_dr_scan(3, fields, TAP_INVALID);
536 if ((retval = jtag_execute_queue()) != ERROR_OK)
537 return retval;
538
539 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
540 return ERROR_OK;
541
542 gettimeofday(&now, NULL);
543 }
544 while ((u32)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout);
545
546 return ERROR_TARGET_TIMEOUT;
547 }
548
549 /* this is the inner loop of the open loop DCC write of data to target */
550 void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
551 {
552 int i;
553 for (i = 0; i < count; i++)
554 {
555 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
556 buffer += 4;
557 }
558 }