jtag newtap change & huge manual update
[openocd.git] / src / target / embeddedice.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 √ėyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "embeddedice.h"
31
32 #include "armv4_5.h"
33 #include "arm7_9_common.h"
34
35 #include "log.h"
36 #include "arm_jtag.h"
37 #include "types.h"
38 #include "binarybuffer.h"
39 #include "target.h"
40 #include "register.h"
41 #include "jtag.h"
42
43 #include <stdlib.h>
44
45 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
46 {
47 {"R", 1},
48 {"W", 1},
49 {"reserved", 26},
50 {"version", 4}
51 };
52
53 int embeddedice_reg_arch_info[] =
54 {
55 0x0, 0x1, 0x4, 0x5,
56 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
57 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
58 0x2
59 };
60
61 char* embeddedice_reg_list[] =
62 {
63 "debug_ctrl",
64 "debug_status",
65
66 "comms_ctrl",
67 "comms_data",
68
69 "watch 0 addr value",
70 "watch 0 addr mask",
71 "watch 0 data value",
72 "watch 0 data mask",
73 "watch 0 control value",
74 "watch 0 control mask",
75
76 "watch 1 addr value",
77 "watch 1 addr mask",
78 "watch 1 data value",
79 "watch 1 data mask",
80 "watch 1 control value",
81 "watch 1 control mask",
82
83 "vector catch"
84 };
85
86 int embeddedice_reg_arch_type = -1;
87
88 int embeddedice_get_reg(reg_t *reg);
89 void embeddedice_set_reg(reg_t *reg, u32 value);
90 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
91
92 void embeddedice_write_reg(reg_t *reg, u32 value);
93 int embeddedice_read_reg(reg_t *reg);
94
95 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
96 {
97 int retval;
98 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
99 reg_t *reg_list = NULL;
100 embeddedice_reg_t *arch_info = NULL;
101 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
102 int num_regs;
103 int i;
104 int eice_version = 0;
105
106 /* register a register arch-type for EmbeddedICE registers only once */
107 if (embeddedice_reg_arch_type == -1)
108 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
109
110 if (arm7_9->has_vector_catch)
111 num_regs = 17;
112 else
113 num_regs = 16;
114
115 /* the actual registers are kept in two arrays */
116 reg_list = calloc(num_regs, sizeof(reg_t));
117 arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
118
119 /* fill in values for the reg cache */
120 reg_cache->name = "EmbeddedICE registers";
121 reg_cache->next = NULL;
122 reg_cache->reg_list = reg_list;
123 reg_cache->num_regs = num_regs;
124
125 /* set up registers */
126 for (i = 0; i < num_regs; i++)
127 {
128 reg_list[i].name = embeddedice_reg_list[i];
129 reg_list[i].size = 32;
130 reg_list[i].dirty = 0;
131 reg_list[i].valid = 0;
132 reg_list[i].bitfield_desc = NULL;
133 reg_list[i].num_bitfields = 0;
134 reg_list[i].value = calloc(1, 4);
135 reg_list[i].arch_info = &arch_info[i];
136 reg_list[i].arch_type = embeddedice_reg_arch_type;
137 arch_info[i].addr = embeddedice_reg_arch_info[i];
138 arch_info[i].jtag_info = jtag_info;
139 }
140
141 /* identify EmbeddedICE version by reading DCC control register */
142 embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
143 if ((retval=jtag_execute_queue())!=ERROR_OK)
144 {
145 for (i = 0; i < num_regs; i++)
146 {
147 free(reg_list[i].value);
148 }
149 free(reg_list);
150 free(arch_info);
151 return NULL;
152 }
153
154 eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
155
156 switch (eice_version)
157 {
158 case 1:
159 reg_list[EICE_DBG_CTRL].size = 3;
160 reg_list[EICE_DBG_STAT].size = 5;
161 break;
162 case 2:
163 reg_list[EICE_DBG_CTRL].size = 4;
164 reg_list[EICE_DBG_STAT].size = 5;
165 arm7_9->has_single_step = 1;
166 break;
167 case 3:
168 LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
169 reg_list[EICE_DBG_CTRL].size = 6;
170 reg_list[EICE_DBG_STAT].size = 5;
171 arm7_9->has_single_step = 1;
172 arm7_9->has_monitor_mode = 1;
173 break;
174 case 4:
175 reg_list[EICE_DBG_CTRL].size = 6;
176 reg_list[EICE_DBG_STAT].size = 5;
177 arm7_9->has_monitor_mode = 1;
178 break;
179 case 5:
180 reg_list[EICE_DBG_CTRL].size = 6;
181 reg_list[EICE_DBG_STAT].size = 5;
182 arm7_9->has_single_step = 1;
183 arm7_9->has_monitor_mode = 1;
184 break;
185 case 6:
186 reg_list[EICE_DBG_CTRL].size = 6;
187 reg_list[EICE_DBG_STAT].size = 10;
188 arm7_9->has_monitor_mode = 1;
189 break;
190 case 7:
191 LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
192 reg_list[EICE_DBG_CTRL].size = 6;
193 reg_list[EICE_DBG_STAT].size = 5;
194 arm7_9->has_monitor_mode = 1;
195 break;
196 default:
197 LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
198 }
199
200 return reg_cache;
201 }
202
203 int embeddedice_setup(target_t *target)
204 {
205 int retval;
206 armv4_5_common_t *armv4_5 = target->arch_info;
207 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
208
209 /* explicitly disable monitor mode */
210 if (arm7_9->has_monitor_mode)
211 {
212 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
213
214 embeddedice_read_reg(dbg_ctrl);
215 if ((retval=jtag_execute_queue())!=ERROR_OK)
216 return retval;
217 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
218 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
219 }
220 return jtag_execute_queue();
221 }
222
223 int embeddedice_get_reg(reg_t *reg)
224 {
225 int retval;
226 if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
227 {
228 LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
229 return retval;
230 }
231
232 if ((retval = jtag_execute_queue()) != ERROR_OK)
233 {
234 LOG_ERROR("register read failed");
235 return retval;
236 }
237
238 return ERROR_OK;
239 }
240
241 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
242 {
243 embeddedice_reg_t *ice_reg = reg->arch_info;
244 u8 reg_addr = ice_reg->addr & 0x1f;
245 scan_field_t fields[3];
246 u8 field1_out[1];
247 u8 field2_out[1];
248
249 jtag_add_end_state(TAP_RTI);
250 arm_jtag_scann(ice_reg->jtag_info, 0x2);
251
252 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
253
254 fields[0].tap = ice_reg->jtag_info->tap;
255 fields[0].num_bits = 32;
256 fields[0].out_value = reg->value;
257 fields[0].out_mask = NULL;
258 fields[0].in_value = NULL;
259 fields[0].in_check_value = NULL;
260 fields[0].in_check_mask = NULL;
261 fields[0].in_handler = NULL;
262 fields[0].in_handler_priv = NULL;
263
264 fields[1].tap = ice_reg->jtag_info->tap;
265 fields[1].num_bits = 5;
266 fields[1].out_value = field1_out;
267 buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
268 fields[1].out_mask = NULL;
269 fields[1].in_value = NULL;
270 fields[1].in_check_value = NULL;
271 fields[1].in_check_mask = NULL;
272 fields[1].in_handler = NULL;
273 fields[1].in_handler_priv = NULL;
274
275 fields[2].tap = ice_reg->jtag_info->tap;
276 fields[2].num_bits = 1;
277 fields[2].out_value = field2_out;
278 buf_set_u32(fields[2].out_value, 0, 1, 0);
279 fields[2].out_mask = NULL;
280 fields[2].in_value = NULL;
281 fields[2].in_check_value = NULL;
282 fields[2].in_check_mask = NULL;
283 fields[2].in_handler = NULL;
284 fields[2].in_handler_priv = NULL;
285
286 jtag_add_dr_scan(3, fields, -1);
287
288 fields[0].in_value = reg->value;
289 jtag_set_check_value(fields+0, check_value, check_mask, NULL);
290
291 /* when reading the DCC data register, leaving the address field set to
292 * EICE_COMMS_DATA would read the register twice
293 * reading the control register is safe
294 */
295 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
296
297 jtag_add_dr_scan(3, fields, -1);
298
299 return ERROR_OK;
300 }
301
302 /* receive <size> words of 32 bit from the DCC
303 * we pretend the target is always going to be fast enough
304 * (relative to the JTAG clock), so we don't need to handshake
305 */
306 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
307 {
308 scan_field_t fields[3];
309 u8 field1_out[1];
310 u8 field2_out[1];
311
312 jtag_add_end_state(TAP_RTI);
313 arm_jtag_scann(jtag_info, 0x2);
314 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
315
316 fields[0].tap = jtag_info->tap;
317 fields[0].num_bits = 32;
318 fields[0].out_value = NULL;
319 fields[0].out_mask = NULL;
320 fields[0].in_value = NULL;
321 fields[0].in_check_value = NULL;
322 fields[0].in_check_mask = NULL;
323 fields[0].in_handler = NULL;
324 fields[0].in_handler_priv = NULL;
325
326 fields[1].tap = jtag_info->tap;
327 fields[1].num_bits = 5;
328 fields[1].out_value = field1_out;
329 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
330 fields[1].out_mask = NULL;
331 fields[1].in_value = NULL;
332 fields[1].in_check_value = NULL;
333 fields[1].in_check_mask = NULL;
334 fields[1].in_handler = NULL;
335 fields[1].in_handler_priv = NULL;
336
337 fields[2].tap = jtag_info->tap;
338 fields[2].num_bits = 1;
339 fields[2].out_value = field2_out;
340 buf_set_u32(fields[2].out_value, 0, 1, 0);
341 fields[2].out_mask = NULL;
342 fields[2].in_value = NULL;
343 fields[2].in_check_value = NULL;
344 fields[2].in_check_mask = NULL;
345 fields[2].in_handler = NULL;
346 fields[2].in_handler_priv = NULL;
347
348 jtag_add_dr_scan(3, fields, -1);
349
350 while (size > 0)
351 {
352 /* when reading the last item, set the register address to the DCC control reg,
353 * to avoid reading additional data from the DCC data reg
354 */
355 if (size == 1)
356 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
357
358 fields[0].in_handler = arm_jtag_buf_to_u32;
359 fields[0].in_handler_priv = data;
360 jtag_add_dr_scan(3, fields, -1);
361
362 data++;
363 size--;
364 }
365
366 return jtag_execute_queue();
367 }
368
369 int embeddedice_read_reg(reg_t *reg)
370 {
371 return embeddedice_read_reg_w_check(reg, NULL, NULL);
372 }
373
374 void embeddedice_set_reg(reg_t *reg, u32 value)
375 {
376 embeddedice_write_reg(reg, value);
377
378 buf_set_u32(reg->value, 0, reg->size, value);
379 reg->valid = 1;
380 reg->dirty = 0;
381
382 }
383
384 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
385 {
386 int retval;
387 embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
388
389 if ((retval = jtag_execute_queue()) != ERROR_OK)
390 {
391 LOG_ERROR("register write failed");
392 return retval;
393 }
394 return ERROR_OK;
395 }
396
397 void embeddedice_write_reg(reg_t *reg, u32 value)
398 {
399 embeddedice_reg_t *ice_reg = reg->arch_info;
400
401 LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
402
403 jtag_add_end_state(TAP_RTI);
404 arm_jtag_scann(ice_reg->jtag_info, 0x2);
405
406 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
407
408 u8 reg_addr = ice_reg->addr & 0x1f;
409 embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
410
411 }
412
413 void embeddedice_store_reg(reg_t *reg)
414 {
415 embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
416 }
417
418 /* send <size> words of 32 bit to the DCC
419 * we pretend the target is always going to be fast enough
420 * (relative to the JTAG clock), so we don't need to handshake
421 */
422 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
423 {
424 scan_field_t fields[3];
425 u8 field0_out[4];
426 u8 field1_out[1];
427 u8 field2_out[1];
428
429 jtag_add_end_state(TAP_RTI);
430 arm_jtag_scann(jtag_info, 0x2);
431 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
432
433 fields[0].tap = jtag_info->tap;
434 fields[0].num_bits = 32;
435 fields[0].out_value = field0_out;
436 fields[0].out_mask = NULL;
437 fields[0].in_value = NULL;
438 fields[0].in_check_value = NULL;
439 fields[0].in_check_mask = NULL;
440 fields[0].in_handler = NULL;
441 fields[0].in_handler_priv = NULL;
442
443 fields[1].tap = jtag_info->tap;
444 fields[1].num_bits = 5;
445 fields[1].out_value = field1_out;
446 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
447 fields[1].out_mask = NULL;
448 fields[1].in_value = NULL;
449 fields[1].in_check_value = NULL;
450 fields[1].in_check_mask = NULL;
451 fields[1].in_handler = NULL;
452 fields[1].in_handler_priv = NULL;
453
454 fields[2].tap = jtag_info->tap;
455 fields[2].num_bits = 1;
456 fields[2].out_value = field2_out;
457 buf_set_u32(fields[2].out_value, 0, 1, 1);
458 fields[2].out_mask = NULL;
459 fields[2].in_value = NULL;
460 fields[2].in_check_value = NULL;
461 fields[2].in_check_mask = NULL;
462 fields[2].in_handler = NULL;
463 fields[2].in_handler_priv = NULL;
464
465 while (size > 0)
466 {
467 buf_set_u32(fields[0].out_value, 0, 32, *data);
468 jtag_add_dr_scan(3, fields, -1);
469
470 data++;
471 size--;
472 }
473
474 /* call to jtag_execute_queue() intentionally omitted */
475 return ERROR_OK;
476 }
477
478 /* wait for DCC control register R/W handshake bit to become active
479 */
480 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
481 {
482 scan_field_t fields[3];
483 u8 field0_in[4];
484 u8 field1_out[1];
485 u8 field2_out[1];
486 int retval;
487 int hsact;
488 struct timeval lap;
489 struct timeval now;
490
491 if (hsbit == EICE_COMM_CTRL_WBIT)
492 hsact = 1;
493 else if (hsbit == EICE_COMM_CTRL_RBIT)
494 hsact = 0;
495 else
496 return ERROR_INVALID_ARGUMENTS;
497
498 jtag_add_end_state(TAP_RTI);
499 arm_jtag_scann(jtag_info, 0x2);
500 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
501
502 fields[0].tap = jtag_info->tap;
503 fields[0].num_bits = 32;
504 fields[0].out_value = NULL;
505 fields[0].out_mask = NULL;
506 fields[0].in_value = field0_in;
507 fields[0].in_check_value = NULL;
508 fields[0].in_check_mask = NULL;
509 fields[0].in_handler = NULL;
510 fields[0].in_handler_priv = NULL;
511
512 fields[1].tap = jtag_info->tap;
513 fields[1].num_bits = 5;
514 fields[1].out_value = field1_out;
515 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
516 fields[1].out_mask = NULL;
517 fields[1].in_value = NULL;
518 fields[1].in_check_value = NULL;
519 fields[1].in_check_mask = NULL;
520 fields[1].in_handler = NULL;
521 fields[1].in_handler_priv = NULL;
522
523 fields[2].tap = jtag_info->tap;
524 fields[2].num_bits = 1;
525 fields[2].out_value = field2_out;
526 buf_set_u32(fields[2].out_value, 0, 1, 0);
527 fields[2].out_mask = NULL;
528 fields[2].in_value = NULL;
529 fields[2].in_check_value = NULL;
530 fields[2].in_check_mask = NULL;
531 fields[2].in_handler = NULL;
532 fields[2].in_handler_priv = NULL;
533
534 jtag_add_dr_scan(3, fields, -1);
535 gettimeofday(&lap, NULL);
536 do
537 {
538 jtag_add_dr_scan(3, fields, -1);
539 if ((retval = jtag_execute_queue()) != ERROR_OK)
540 return retval;
541
542 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
543 return ERROR_OK;
544
545 gettimeofday(&now, NULL);
546 }
547 while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout);
548
549 return ERROR_TARGET_TIMEOUT;
550 }
551
552 /* this is the inner loop of the open loop DCC write of data to target */
553 void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
554 {
555 int i;
556 for (i = 0; i < count; i++)
557 {
558 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
559 buffer += 4;
560 }
561 }