- This speeds up dcc arm7_9 bulk write a little bit and exercises the jtag_add_dr_out...
[openocd.git] / src / target / embeddedice.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "embeddedice.h"
25
26 #include "armv4_5.h"
27 #include "arm7_9_common.h"
28
29 #include "log.h"
30 #include "arm_jtag.h"
31 #include "types.h"
32 #include "binarybuffer.h"
33 #include "target.h"
34 #include "register.h"
35 #include "jtag.h"
36
37 #include <stdlib.h>
38
39 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
40 {
41 {"R", 1},
42 {"W", 1},
43 {"reserved", 26},
44 {"version", 4}
45 };
46
47 int embeddedice_reg_arch_info[] =
48 {
49 0x0, 0x1, 0x4, 0x5,
50 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
51 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
52 0x2
53 };
54
55 char* embeddedice_reg_list[] =
56 {
57 "debug_ctrl",
58 "debug_status",
59
60 "comms_ctrl",
61 "comms_data",
62
63 "watch 0 addr value",
64 "watch 0 addr mask",
65 "watch 0 data value",
66 "watch 0 data mask",
67 "watch 0 control value",
68 "watch 0 control mask",
69
70 "watch 1 addr value",
71 "watch 1 addr mask",
72 "watch 1 data value",
73 "watch 1 data mask",
74 "watch 1 control value",
75 "watch 1 control mask",
76
77 "vector catch"
78 };
79
80 int embeddedice_reg_arch_type = -1;
81
82 int embeddedice_get_reg(reg_t *reg);
83 int embeddedice_set_reg(reg_t *reg, u32 value);
84 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
85
86 int embeddedice_write_reg(reg_t *reg, u32 value);
87 int embeddedice_read_reg(reg_t *reg);
88
89 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
90 {
91 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
92 reg_t *reg_list = NULL;
93 embeddedice_reg_t *arch_info = NULL;
94 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
95 int num_regs;
96 int i;
97 int eice_version = 0;
98
99 /* register a register arch-type for EmbeddedICE registers only once */
100 if (embeddedice_reg_arch_type == -1)
101 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
102
103 if (arm7_9->has_vector_catch)
104 num_regs = 17;
105 else
106 num_regs = 16;
107
108 /* the actual registers are kept in two arrays */
109 reg_list = calloc(num_regs, sizeof(reg_t));
110 arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
111
112 /* fill in values for the reg cache */
113 reg_cache->name = "EmbeddedICE registers";
114 reg_cache->next = NULL;
115 reg_cache->reg_list = reg_list;
116 reg_cache->num_regs = num_regs;
117
118 /* set up registers */
119 for (i = 0; i < num_regs; i++)
120 {
121 reg_list[i].name = embeddedice_reg_list[i];
122 reg_list[i].size = 32;
123 reg_list[i].dirty = 0;
124 reg_list[i].valid = 0;
125 reg_list[i].bitfield_desc = NULL;
126 reg_list[i].num_bitfields = 0;
127 reg_list[i].value = calloc(1, 4);
128 reg_list[i].arch_info = &arch_info[i];
129 reg_list[i].arch_type = embeddedice_reg_arch_type;
130 arch_info[i].addr = embeddedice_reg_arch_info[i];
131 arch_info[i].jtag_info = jtag_info;
132 }
133
134 /* identify EmbeddedICE version by reading DCC control register */
135 embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
136 jtag_execute_queue();
137
138 eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
139
140 switch (eice_version)
141 {
142 case 1:
143 reg_list[EICE_DBG_CTRL].size = 3;
144 reg_list[EICE_DBG_STAT].size = 5;
145 break;
146 case 2:
147 reg_list[EICE_DBG_CTRL].size = 4;
148 reg_list[EICE_DBG_STAT].size = 5;
149 arm7_9->has_single_step = 1;
150 break;
151 case 3:
152 ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
153 reg_list[EICE_DBG_CTRL].size = 6;
154 reg_list[EICE_DBG_STAT].size = 5;
155 arm7_9->has_single_step = 1;
156 arm7_9->has_monitor_mode = 1;
157 break;
158 case 4:
159 reg_list[EICE_DBG_CTRL].size = 6;
160 reg_list[EICE_DBG_STAT].size = 5;
161 arm7_9->has_monitor_mode = 1;
162 break;
163 case 5:
164 reg_list[EICE_DBG_CTRL].size = 6;
165 reg_list[EICE_DBG_STAT].size = 5;
166 arm7_9->has_single_step = 1;
167 arm7_9->has_monitor_mode = 1;
168 break;
169 case 6:
170 reg_list[EICE_DBG_CTRL].size = 6;
171 reg_list[EICE_DBG_STAT].size = 10;
172 arm7_9->has_monitor_mode = 1;
173 break;
174 case 7:
175 WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
176 reg_list[EICE_DBG_CTRL].size = 6;
177 reg_list[EICE_DBG_STAT].size = 5;
178 arm7_9->has_monitor_mode = 1;
179 break;
180 default:
181 ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
182 }
183
184 /* explicitly disable monitor mode */
185 if (arm7_9->has_monitor_mode)
186 {
187 embeddedice_read_reg(&reg_list[EICE_DBG_CTRL]);
188 jtag_execute_queue();
189 buf_set_u32(reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
190 embeddedice_set_reg_w_exec(&reg_list[EICE_DBG_CTRL], reg_list[EICE_DBG_CTRL].value);
191 }
192
193 return reg_cache;
194 }
195
196 int embeddedice_get_reg(reg_t *reg)
197 {
198 if (embeddedice_read_reg(reg) != ERROR_OK)
199 {
200 ERROR("BUG: error scheduling EmbeddedICE register read");
201 exit(-1);
202 }
203
204 if (jtag_execute_queue() != ERROR_OK)
205 {
206 ERROR("register read failed");
207 }
208
209 return ERROR_OK;
210 }
211
212 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
213 {
214 embeddedice_reg_t *ice_reg = reg->arch_info;
215 u8 reg_addr = ice_reg->addr & 0x1f;
216 scan_field_t fields[3];
217 u8 field1_out[1];
218 u8 field2_out[1];
219
220 DEBUG("%i", ice_reg->addr);
221
222 jtag_add_end_state(TAP_RTI);
223 arm_jtag_scann(ice_reg->jtag_info, 0x2);
224
225 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
226
227 fields[0].device = ice_reg->jtag_info->chain_pos;
228 fields[0].num_bits = 32;
229 fields[0].out_value = reg->value;
230 fields[0].out_mask = NULL;
231 fields[0].in_value = NULL;
232 fields[0].in_check_value = NULL;
233 fields[0].in_check_mask = NULL;
234 fields[0].in_handler = NULL;
235 fields[0].in_handler_priv = NULL;
236
237 fields[1].device = ice_reg->jtag_info->chain_pos;
238 fields[1].num_bits = 5;
239 fields[1].out_value = field1_out;
240 buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
241 fields[1].out_mask = NULL;
242 fields[1].in_value = NULL;
243 fields[1].in_check_value = NULL;
244 fields[1].in_check_mask = NULL;
245 fields[1].in_handler = NULL;
246 fields[1].in_handler_priv = NULL;
247
248 fields[2].device = ice_reg->jtag_info->chain_pos;
249 fields[2].num_bits = 1;
250 fields[2].out_value = field2_out;
251 buf_set_u32(fields[2].out_value, 0, 1, 0);
252 fields[2].out_mask = NULL;
253 fields[2].in_value = NULL;
254 fields[2].in_check_value = NULL;
255 fields[2].in_check_mask = NULL;
256 fields[2].in_handler = NULL;
257 fields[2].in_handler_priv = NULL;
258
259 jtag_add_dr_scan(3, fields, -1);
260
261 fields[0].in_value = reg->value;
262 jtag_set_check_value(fields+0, check_value, check_mask, NULL);
263
264 /* when reading the DCC data register, leaving the address field set to
265 * EICE_COMMS_DATA would read the register twice
266 * reading the control register is safe
267 */
268 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
269
270 jtag_add_dr_scan(3, fields, -1);
271
272 return ERROR_OK;
273 }
274
275 /* receive <size> words of 32 bit from the DCC
276 * we pretend the target is always going to be fast enough
277 * (relative to the JTAG clock), so we don't need to handshake
278 */
279 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
280 {
281 scan_field_t fields[3];
282 u8 field1_out[1];
283 u8 field2_out[1];
284
285 jtag_add_end_state(TAP_RTI);
286 arm_jtag_scann(jtag_info, 0x2);
287 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
288
289 fields[0].device = jtag_info->chain_pos;
290 fields[0].num_bits = 32;
291 fields[0].out_value = NULL;
292 fields[0].out_mask = NULL;
293 fields[0].in_value = NULL;
294 fields[0].in_check_value = NULL;
295 fields[0].in_check_mask = NULL;
296 fields[0].in_handler = NULL;
297 fields[0].in_handler_priv = NULL;
298
299 fields[1].device = jtag_info->chain_pos;
300 fields[1].num_bits = 5;
301 fields[1].out_value = field1_out;
302 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
303 fields[1].out_mask = NULL;
304 fields[1].in_value = NULL;
305 fields[1].in_check_value = NULL;
306 fields[1].in_check_mask = NULL;
307 fields[1].in_handler = NULL;
308 fields[1].in_handler_priv = NULL;
309
310 fields[2].device = jtag_info->chain_pos;
311 fields[2].num_bits = 1;
312 fields[2].out_value = field2_out;
313 buf_set_u32(fields[2].out_value, 0, 1, 0);
314 fields[2].out_mask = NULL;
315 fields[2].in_value = NULL;
316 fields[2].in_check_value = NULL;
317 fields[2].in_check_mask = NULL;
318 fields[2].in_handler = NULL;
319 fields[2].in_handler_priv = NULL;
320
321 jtag_add_dr_scan(3, fields, -1);
322
323 while (size > 0)
324 {
325 /* when reading the last item, set the register address to the DCC control reg,
326 * to avoid reading additional data from the DCC data reg
327 */
328 if (size == 1)
329 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
330
331 fields[0].in_handler = arm_jtag_buf_to_u32;
332 fields[0].in_handler_priv = data;
333 jtag_add_dr_scan(3, fields, -1);
334
335 data++;
336 size--;
337 }
338
339 return jtag_execute_queue();
340 }
341
342 int embeddedice_read_reg(reg_t *reg)
343 {
344 return embeddedice_read_reg_w_check(reg, NULL, NULL);
345 }
346
347 int embeddedice_set_reg(reg_t *reg, u32 value)
348 {
349 if (embeddedice_write_reg(reg, value) != ERROR_OK)
350 {
351 ERROR("BUG: error scheduling EmbeddedICE register write");
352 exit(-1);
353 }
354
355 buf_set_u32(reg->value, 0, reg->size, value);
356 reg->valid = 1;
357 reg->dirty = 0;
358
359 return ERROR_OK;
360 }
361
362 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
363 {
364 embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
365
366 if (jtag_execute_queue() != ERROR_OK)
367 {
368 ERROR("register write failed");
369 exit(-1);
370 }
371 return ERROR_OK;
372 }
373
374 int embeddedice_write_reg(reg_t *reg, u32 value)
375 {
376 embeddedice_reg_t *ice_reg = reg->arch_info;
377
378 DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
379
380 jtag_add_end_state(TAP_RTI);
381 arm_jtag_scann(ice_reg->jtag_info, 0x2);
382
383 arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
384
385 u8 reg_addr = ice_reg->addr & 0x1f;
386 embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
387
388 return ERROR_OK;
389 }
390
391 int embeddedice_store_reg(reg_t *reg)
392 {
393 return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
394 }
395
396 /* send <size> words of 32 bit to the DCC
397 * we pretend the target is always going to be fast enough
398 * (relative to the JTAG clock), so we don't need to handshake
399 */
400 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
401 {
402 scan_field_t fields[3];
403 u8 field0_out[4];
404 u8 field1_out[1];
405 u8 field2_out[1];
406
407 jtag_add_end_state(TAP_RTI);
408 arm_jtag_scann(jtag_info, 0x2);
409 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
410
411 fields[0].device = jtag_info->chain_pos;
412 fields[0].num_bits = 32;
413 fields[0].out_value = field0_out;
414 fields[0].out_mask = NULL;
415 fields[0].in_value = NULL;
416 fields[0].in_check_value = NULL;
417 fields[0].in_check_mask = NULL;
418 fields[0].in_handler = NULL;
419 fields[0].in_handler_priv = NULL;
420
421 fields[1].device = jtag_info->chain_pos;
422 fields[1].num_bits = 5;
423 fields[1].out_value = field1_out;
424 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
425 fields[1].out_mask = NULL;
426 fields[1].in_value = NULL;
427 fields[1].in_check_value = NULL;
428 fields[1].in_check_mask = NULL;
429 fields[1].in_handler = NULL;
430 fields[1].in_handler_priv = NULL;
431
432 fields[2].device = jtag_info->chain_pos;
433 fields[2].num_bits = 1;
434 fields[2].out_value = field2_out;
435 buf_set_u32(fields[2].out_value, 0, 1, 1);
436 fields[2].out_mask = NULL;
437 fields[2].in_value = NULL;
438 fields[2].in_check_value = NULL;
439 fields[2].in_check_mask = NULL;
440 fields[2].in_handler = NULL;
441 fields[2].in_handler_priv = NULL;
442
443 while (size > 0)
444 {
445 buf_set_u32(fields[0].out_value, 0, 32, *data);
446 jtag_add_dr_scan(3, fields, -1);
447
448 data++;
449 size--;
450 }
451
452 /* call to jtag_execute_queue() intentionally omitted */
453 return ERROR_OK;
454 }
455
456 /* wait for DCC control register R/W handshake bit to become active
457 */
458 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
459 {
460 scan_field_t fields[3];
461 u8 field0_in[4];
462 u8 field1_out[1];
463 u8 field2_out[1];
464 int retval;
465 int hsact;
466 struct timeval lap;
467 struct timeval now;
468
469 if (hsbit == EICE_COMM_CTRL_WBIT)
470 hsact = 1;
471 else if (hsbit == EICE_COMM_CTRL_RBIT)
472 hsact = 0;
473 else
474 return ERROR_INVALID_ARGUMENTS;
475
476 jtag_add_end_state(TAP_RTI);
477 arm_jtag_scann(jtag_info, 0x2);
478 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
479
480 fields[0].device = jtag_info->chain_pos;
481 fields[0].num_bits = 32;
482 fields[0].out_value = NULL;
483 fields[0].out_mask = NULL;
484 fields[0].in_value = field0_in;
485 fields[0].in_check_value = NULL;
486 fields[0].in_check_mask = NULL;
487 fields[0].in_handler = NULL;
488 fields[0].in_handler_priv = NULL;
489
490 fields[1].device = jtag_info->chain_pos;
491 fields[1].num_bits = 5;
492 fields[1].out_value = field1_out;
493 buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
494 fields[1].out_mask = NULL;
495 fields[1].in_value = NULL;
496 fields[1].in_check_value = NULL;
497 fields[1].in_check_mask = NULL;
498 fields[1].in_handler = NULL;
499 fields[1].in_handler_priv = NULL;
500
501 fields[2].device = jtag_info->chain_pos;
502 fields[2].num_bits = 1;
503 fields[2].out_value = field2_out;
504 buf_set_u32(fields[2].out_value, 0, 1, 0);
505 fields[2].out_mask = NULL;
506 fields[2].in_value = NULL;
507 fields[2].in_check_value = NULL;
508 fields[2].in_check_mask = NULL;
509 fields[2].in_handler = NULL;
510 fields[2].in_handler_priv = NULL;
511
512 jtag_add_dr_scan(3, fields, -1);
513 gettimeofday(&lap, NULL);
514 do
515 {
516 jtag_add_dr_scan(3, fields, -1);
517 if ((retval = jtag_execute_queue()) != ERROR_OK)
518 return retval;
519
520 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
521 return ERROR_OK;
522
523 gettimeofday(&now, NULL);
524 }
525 while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout);
526
527 return ERROR_TARGET_TIMEOUT;
528 }