src/target/dsp5680xx.h

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Rodrigo L. Rosa                                 *
   3  *   rodrigorosa.LG@gmail.com                                              *
   4  *                                                                         *
   5  *   Based on dsp563xx_once.h written by Mathias Kuester                   *
   6  *   mkdorg@users.sourceforge.net                                          *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  20  ***************************************************************************/
  21
  22 #ifndef OPENOCD_TARGET_DSP5680XX_H
  23 #define OPENOCD_TARGET_DSP5680XX_H
  24
  25 #include <jtag/jtag.h>
  26
  27 /**
  28  * @file   dsp5680xx.h
  29  * @author Rodrigo Rosa <rodrigorosa.LG@gmail.com>
  30  * @date   Thu Jun  9 18:54:38 2011
  31  *
  32  * @brief  Basic support for the 5680xx DSP from Freescale.
  33  * The chip has two taps in the JTAG chain, the Master tap and the Core tap.
  34  * In this code the Master tap is only used to unlock the flash memory by executing a JTAG instruction.
  35  *
  36  */
  37
  38 #define S_FILE_DATA_OFFSET 0x200000
  39 #define TIME_DIV_FREESCALE 0.3
  40
  41 /** ----------------------------------------------------------------
  42  * JTAG
  43  *----------------------------------------------------------------
  44  */
  45 #define DSP5680XX_JTAG_CORE_TAP_IRLEN   4
  46 #define DSP5680XX_JTAG_MASTER_TAP_IRLEN 8
  47
  48 #define JTAG_STATUS_MASK                0x0F
  49
  50 #define JTAG_STATUS_NORMAL              0x01
  51 #define JTAG_STATUS_STOPWAIT            0x05
  52 #define JTAG_STATUS_BUSY                0x09
  53 #define JTAG_STATUS_DEBUG               0x0D
  54 #define JTAG_STATUS_DEAD                0x0f
  55
  56 #define JTAG_INSTR_EXTEST               0x0
  57 #define JTAG_INSTR_SAMPLE_PRELOAD       0x1
  58 #define JTAG_INSTR_IDCODE               0x2
  59 #define JTAG_INSTR_EXTEST_PULLUP        0x3
  60 #define JTAG_INSTR_HIGHZ                0x4
  61 #define JTAG_INSTR_CLAMP                0x5
  62 #define JTAG_INSTR_ENABLE_ONCE          0x6
  63 #define JTAG_INSTR_DEBUG_REQUEST        0x7
  64 #define JTAG_INSTR_BYPASS               0xF
  65  /**
  66  * ----------------------------------------------------------------
  67  */
  68
  69 /** ----------------------------------------------------------------
  70  * Master TAP instructions from MC56F8000RM.pdf
  71  * ----------------------------------------------------------------
  72  */
  73 #define MASTER_TAP_CMD_BYPASS      0xF
  74 #define MASTER_TAP_CMD_IDCODE      0x2
  75 #define MASTER_TAP_CMD_TLM_SEL     0x5
  76 #define MASTER_TAP_CMD_FLASH_ERASE 0x8
  77  /**
  78  * ----------------------------------------------------------------
  79  */
  80
  81  /** ----------------------------------------------------------------
  82  * EOnCE control register info
  83  * ----------------------------------------------------------------
  84  */
  85 #define DSP5680XX_ONCE_OCR_EX   (1<<5)
  86 /* EX Bit Definition
  87    0 Remain in the Debug Processing State
  88    1 Leave the Debug Processing State */
  89 #define DSP5680XX_ONCE_OCR_GO   (1<<6)
  90 /* GO Bit Definition
  91    0 Inactive—No Action Taken
  92    1 Execute Controller Instruction */
  93 #define DSP5680XX_ONCE_OCR_RW   (1<<7)
  94 /** RW Bit Definition
  95  * 0 Write To the Register Specified by the RS[4:0] Bits
  96  * 1 ReadFrom the Register Specified by the RS[4:0] Bits
  97  * ----------------------------------------------------------------
  98  */
  99
 100  /** ----------------------------------------------------------------
 101  * EOnCE Status Register
 102  * ----------------------------------------------------------------
 103  */
 104 #define DSP5680XX_ONCE_OSCR_OS1  (1<<5)
 105 #define DSP5680XX_ONCE_OSCR_OS0  (1<<4)
 106  /**
 107  * ----------------------------------------------------------------
 108  */
 109
 110  /** ----------------------------------------------------------------
 111  * EOnCE Core Status - Describes the operating status of the core controller
 112  * ----------------------------------------------------------------
 113  */
 114 #define DSP5680XX_ONCE_OSCR_NORMAL_M    (0)
 115 /* 00  -   Normal      -   Controller Core Executing Instructions or in Reset */
 116 #define DSP5680XX_ONCE_OSCR_STOPWAIT_M  (DSP5680XX_ONCE_OSCR_OS0)
 117 /* 01  -   Stop/Wait   -   Controller Core in Stop or Wait Mode */
 118 #define DSP5680XX_ONCE_OSCR_BUSY_M      (DSP5680XX_ONCE_OSCR_OS1)
 119 /* 10  -   Busy -   Controller is Performing External or Peripheral Access (Wait States) */
 120 #define DSP5680XX_ONCE_OSCR_DEBUG_M     (DSP5680XX_ONCE_OSCR_OS0|DSP5680XX_ONCE_OSCR_OS1)
 121 /* 11  -   Debug       -   Controller Core Halted and in Debug Mode */
 122 #define EONCE_STAT_MASK 0x30
 123  /**
 124  * ----------------------------------------------------------------
 125  */
 126
 127  /** ----------------------------------------------------------------
 128  * Register Select Encoding (eonce_rev.1.0_0208081.pdf:14)
 129  * ----------------------------------------------------------------
 130  */
 131 #define DSP5680XX_ONCE_NOREG    0x00    /* No register selected */
 132 #define DSP5680XX_ONCE_OCR      0x01    /* OnCE Debug Control Register */
 133 #define DSP5680XX_ONCE_OCNTR    0x02    /* OnCE Breakpoint and Trace Counter */
 134 #define DSP5680XX_ONCE_OSR      0x03    /* EOnCE status register */
 135 #define DSP5680XX_ONCE_OBAR     0x04    /* OnCE Breakpoint Address Register */
 136 #define DSP5680XX_ONCE_OBASE    0x05    /* EOnCE Peripheral Base Address register */
 137 #define DSP5680XX_ONCE_OTXRXSR  0x06    /* EOnCE TXRX Status and Control Register (OTXRXSR)  */
 138 #define DSP5680XX_ONCE_OTX      0x07    /* EOnCE Transmit register (OTX)  */
 139 #define DSP5680XX_ONCE_OPDBR    0x08    /* EOnCE Program Data Bus Register (OPDBR) */
 140 #define DSP5680XX_ONCE_OTX1     0x09    /* EOnCE Upper Transmit register (OTX1) */
 141 #define DSP5680XX_ONCE_OPABFR   0x0A    /* OnCE Program Address Register—Fetch cycle */
 142 #define DSP5680XX_ONCE_ORX      0x0B    /* EOnCE Receive register (ORX) */
 143 #define DSP5680XX_ONCE_OCNTR_C  0x0C    /* Clear OCNTR */
 144 #define DSP5680XX_ONCE_ORX1     0x0D    /* EOnCE Upper Receive register (ORX1) */
 145 #define DSP5680XX_ONCE_OTBCR    0x0E    /* EOnCE Trace Buffer Control Reg (OTBCR) */
 146 #define DSP5680XX_ONCE_OPABER   0x10    /* OnCE Program Address Register—Execute cycle */
 147 #define DSP5680XX_ONCE_OPFIFO   0x11    /* OnCE Program address FIFO */
 148 #define DSP5680XX_ONCE_OBAR1    0x12    /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
 149 #define DSP5680XX_ONCE_OPABDR   0x13    /* OnCE Program Address Register—Decode cycle (OPABDR) */
 150  /**
 151  * ----------------------------------------------------------------
 152  */
 153
 154 #define FLUSH_COUNT_READ_WRITE 8192 /* This value works, higher values (and lower...) may work as well. */
 155 #define FLUSH_COUNT_FLASH 8192
 156 /** ----------------------------------------------------------------
 157  * HFM (flash module) Commands (ref:MC56F801xRM.pdf:159)
 158  * ----------------------------------------------------------------
 159  */
 160 #define HFM_ERASE_VERIFY                  0x05
 161 #define HFM_CALCULATE_DATA_SIGNATURE      0x06
 162 #define HFM_WORD_PROGRAM                  0x20
 163 #define HFM_PAGE_ERASE              0x40
 164 #define HFM_MASS_ERASE              0x41
 165 #define HFM_CALCULATE_IFR_BLOCK_SIGNATURE 0x66
 166  /**
 167  * ----------------------------------------------------------------
 168  */
 169
 170 /** ----------------------------------------------------------------
 171  * Flashing (ref:MC56F801xRM.pdf:159)
 172  * ----------------------------------------------------------------
 173  */
 174 #define HFM_BASE_ADDR     0x0F400   /** In x: mem. (write to S_FILE_DATA_OFFSET+HFM_BASE_ADDR
 175                                      * to get data into x: mem.)
 176                                      */
 177 /**
 178  * The following are register addresses, not memory
 179  * addresses (though all registers are memory mapped)
 180  */
 181 #define HFM_CLK_DIV       0x00  /* r/w */
 182 #define HFM_CNFG          0x01  /* r/w */
 183 #define HFM_SECHI        0x03  /* r */
 184 #define HFM_SECLO        0x04  /* r */
 185 #define HFM_PROT          0x10  /* r/w */
 186 #define HFM_PROTB        0x11  /* r/w */
 187 #define HFM_USTAT        0x13  /* r/w */
 188 #define HFM_CMD    0x14  /* r/w */
 189 #define HFM_DATA          0x18  /* r */
 190 #define HFM_OPT1          0x1B  /* r */
 191 #define HFM_TSTSIG      0x1D  /* r */
 192
 193 #define HFM_EXEC_COMPLETE  0x40
 194
 195 /* User status register (USTAT) masks (MC56F80XXRM.pdf:6.7.5) */
 196 #define HFM_USTAT_MASK_BLANK 0x4
 197 #define HFM_USTAT_MASK_PVIOL_ACCER 0x30
 198
 199 /**
 200  * The value used on for the FM clock is important to prevent flashing errors and to prevent deterioration of the FM.
 201  * This value was calculated using a spreadsheet tool available on the Freescale website under FAQ 25464.
 202  *
 203  */
 204 #define HFM_CLK_DEFAULT 0x27
 205 /* 0x27 according to freescale cfg, but 0x40 according to freescale spreadsheet... */
 206 #define HFM_FLASH_BASE_ADDR 0x0
 207 #define HFM_SIZE_BYTES 0x4000   /* bytes */
 208 #define HFM_SIZE_WORDS 0x2000   /* words */
 209 #define HFM_SECTOR_SIZE 0x200   /* Size in bytes */
 210 #define HFM_SECTOR_COUNT 0x20
 211 /* A 16K block in pages of 256 words. */
 212
 213 /**
 214  * Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset.
 215  */
 216 #define HFM_LOCK_FLASH 0xE70A
 217 #define HFM_LOCK_ADDR_L 0x1FF7
 218 #define HFM_LOCK_ADDR_H 0x1FF8
 219  /**
 220  * ----------------------------------------------------------------
 221  */
 222
 223 /** ----------------------------------------------------------------
 224  * Register Memory Map (eonce_rev.1.0_0208081.pdf:16)
 225  * ----------------------------------------------------------------
 226  */
 227 #define MC568013_EONCE_OBASE_ADDR 0xFF
 228 /* The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...) */
 229 #define MC568013_EONCE_TX_RX_ADDR    0xFFFE
 230 #define MC568013_EONCE_TX1_RX1_HIGH_ADDR  0xFFFF /* Relative to EONCE_OBASE_ADDR */
 231 #define MC568013_EONCE_OCR 0xFFA0   /* Relative to EONCE_OBASE_ADDR */
 232  /**
 233  * ----------------------------------------------------------------
 234  */
 235
 236 /** ----------------------------------------------------------------
 237  * SIM addresses & commands (MC56F80xx.h from freescale)
 238  * ----------------------------------------------------------------
 239  */
 240 #define MC568013_SIM_BASE_ADDR 0xF140
 241 #define MC56803x_2x_SIM_BASE_ADDR 0xF100
 242
 243 #define SIM_CMD_RESET 0x10
 244  /**
 245  * ----------------------------------------------------------------
 246  */
 247
 248 /**
 249  * ----------------------------------------------------------------
 250  * ERROR codes - enable automatic parsing of output
 251  * ----------------------------------------------------------------
 252  */
 253 #define DSP5680XX_ERROR_UNKNOWN_OR_ERROR_OPENOCD -100
 254 #define DSP5680XX_ERROR_JTAG_COMM -1
 255 #define DSP5680XX_ERROR_JTAG_RESET -2
 256 #define DSP5680XX_ERROR_JTAG_INVALID_TAP -3
 257 #define DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW -4
 258 #define DSP5680XX_ERROR_INVALID_IR_LEN -5
 259 #define DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER -6
 260 #define DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE -7
 261 #define DSP5680XX_ERROR_JTAG_TAP_FIND_MASTER -8
 262 #define DSP5680XX_ERROR_JTAG_TAP_FIND_CORE -9
 263 #define DSP5680XX_ERROR_JTAG_DRSCAN -10
 264 #define DSP5680XX_ERROR_JTAG_IRSCAN -11
 265 #define DSP5680XX_ERROR_ENTER_DEBUG_MODE -12
 266 #define DSP5680XX_ERROR_RESUME -13
 267 #define DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING -14
 268 #define DSP5680XX_ERROR_INVALID_DATA_SIZE_UNIT -15
 269 #define DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS -16
 270 #define DSP5680XX_ERROR_FM_BUSY -17
 271 #define DSP5680XX_ERROR_FM_CMD_TIMED_OUT -18
 272 #define DSP5680XX_ERROR_FM_EXEC -19
 273 #define DSP5680XX_ERROR_FM_SET_CLK -20
 274 #define DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT -21
 275 #define DSP5680XX_ERROR_FLASHING_CRC -22
 276 #define DSP5680XX_ERROR_FLASHING -23
 277 #define DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP -24
 278 #define DSP5680XX_ERROR_HALT -25
 279 #define DSP5680XX_ERROR_EXIT_DEBUG_MODE -26
 280 #define DSP5680XX_ERROR_TARGET_RUNNING -27
 281 #define DSP5680XX_ERROR_NOT_IN_DEBUG -28
 282 /**
 283  * ----------------------------------------------------------------
 284  */
 285
 286 struct dsp5680xx_common {
 287         uint32_t stored_pc;
 288         int flush;
 289         bool debug_mode_enabled;
 290 };
 291
 292 extern struct dsp5680xx_common dsp5680xx_context;
 293
 294 static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target
 295                                                            *target)
 296 {
 297         return target->arch_info;
 298 }
 299
 300 /**
 301  * Writes to flash memory.
 302  * Does not check if flash is erased, it's up to the user to erase the flash before running
 303  * this function.
 304  * The flashing algorithm runs from RAM, reading from a register to which this function
 305  * writes to. The algorithm is open loop, there is no control to verify that the FM read
 306  * the register before writing the next data. A closed loop approach was much slower,
 307  * and the current implementation does not fail, and if it did the crc check would detect it,
 308  * allowing to flash again.
 309  *
 310  * @param target
 311  * @param buffer
 312  * @param address Word addressing.
 313  * @param count In bytes.
 314  * @param is_flash_lock
 315  *
 316  * @return
 317  */
 318 int dsp5680xx_f_wr(struct target *target, const uint8_t * buffer, uint32_t address,
 319                 uint32_t count, int is_flash_lock);
 320
 321 /**
 322  * The FM has the functionality of checking if the flash array is erased. This function
 323  * executes it. It does not support individual sector analysis.
 324  *
 325  * @param target
 326  * @param erased
 327  * @param sector This parameter is ignored because the FM does not support checking if
 328  * individual sectors are erased.
 329  *
 330  * @return
 331  */
 332 int dsp5680xx_f_erase_check(struct target *target, uint8_t * erased,
 333                 uint32_t sector);
 334
 335 /**
 336  * Erases either a sector or the complete flash array. If either the range first-last covers
 337  * the complete array or if first == 0 and last == 0 then a mass erase command is executed
 338  * on the FM. If not, then individual sectors are erased.
 339  *
 340  * @param target
 341  * @param first
 342  * @param last
 343  *
 344  * @return
 345  */
 346 int dsp5680xx_f_erase(struct target *target, int first, int last);
 347
 348 /**
 349  * Reads the memory mapped protection register. A 1 implies the sector is protected,
 350  * a 0 implies the sector is not protected.
 351  *
 352  * @param target
 353  * @param protected Data read from the protection register.
 354  *
 355  * @return
 356  */
 357 int dsp5680xx_f_protect_check(struct target *target, uint16_t * protected);
 358
 359 /**
 360  * Writes the flash security words with a specific value. The chip's security will be
 361  * enabled after the first reset following the execution of this function.
 362  *
 363  * @param target
 364  *
 365  * @return
 366  */
 367 int dsp5680xx_f_lock(struct target *target);
 368
 369 /**
 370  * Executes a mass erase command. The must be done from the Master tap.
 371  * It is up to the user to select the master tap (jtag tapenable dsp5680xx.chp)
 372  * before running this function.
 373  * The flash array will be unsecured (and erased) after the first reset following
 374  * the execution of this function.
 375  *
 376  * @param target
 377  *
 378  * @return
 379  */
 380 int dsp5680xx_f_unlock(struct target *target);
 381
 382 #endif /* OPENOCD_TARGET_DSP5680XX_H */