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jtag: cut down on usage of unintended modification of global end state
[openocd.git] / src / target / dsp563xx.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Mathias Kuester *
3 * mkdorg@users.sourceforge.net *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include <helper/jim.h>
25
26 #include "target.h"
27 #include "target_type.h"
28 #include "register.h"
29 #include "dsp563xx.h"
30 #include "dsp563xx_once.h"
31
32 #define DSP563XX_JTAG_INS_LEN 4
33
34 #define JTAG_STATUS_NORMAL 0x01
35 #define JTAG_STATUS_STOPWAIT 0x05
36 #define JTAG_STATUS_BUSY 0x09
37 #define JTAG_STATUS_DEBUG 0x0d
38
39 #define JTAG_INSTR_EXTEST 0x00
40 #define JTAG_INSTR_SAMPLE_PRELOAD 0x01
41 #define JTAG_INSTR_IDCODE 0x02
42 #define JTAG_INSTR_CLAMP 0x03
43 #define JTAG_INSTR_HIZ 0x04
44 #define JTAG_INSTR_ENABLE_ONCE 0x06
45 #define JTAG_INSTR_DEBUG_REQUEST 0x07
46 #define JTAG_INSTR_BYPASS 0x0F
47
48 /* forward declarations */
49 int dsp563xx_target_create(struct target *target, Jim_Interp * interp);
50 int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target);
51
52 int dsp563xx_arch_state(struct target *target);
53 int dsp563xx_poll(struct target *target);
54 int dsp563xx_halt(struct target *target);
55 int dsp563xx_resume(struct target *target, int current, uint32_t address,
56 int handle_breakpoints, int debug_execution);
57 int dsp563xx_step(struct target *target, int current, uint32_t address,
58 int handle_breakpoints);
59
60 int dsp563xx_assert_reset(struct target *target);
61 int dsp563xx_deassert_reset(struct target *target);
62 int dsp563xx_soft_reset_halt(struct target *target);
63
64 /* IR and DR functions */
65 int dsp563xx_jtag_sendinstr(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out);
66 int dsp563xx_jtag_senddat(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out,
67 int len);
68
69 int dsp563xx_read_memory_p(struct target *target, uint32_t address, uint32_t size,
70 uint32_t count, uint8_t * buffer);
71 int dsp563xx_write_memory_p(struct target *target, uint32_t address, uint32_t size,
72 uint32_t count, uint8_t * buffer);
73
74 #define ASM_REG_R_R0 0x607000
75 #define ASM_REG_R_R1 0x617000
76 #define ASM_REG_R_R2 0x627000
77 #define ASM_REG_R_R3 0x637000
78 #define ASM_REG_R_R4 0x647000
79 #define ASM_REG_R_R5 0x657000
80 #define ASM_REG_R_R6 0x667000
81 #define ASM_REG_R_R7 0x677000
82
83 #define ASM_REG_W_R0 0x60F400
84 #define ASM_REG_W_R1 0x61F400
85 #define ASM_REG_W_R2 0x62F400
86 #define ASM_REG_W_R3 0x63F400
87 #define ASM_REG_W_R4 0x64F400
88 #define ASM_REG_W_R5 0x65F400
89 #define ASM_REG_W_R6 0x66F400
90 #define ASM_REG_W_R7 0x67F400
91
92 #define ASM_REG_R_N0 0x707000
93 #define ASM_REG_R_N1 0x717000
94 #define ASM_REG_R_N2 0x727000
95 #define ASM_REG_R_N3 0x737000
96 #define ASM_REG_R_N4 0x747000
97 #define ASM_REG_R_N5 0x757000
98 #define ASM_REG_R_N6 0x767000
99 #define ASM_REG_R_N7 0x777000
100
101 #define ASM_REG_W_N0 0x70F400
102 #define ASM_REG_W_N1 0x71F400
103 #define ASM_REG_W_N2 0x72F400
104 #define ASM_REG_W_N3 0x73F400
105 #define ASM_REG_W_N4 0x74F400
106 #define ASM_REG_W_N5 0x75F400
107 #define ASM_REG_W_N6 0x76F400
108 #define ASM_REG_W_N7 0x77F400
109
110 #define ASM_REG_R_M0 0x057020 /* control register m[0..7] */
111 #define ASM_REG_R_M1 0x057021
112 #define ASM_REG_R_M2 0x057022
113 #define ASM_REG_R_M3 0x057023
114 #define ASM_REG_R_M4 0x057024
115 #define ASM_REG_R_M5 0x057025
116 #define ASM_REG_R_M6 0x057026
117 #define ASM_REG_R_M7 0x057027
118
119 #define ASM_REG_W_M0 0x05F420
120 #define ASM_REG_W_M1 0x05F421
121 #define ASM_REG_W_M2 0x05F422
122 #define ASM_REG_W_M3 0x05F423
123 #define ASM_REG_W_M4 0x05F424
124 #define ASM_REG_W_M5 0x05F425
125 #define ASM_REG_W_M6 0x05F426
126 #define ASM_REG_W_M7 0x05F427
127
128 #define ASM_REG_R_X0 0x447000
129 #define ASM_REG_R_X1 0x457000
130
131 #define ASM_REG_W_X0 0x44F400
132 #define ASM_REG_W_X1 0x45F400
133
134 #define ASM_REG_R_Y0 0x467000
135 #define ASM_REG_R_Y1 0x477000
136
137 #define ASM_REG_W_Y0 0x46F400
138 #define ASM_REG_W_Y1 0x47F400
139
140 #define ASM_REG_R_A0 0x507000
141 #define ASM_REG_R_A1 0x547000
142 #define ASM_REG_R_A2 0x527000
143
144 #define ASM_REG_W_A0 0x50F400
145 #define ASM_REG_W_A1 0x54F400
146 #define ASM_REG_W_A2 0x52F400
147
148 #define ASM_REG_R_B0 0x517000
149 #define ASM_REG_R_B1 0x557000
150 #define ASM_REG_R_B2 0x537000
151
152 #define ASM_REG_W_B0 0x51F400
153 #define ASM_REG_W_B1 0x55F400
154 #define ASM_REG_W_B2 0x53F400
155
156 #define ASM_REG_R_VBA 0x057030 /* control register */
157 #define ASM_REG_W_VBA 0x05F430
158
159 #define ASM_REG_R_OMR 0x05703A /* control register */
160 #define ASM_REG_W_OMR 0x05F43A
161
162 #define ASM_REG_R_EP 0x05702A
163 #define ASM_REG_W_EP 0x05F42A
164
165 #define ASM_REG_R_SC 0x057031 /* stack counter */
166 #define ASM_REG_W_SC 0x05F431
167
168 #define ASM_REG_R_SZ 0x057038 /* stack size */
169 #define ASM_REG_W_SZ 0x05F438
170
171 #define ASM_REG_R_SR 0x057039 /* control register, status register */
172 #define ASM_REG_W_SR 0x05F439
173
174 #define ASM_REG_R_SP 0x05703B /* control register, stack pointer */
175 #define ASM_REG_W_SP 0x05F43B
176
177 #define ASM_REG_R_SSH 0x05703C /* control register, system stack high */
178 #define ASM_REG_W_SSH 0x05743C
179
180 #define ASM_REG_R_SSL 0x05703D /* control register, system stack low */
181 #define ASM_REG_W_SSL 0x05F43D
182
183 #define ASM_REG_R_LA 0x05703E /* control register, loop address */
184 #define ASM_REG_W_LA 0x05F43E
185
186 #define ASM_REG_R_LC 0x05703F /* control register, loop count */
187 #define ASM_REG_W_LC 0x05F43F
188
189 #define ASM_REG_R_PC 0x000000
190 #define ASM_REG_W_PC 0x000000
191
192 static const struct
193 {
194 unsigned id;
195 char *name;
196 unsigned bits;
197 uint32_t r_cmd;
198 uint32_t w_cmd;
199 } dsp563xx_regs[] =
200 {
201 /* *INDENT-OFF* */
202 {0, "r0", 24, ASM_REG_R_R0, ASM_REG_W_R0},
203 {1, "r1", 24, ASM_REG_R_R1, ASM_REG_W_R1},
204 {2, "r2", 24, ASM_REG_R_R2, ASM_REG_W_R2},
205 {3, "r3", 24, ASM_REG_R_R3, ASM_REG_W_R3},
206 {4, "r4", 24, ASM_REG_R_R4, ASM_REG_W_R4},
207 {5, "r5", 24, ASM_REG_R_R5, ASM_REG_W_R5},
208 {6, "r6", 24, ASM_REG_R_R6, ASM_REG_W_R6},
209 {7, "r7", 24, ASM_REG_R_R7, ASM_REG_W_R7},
210 {8, "n0", 24, ASM_REG_R_N0, ASM_REG_W_N0},
211 {9, "n1", 24, ASM_REG_R_N1, ASM_REG_W_N1},
212 {10, "n2", 24, ASM_REG_R_N2, ASM_REG_W_N2},
213 {11, "n3", 24, ASM_REG_R_N3, ASM_REG_W_N3},
214 {12, "n4", 24, ASM_REG_R_N4, ASM_REG_W_N4},
215 {13, "n5", 24, ASM_REG_R_N5, ASM_REG_W_N5},
216 {14, "n6", 24, ASM_REG_R_N6, ASM_REG_W_N6},
217 {15, "n7", 24, ASM_REG_R_N7, ASM_REG_W_N7},
218 {16, "m0", 24, ASM_REG_R_M0, ASM_REG_W_M0},
219 {17, "m1", 24, ASM_REG_R_M1, ASM_REG_W_M1},
220 {18, "m2", 24, ASM_REG_R_M2, ASM_REG_W_M2},
221 {19, "m3", 24, ASM_REG_R_M3, ASM_REG_W_M3},
222 {20, "m4", 24, ASM_REG_R_M4, ASM_REG_W_M4},
223 {21, "m5", 24, ASM_REG_R_M5, ASM_REG_W_M5},
224 {22, "m6", 24, ASM_REG_R_M6, ASM_REG_W_M6},
225 {23, "m7", 24, ASM_REG_R_M7, ASM_REG_W_M7},
226 {24, "x0", 24, ASM_REG_R_X0, ASM_REG_W_X0},
227 {25, "x1", 24, ASM_REG_R_X1, ASM_REG_W_X1},
228 {26, "y0", 24, ASM_REG_R_Y0, ASM_REG_W_Y0},
229 {27, "y1", 24, ASM_REG_R_Y1, ASM_REG_W_Y1},
230 {28, "a0", 24, ASM_REG_R_A0, ASM_REG_W_A0},
231 {29, "a1", 24, ASM_REG_R_A1, ASM_REG_W_A1},
232 {30, "a2", 8, ASM_REG_R_A2, ASM_REG_W_A2},
233 {31, "b0", 24, ASM_REG_R_B0, ASM_REG_W_B0},
234 {32, "b1", 24, ASM_REG_R_B1, ASM_REG_W_B1},
235 {33, "b2", 8, ASM_REG_R_B2, ASM_REG_W_B2},
236 {34, "omr", 24, ASM_REG_R_OMR, ASM_REG_W_OMR},
237 {35, "vba", 24, ASM_REG_R_VBA, ASM_REG_W_VBA},
238 {36, "ep", 24, ASM_REG_R_EP, ASM_REG_W_EP},
239 {37, "sc", 24, ASM_REG_R_SC, ASM_REG_W_SC},
240 {38, "sz", 24, ASM_REG_R_SZ, ASM_REG_W_SZ},
241 {39, "sr", 24, ASM_REG_R_SR, ASM_REG_W_SR},
242 {40, "sp", 24, ASM_REG_R_SP, ASM_REG_W_SP},
243 {41, "la", 24, ASM_REG_R_LA, ASM_REG_W_LA},
244 {42, "lc", 24, ASM_REG_R_LC, ASM_REG_W_LC},
245 {43, "pc", 24, ASM_REG_R_PC, ASM_REG_W_PC}
246 /* *INDENT-ON* */
247 };
248
249 static int dsp563xx_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
250 int *reg_list_size)
251 {
252 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
253 int i;
254
255 if (target->state != TARGET_HALTED)
256 {
257 return ERROR_TARGET_NOT_HALTED;
258 }
259
260 *reg_list_size = DSP563XX_NUMCOREREGS;
261 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
262
263 for (i = 0; i < DSP563XX_NUMCOREREGS; i++)
264 {
265 (*reg_list)[i] = &dsp563xx->core_cache->reg_list[i];
266 }
267
268 return ERROR_OK;
269
270 }
271
272 int dsp563xx_read_core_reg(struct target *target, int num)
273 {
274 uint32_t reg_value;
275 struct dsp563xx_core_reg *dsp563xx_core_reg;
276 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
277
278 if ((num < 0) || (num >= DSP563XX_NUMCOREREGS))
279 return ERROR_INVALID_ARGUMENTS;
280
281 dsp563xx_core_reg = dsp563xx->core_cache->reg_list[num].arch_info;
282 reg_value = dsp563xx->core_regs[num];
283 buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value);
284 dsp563xx->core_cache->reg_list[num].valid = 1;
285 dsp563xx->core_cache->reg_list[num].dirty = 0;
286
287 return ERROR_OK;
288 }
289
290 int dsp563xx_write_core_reg(struct target *target, int num)
291 {
292 uint32_t reg_value;
293 struct dsp563xx_core_reg *dsp563xx_core_reg;
294 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
295
296 if ((num < 0) || (num >= DSP563XX_NUMCOREREGS))
297 return ERROR_INVALID_ARGUMENTS;
298
299 reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32);
300 dsp563xx_core_reg = dsp563xx->core_cache->reg_list[num].arch_info;
301 dsp563xx->core_regs[num] = reg_value;
302 dsp563xx->core_cache->reg_list[num].valid = 1;
303 dsp563xx->core_cache->reg_list[num].dirty = 0;
304
305 return ERROR_OK;
306 }
307
308 int dsp563xx_target_create(struct target *target, Jim_Interp * interp)
309 {
310 struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common));
311
312 dsp563xx->jtag_info.tap = target->tap;
313 target->arch_info = dsp563xx;
314 dsp563xx->read_core_reg = dsp563xx_read_core_reg;
315 dsp563xx->write_core_reg = dsp563xx_write_core_reg;
316
317 return ERROR_OK;
318 }
319
320 int dsp563xx_get_core_reg(struct reg *reg)
321 {
322 int retval = 0;
323
324 LOG_DEBUG("%s", __FUNCTION__);
325
326 struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
327 struct target *target = dsp563xx_reg->target;
328 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
329
330 if (target->state != TARGET_HALTED)
331 {
332 return ERROR_TARGET_NOT_HALTED;
333 }
334
335 retval = dsp563xx->read_core_reg(target, dsp563xx_reg->num);
336
337 return retval;
338 }
339
340 int dsp563xx_set_core_reg(struct reg *reg, uint8_t * buf)
341 {
342 LOG_DEBUG("%s", __FUNCTION__);
343
344 struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
345 struct target *target = dsp563xx_reg->target;
346 uint32_t value = buf_get_u32(buf, 0, 32);
347
348 if (target->state != TARGET_HALTED)
349 {
350 return ERROR_TARGET_NOT_HALTED;
351 }
352
353 buf_set_u32(reg->value, 0, reg->size, value);
354 reg->dirty = 1;
355 reg->valid = 1;
356
357 return ERROR_OK;
358 }
359
360 int dsp563xx_save_context(struct target *target)
361 {
362 int i;
363 uint32_t data = 0;
364 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
365 struct dsp563xx_core_reg *arch_info;
366
367 for (i = 0; i < DSP563XX_NUMCOREREGS - 1; i++)
368 {
369
370 // if (!dsp563xx->core_cache->reg_list[i].valid)
371 {
372 arch_info = dsp563xx->core_cache->reg_list[i].arch_info;
373 dsp563xx_once_execute_dw_ir(target->tap, arch_info->r_cmd,
374 0xfffffc);
375 dsp563xx_once_execute_sw_ir(target->tap, 0x000000);
376 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OGDBR,
377 &data);
378 dsp563xx->core_regs[i] = data;
379 dsp563xx->read_core_reg(target, i);
380 }
381 }
382
383 /* read pc */
384 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABEX, &data);
385 dsp563xx->core_regs[i] = data;
386 dsp563xx->read_core_reg(target, i);
387
388 return ERROR_OK;
389 }
390
391 int dsp563xx_restore_context(struct target *target)
392 {
393 int i;
394 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
395 struct dsp563xx_core_reg *arch_info;
396
397 for (i = 0; i < DSP563XX_NUMCOREREGS - 1; i++)
398 {
399 if (dsp563xx->core_cache->reg_list[i].dirty)
400 {
401 arch_info = dsp563xx->core_cache->reg_list[i].arch_info;
402
403 dsp563xx->write_core_reg(target, i);
404
405 dsp563xx_once_execute_dw_ir(target->tap, arch_info->w_cmd,
406 dsp563xx->core_regs[i]);
407 dsp563xx_once_execute_sw_ir(target->tap, 0x000000);
408 }
409 }
410
411 return ERROR_OK;
412 }
413
414 static const struct reg_arch_type dsp563xx_reg_type = {
415 .get = dsp563xx_get_core_reg,
416 .set = dsp563xx_set_core_reg,
417 };
418
419 int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target)
420 {
421 /* get pointers to arch-specific information */
422 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
423
424 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
425 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
426 struct reg *reg_list = malloc(sizeof(struct reg) * DSP563XX_NUMCOREREGS);
427 struct dsp563xx_core_reg *arch_info =
428 malloc(sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS);
429 int i;
430
431 LOG_DEBUG("%s", __FUNCTION__);
432
433 /* Build the process context cache */
434 cache->name = "dsp563xx registers";
435 cache->next = NULL;
436 cache->reg_list = reg_list;
437 cache->num_regs = DSP563XX_NUMCOREREGS;
438 (*cache_p) = cache;
439 dsp563xx->core_cache = cache;
440
441 for (i = 0; i < DSP563XX_NUMCOREREGS; i++)
442 {
443 arch_info[i].num = dsp563xx_regs[i].id;
444 arch_info[i].name = dsp563xx_regs[i].name;
445 arch_info[i].size = dsp563xx_regs[i].bits;
446 arch_info[i].r_cmd = dsp563xx_regs[i].r_cmd;
447 arch_info[i].w_cmd = dsp563xx_regs[i].w_cmd;
448 arch_info[i].target = target;
449 arch_info[i].dsp563xx_common = dsp563xx;
450 reg_list[i].name = dsp563xx_regs[i].name;
451 reg_list[i].size = dsp563xx_regs[i].bits;
452 reg_list[i].value = calloc(1, 4);
453 reg_list[i].dirty = 0;
454 reg_list[i].valid = 0;
455 reg_list[i].type = &dsp563xx_reg_type;
456 reg_list[i].arch_info = &arch_info[i];
457 }
458
459 return ERROR_OK;
460 }
461
462 int dsp563xx_arch_state(struct target *target)
463 {
464 LOG_DEBUG("%s", __FUNCTION__);
465 return ERROR_OK;
466 }
467
468 int dsp563xx_jtag_status(struct target *target, uint8_t * status)
469 {
470 uint8_t ir_in;
471
472 ir_in = 0;
473
474 dsp563xx_jtag_sendinstr(target->tap, &ir_in, JTAG_INSTR_ENABLE_ONCE);
475 dsp563xx_execute_queue();
476
477 *status = ir_in;
478
479 return ERROR_OK;
480 }
481
482 int dsp563xx_jtag_debug_request(struct target *target)
483 {
484 uint8_t ir_in = 0;
485 uint32_t retry = 0;
486
487 while (ir_in != JTAG_STATUS_DEBUG)
488 {
489 dsp563xx_jtag_sendinstr(target->tap, &ir_in,
490 JTAG_INSTR_DEBUG_REQUEST);
491 dsp563xx_execute_queue();
492 LOG_DEBUG("JTAG CMD 7 res: %02X", ir_in);
493 dsp563xx_jtag_sendinstr(target->tap, &ir_in, JTAG_INSTR_ENABLE_ONCE);
494 dsp563xx_execute_queue();
495 LOG_DEBUG("JTAG CMD 6 res: %02X", ir_in);
496
497 if (retry++ == 100)
498 return ERROR_TARGET_FAILURE;
499 }
500
501 if (ir_in != JTAG_STATUS_DEBUG)
502 {
503 return ERROR_TARGET_FAILURE;
504 }
505
506 return ERROR_OK;
507 }
508
509 int dsp563xx_poll(struct target *target)
510 {
511 uint8_t jtag_status;
512 uint32_t once_status;
513
514 dsp563xx_jtag_status(target, &jtag_status);
515
516 if ((jtag_status & 1) != 1)
517 {
518 target->state = TARGET_UNKNOWN;
519 LOG_ERROR
520 ("jtag status contains invalid mode value - communication failure");
521 return ERROR_TARGET_FAILURE;
522 }
523
524 if (jtag_status != JTAG_STATUS_DEBUG)
525 {
526 target->state = TARGET_RUNNING;
527 }
528
529 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR, &once_status);
530
531 if ((once_status & DSP563XX_ONCE_OSCR_DEBUG_M) == DSP563XX_ONCE_OSCR_DEBUG_M)
532 {
533 target->state = TARGET_HALTED;
534
535 }
536
537 return ERROR_OK;
538 }
539
540 int dsp563xx_halt(struct target *target)
541 {
542 uint8_t jtag_status;
543 uint32_t once_status;
544 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
545
546 if (target->state == TARGET_HALTED)
547 {
548 LOG_DEBUG("target was already halted");
549 return ERROR_OK;
550 }
551
552 if (target->state == TARGET_UNKNOWN)
553 {
554 LOG_WARNING("target was in unknown state when halt was requested");
555 }
556
557 // if ( jtag_status != 0x0d )
558 {
559 dsp563xx_jtag_debug_request(target);
560
561 /* store pipeline register */
562 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPILR,
563 &dsp563xx->pipeline_context.once_opilr);
564 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPDBR,
565 &dsp563xx->pipeline_context.once_opdbr);
566
567 dsp563xx_save_context(target);
568
569 dsp563xx_jtag_status(target, &jtag_status);
570 LOG_DEBUG("%02X", jtag_status);
571 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR,
572 &once_status);
573 LOG_DEBUG("%02X", (unsigned) once_status);
574 }
575
576 LOG_DEBUG("target->state: %s", target_state_name(target));
577
578 LOG_DEBUG("%s", __FUNCTION__);
579
580 return ERROR_OK;
581 }
582
583 #define DSP563XX_ASM_CMD_JUMP 0x0AF080
584
585 int dsp563xx_resume(struct target *target, int current, uint32_t address,
586 int handle_breakpoints, int debug_execution)
587 {
588 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
589
590 LOG_DEBUG("%s", __FUNCTION__);
591
592 dsp563xx_restore_context(target);
593
594 if (current)
595 {
596 /* restore pipeline registers and go */
597 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPILR,
598 dsp563xx->pipeline_context.once_opilr);
599 dsp563xx_once_reg_write(target->tap,
600 DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX |
601 DSP563XX_ONCE_OCR_GO,
602 dsp563xx->pipeline_context.once_opdbr);
603 }
604 else
605 {
606 /* set to go register and jump */
607 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR,
608 DSP563XX_ASM_CMD_JUMP);
609 dsp563xx_once_reg_write(target->tap,
610 DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX
611 | DSP563XX_ONCE_OCR_GO, address);
612 }
613
614 target->state = TARGET_RUNNING;
615
616 return ERROR_OK;
617 }
618
619 int dsp563xx_step(struct target *target, int current, uint32_t address,
620 int handle_breakpoints)
621 {
622 uint32_t once_status;
623 uint32_t dr_in, cnt;
624 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
625
626 if (target->state != TARGET_HALTED)
627 {
628 LOG_DEBUG("target was not halted");
629 return ERROR_OK;
630 }
631
632 LOG_DEBUG("%s %08X %08X", __FUNCTION__, current, (unsigned) address);
633
634 dsp563xx_jtag_debug_request(target);
635
636 dsp563xx_restore_context(target);
637
638 /* reset trace mode */
639 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR, 0x000000);
640 /* enable trace mode */
641 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR,
642 DSP563XX_ONCE_OSCR_TME);
643
644 cnt = 0;
645
646 /* on JUMP we need one extra cycle */
647 if (!current)
648 cnt++;
649
650 /* load step counter with N-1 */
651 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OTC, cnt);
652
653 if (current)
654 {
655 /* restore pipeline registers and go */
656 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPILR,
657 dsp563xx->pipeline_context.once_opilr);
658 dsp563xx_once_reg_write(target->tap,
659 DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX |
660 DSP563XX_ONCE_OCR_GO,
661 dsp563xx->pipeline_context.once_opdbr);
662 }
663 else
664 {
665 /* set to go register and jump */
666 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR,
667 DSP563XX_ASM_CMD_JUMP);
668 dsp563xx_once_reg_write(target->tap,
669 DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX
670 | DSP563XX_ONCE_OCR_GO, address);
671 }
672
673 while (1)
674 {
675 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR,
676 &once_status);
677
678 if (once_status & DSP563XX_ONCE_OSCR_TO)
679 {
680 /* store pipeline register */
681 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPILR,
682 &dsp563xx->pipeline_context.
683 once_opilr);
684 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPDBR,
685 &dsp563xx->pipeline_context.
686 once_opdbr);
687
688 dsp563xx_save_context(target);
689
690 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABFR,
691 &dr_in);
692 LOG_DEBUG("%08X", (unsigned) dr_in);
693 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABDR,
694 &dr_in);
695 LOG_DEBUG("%08X", (unsigned) dr_in);
696 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABEX,
697 &dr_in);
698 LOG_DEBUG("%08X", (unsigned) dr_in);
699
700 /* reset trace mode */
701 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR,
702 0x000000);
703
704 break;
705 }
706 }
707
708 return ERROR_OK;
709 }
710
711 int dsp563xx_assert_reset(struct target *target)
712 {
713 target->state = TARGET_RESET;
714
715 LOG_DEBUG("%s", __FUNCTION__);
716 return ERROR_OK;
717 }
718
719 int dsp563xx_deassert_reset(struct target *target)
720 {
721 target->state = TARGET_RUNNING;
722
723 LOG_DEBUG("%s", __FUNCTION__);
724 return ERROR_OK;
725 }
726
727 int dsp563xx_soft_reset_halt(struct target *target)
728 {
729 LOG_DEBUG("%s", __FUNCTION__);
730 return ERROR_OK;
731 }
732
733 /*
734 * 000000 nop
735 * 46F400 AABBCC move #$aabbcc,y0
736 * 60F400 AABBCC move #$aabbcc,r0
737 * 467000 AABBCC move y0,x:AABBCC
738 * 607000 AABBCC move r0,x:AABBCC
739
740 * 46E000 move x:(r0),y0
741 * 4EE000 move y:(r0),y0
742 * 07E086 move p:(r0),y0
743
744 * 0450B9 move sr,r0
745 * 0446BA move omr,y0
746 * 0446BC move ssh,y0
747 * 0446BD move ssl,y0
748 * 0446BE move la,y0
749 * 0446BF move lc,y0
750 *
751 * 61F000 AABBCC move x:AABBCC,r1
752 * 076190 movem r0,p:(r1)
753 *
754 */
755 int dsp563xx_read_memory_p(struct target *target, uint32_t address,
756 uint32_t size, uint32_t count, uint8_t * buffer)
757 {
758 uint32_t i, x;
759 uint32_t data;
760 uint8_t *b;
761
762 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8"
763 PRIx32, address, size, count);
764
765 if (target->state != TARGET_HALTED)
766 {
767 LOG_WARNING("target not halted");
768 return ERROR_TARGET_NOT_HALTED;
769 }
770
771 x = count;
772
773 for (i = 0; i < x; i++)
774 {
775 dsp563xx_once_execute_dw_ir_nq(target->tap, 0x60F400, address + i);
776 dsp563xx_once_execute_sw_ir_nq(target->tap, 0x07E086);
777 dsp563xx_once_execute_dw_ir_nq(target->tap, 0x467000, 0xfffffc);
778 dsp563xx_execute_queue();
779
780 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OGDBR, &data);
781
782 b = buffer + 4 * i;
783 if (size > 0)
784 *b++ = data >> 0;
785 if (size > 1)
786 *b++ = data >> 8;
787 if (size > 2)
788 *b++ = data >> 16;
789 if (size > 3)
790 *b++ = 0x00;
791 }
792
793 return ERROR_OK;
794 }
795
796 int dsp563xx_write_memory_p(struct target *target, uint32_t address, uint32_t size,
797 uint32_t count, uint8_t * buffer)
798 {
799 uint32_t i, x;
800 uint32_t data;
801 uint8_t *b;
802
803 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8"
804 PRIx32 "", address, size, count);
805
806 if (target->state != TARGET_HALTED)
807 {
808 LOG_WARNING("target not halted");
809 return ERROR_TARGET_NOT_HALTED;
810 }
811
812 x = count;
813
814 for (i = 0; i < x; i++)
815 {
816 b = buffer + 4 * i;
817
818 data = 0;
819 if (size > 0)
820 data = *buffer++;
821 if (size > 1)
822 data |= (*buffer++) << 8;
823 if (size > 2)
824 data |= (*buffer++) << 16;
825 if (size > 3)
826 data |= (*buffer++) << 24;
827
828 // LOG_DEBUG("%08X", data);
829
830 dsp563xx_once_execute_dw_ir_nq(target->tap, 0x61F400, address + i);
831 dsp563xx_once_execute_dw_ir_nq(target->tap, 0x60F400, data);
832 dsp563xx_once_execute_sw_ir_nq(target->tap, 0x076190);
833 dsp563xx_execute_queue();
834 }
835
836 return ERROR_OK;
837 }
838
839 int dsp563xx_jtag_senddat(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out,
840 int len)
841 {
842 return dsp563xx_write_dr_u32(tap, dr_in, dr_out, len, 1);
843 }
844
845 int dsp563xx_jtag_sendinstr(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out)
846 {
847 return dsp563xx_write_ir_u8(tap, ir_in, ir_out, DSP563XX_JTAG_INS_LEN, 1);
848 }
849
850 /* IR and DR functions */
851 int dsp563xx_write_ir(struct jtag_tap *tap, uint8_t * ir_in, uint8_t * ir_out,
852 int ir_len, int rti)
853 {
854 if (NULL == tap)
855 {
856 LOG_ERROR("invalid tap");
857 return ERROR_FAIL;
858 }
859 if (ir_len != tap->ir_length)
860 {
861 LOG_ERROR("invalid ir_len");
862 return ERROR_FAIL;
863 }
864
865 {
866 jtag_add_plain_ir_scan(tap->ir_length, ir_out, ir_in, TAP_IDLE);
867 }
868
869 return ERROR_OK;
870 }
871
872 int dsp563xx_write_dr(struct jtag_tap *tap, uint8_t * dr_in, uint8_t * dr_out,
873 int dr_len, int rti)
874 {
875 if (NULL == tap)
876 {
877 LOG_ERROR("invalid tap");
878 return ERROR_FAIL;
879 }
880
881 {
882 jtag_add_plain_dr_scan(dr_len, dr_out, dr_in, TAP_IDLE);
883 }
884
885 return ERROR_OK;
886 }
887
888 int dsp563xx_write_ir_u8(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out,
889 int ir_len, int rti)
890 {
891 if (ir_len > 8)
892 {
893 LOG_ERROR("ir_len overflow, maxium is 8");
894 return ERROR_FAIL;
895 }
896
897 dsp563xx_write_ir(tap, ir_in, &ir_out, ir_len, rti);
898
899 return ERROR_OK;
900 }
901
902 int dsp563xx_write_dr_u8(struct jtag_tap *tap, uint8_t * dr_in, uint8_t dr_out,
903 int dr_len, int rti)
904 {
905 if (dr_len > 8)
906 {
907 LOG_ERROR("dr_len overflow, maxium is 8");
908 return ERROR_FAIL;
909 }
910
911 dsp563xx_write_dr(tap, dr_in, &dr_out, dr_len, rti);
912
913 return ERROR_OK;
914 }
915
916 int dsp563xx_write_ir_u16(struct jtag_tap *tap, uint16_t * ir_in, uint16_t ir_out,
917 int ir_len, int rti)
918 {
919 if (ir_len > 16)
920 {
921 LOG_ERROR("ir_len overflow, maxium is 16");
922 return ERROR_FAIL;
923 }
924
925 dsp563xx_write_ir(tap, (uint8_t *) ir_in, (uint8_t *) & ir_out, ir_len, rti);
926
927 return ERROR_OK;
928 }
929
930 int dsp563xx_write_dr_u16(struct jtag_tap *tap, uint16_t * dr_in, uint16_t dr_out,
931 int dr_len, int rti)
932 {
933 if (dr_len > 16)
934 {
935 LOG_ERROR("dr_len overflow, maxium is 16");
936 return ERROR_FAIL;
937 }
938
939 dsp563xx_write_dr(tap, (uint8_t *) dr_in, (uint8_t *) & dr_out, dr_len, rti);
940
941 return ERROR_OK;
942 }
943
944 int dsp563xx_write_ir_u32(struct jtag_tap *tap, uint32_t * ir_in, uint32_t ir_out,
945 int ir_len, int rti)
946 {
947 if (ir_len > 32)
948 {
949 LOG_ERROR("ir_len overflow, maxium is 32");
950 return ERROR_FAIL;
951 }
952
953 dsp563xx_write_ir(tap, (uint8_t *) ir_in, (uint8_t *) & ir_out, ir_len, rti);
954
955 return ERROR_OK;
956 }
957
958 int dsp563xx_write_dr_u32(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out,
959 int dr_len, int rti)
960 {
961 if (dr_len > 32)
962 {
963 LOG_ERROR("dr_len overflow, maxium is 32");
964 return ERROR_FAIL;
965 }
966
967 dsp563xx_write_dr(tap, (uint8_t *) dr_in, (uint8_t *) & dr_out, dr_len, rti);
968
969 return ERROR_OK;
970 }
971
972 int dsp563xx_execute_queue(void)
973 {
974 return jtag_execute_queue();
975 }
976
977 /** Holds methods for DSP563XX targets. */
978 struct target_type dsp563xx_target = {
979 .name = "dsp563xx",
980
981 .poll = dsp563xx_poll,
982 .arch_state = dsp563xx_arch_state,
983
984 .target_request_data = NULL,
985
986 .get_gdb_reg_list = dsp563xx_get_gdb_reg_list,
987
988 .halt = dsp563xx_halt,
989 .resume = dsp563xx_resume,
990 .step = dsp563xx_step,
991
992 .assert_reset = dsp563xx_assert_reset,
993 .deassert_reset = dsp563xx_deassert_reset,
994 .soft_reset_halt = dsp563xx_soft_reset_halt,
995
996 .read_memory = dsp563xx_read_memory_p,
997 .write_memory = dsp563xx_write_memory_p,
998
999 .target_create = dsp563xx_target_create,
1000 .init_target = dsp563xx_init_target,
1001 };
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