src/target/cortex_swjdp.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifndef CORTEX_SWJDP_H
  21 #define CORTEX_SWJDP_H
  22
  23 #include "target.h"
  24 #include "register.h"
  25 #include "arm_jtag.h"
  26
  27 #define SWJDP_IR_DPACC  0xA
  28 #define SWJDP_IR_APACC  0xB
  29
  30 #define DPAP_WRITE              0
  31 #define DPAP_READ               1
  32 #define DP_ZERO                 0
  33 #define DP_CTRL_STAT    0x4
  34 #define DP_SELECT       0x8
  35 #define DP_RDBUFF       0xC
  36
  37 #define CORUNDETECT     (1<<0)
  38 #define SSTICKYORUN     (1<<1)
  39 #define SSTICKYERR      (1<<5)
  40 #define CDBGRSTREQ      (1<<26)
  41 #define CDBGRSTACK      (1<<27)
  42 #define CDBGPWRUPREQ    (1<<28)
  43 #define CDBGPWRUPACK    (1<<29)
  44 #define CSYSPWRUPREQ    (1<<30)
  45 #define CSYSPWRUPACK    (1<<31)
  46
  47
  48
  49 #define AHBAP_CSW       0x00
  50 #define AHBAP_TAR       0x04
  51 #define AHBAP_DRW       0x0C
  52 #define AHBAP_BD0       0x10
  53 #define AHBAP_BD1       0x14
  54 #define AHBAP_BD2       0x18
  55 #define AHBAP_BD3       0x1C
  56 #define AHBAP_DBGROMA   0xF8
  57 #define AHBAP_IDR       0xFC
  58
  59
  60 #define CSW_8BIT                0
  61 #define CSW_16BIT               1
  62 #define CSW_32BIT               2
  63
  64 #define CSW_ADDRINC_MASK        (3<<4)
  65 #define CSW_ADDRINC_OFF         0
  66 #define CSW_ADDRINC_SINGLE      (1<<4)
  67 #define CSW_ADDRINC_PACKED      (2<<4)
  68 #define CSW_HPROT       (1<<25)
  69 #define CSW_MASTER_DEBUG        (1<<29)
  70 #define CSW_DBGSWENABLE (1<<31)
  71 #define TRANS_MODE_NONE 0
  72
  73 /* Transaction waits for previous to complete */
  74 #define TRANS_MODE_ATOMIC       1
  75 /* Freerunning transactions with delays and overrun checking */
  76 #define TRANS_MODE_COMPOSITE    2
  77
  78
  79 typedef struct swjdp_reg_s
  80 {
  81         int addr;
  82         arm_jtag_t *jtag_info;
  83 } swjdp_reg_t;
  84
  85 typedef struct swjdp_common_s
  86 {
  87         arm_jtag_t *jtag_info;
  88         /* Control config */
  89         u32 dp_ctrl_stat;
  90         /* Register select cache */
  91         u32 dp_select_value;
  92         u32 ap_csw_value;
  93         u32 ap_tar_value;
  94         u8  prev_ack;
  95         /* information about current pending SWjDP-AHBAP transaction */
  96         u8  trans_mode;
  97         u8  trans_rw;
  98         u8  ack;
  99         u32 * trans_value;
 100 } swjdp_common_t;
 101
 102 /* Internal functions used in the module, partial transactions, use with caution */
 103 extern int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
 104 //extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
 105 extern int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
 106 //extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
 107 extern int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf);
 108 extern int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf);
 109
 110 /* External interface, partial operations must be completed with swjdp_transaction_endcheck() */
 111 extern int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
 112 extern int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value);
 113 extern int swjdp_transaction_endcheck(swjdp_common_t *swjdp);
 114
 115
 116 /* External interface, complete atomic operations  */
 117 /* Host endian word transfer of single memory and system registers */
 118 extern int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
 119 extern int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value);
 120 /* Target endian (u8*) buffer transfers of blocks of memory and system registers */
 121 extern int ahbap_read_block(swjdp_common_t *swjdp, u8 *buffer, int bytecount, u32 address);
 122 extern int ahbap_write_block(swjdp_common_t *swjdp, u8 *buffer, int bytecount, u32 address);
 123 /* Host endian word transfers of processor core registers */
 124 extern int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum);
 125 extern int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum);
 126
 127 /* Initialisation of the debug system, power domains and registers */
 128 extern int ahbap_debugport_init(swjdp_common_t *swjdp);
 129
 130 #endif