- 16 and 32 bit unaligned accesses supported
[openocd.git] / src / target / cortex_m3.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifndef CORTEX_M3_H
24 #define CORTEX_M3_H
25
26 #include "register.h"
27 #include "target.h"
28 #include "armv7m.h"
29 #include "cortex_swjdp.h"
30
31 extern char* cortex_m3_state_strings[];
32
33 #define CORTEX_M3_COMMON_MAGIC 0x1A451A45
34
35 #define SYSTEM_CONTROL_BASE 0x400FE000
36
37 #define CPUID 0xE000ED00
38 /* Debug Control Block */
39 #define DCB_DHCSR 0xE000EDF0
40 #define DCB_DCRSR 0xE000EDF4
41 #define DCB_DCRDR 0xE000EDF8
42 #define DCB_DEMCR 0xE000EDFC
43
44 #define DCRSR_WnR (1<<16)
45
46 #define DWT_CTRL 0xE0001000
47 #define DWT_COMP0 0xE0001020
48 #define DWT_MASK0 0xE0001024
49 #define DWT_FUNCTION0 0xE0001028
50
51 #define FP_CTRL 0xE0002000
52 #define FP_REMAP 0xE0002004
53 #define FP_COMP0 0xE0002008
54 #define FP_COMP1 0xE000200C
55 #define FP_COMP2 0xE0002010
56 #define FP_COMP3 0xE0002014
57 #define FP_COMP4 0xE0002018
58 #define FP_COMP5 0xE000201C
59 #define FP_COMP6 0xE0002020
60 #define FP_COMP7 0xE0002024
61
62 #define DWT_CTRL 0xE0001000
63
64 /* DCB_DHCSR bit and field definitions */
65 #define DBGKEY (0xA05F<<16)
66 #define C_DEBUGEN (1<<0)
67 #define C_HALT (1<<1)
68 #define C_STEP (1<<2)
69 #define C_MASKINTS (1<<3)
70 #define S_REGRDY (1<<16)
71 #define S_HALT (1<<17)
72 #define S_SLEEP (1<<18)
73 #define S_LOCKUP (1<<19)
74 #define S_RETIRE_ST (1<<24)
75 #define S_RESET_ST (1<<25)
76
77 /* DCB_DEMCR bit and field definitions */
78 #define TRCENA (1<<24)
79 #define VC_HARDERR (1<<10)
80 #define VC_BUSERR (1<<8)
81 #define VC_CORERESET (1<<0)
82
83 #define NVIC_ICTR 0xE000E004
84 #define NVIC_ISE0 0xE000E100
85 #define NVIC_ICSR 0xE000ED04
86 #define NVIC_AIRCR 0xE000ED0C
87 #define NVIC_SHCSR 0xE000ED24
88 #define NVIC_CFSR 0xE000ED28
89 #define NVIC_MMFSRb 0xE000ED28
90 #define NVIC_BFSRb 0xE000ED29
91 #define NVIC_USFSRh 0xE000ED2A
92 #define NVIC_HFSR 0xE000ED2C
93 #define NVIC_DFSR 0xE000ED30
94 #define NVIC_MMFAR 0xE000ED34
95 #define NVIC_BFAR 0xE000ED38
96
97 /* NVIC_AIRCR bits */
98 #define AIRCR_VECTKEY (0x5FA<<16)
99 #define AIRCR_SYSRESETREQ (1<<2)
100 #define AIRCR_VECTCLRACTIVE (1<<1)
101 #define AIRCR_VECTRESET (1<<0)
102 /* NVIC_SHCSR bits */
103 #define SHCSR_BUSFAULTENA (1<<17)
104 /* NVIC_DFSR bits */
105 #define DFSR_HALTED 1
106 #define DFSR_BKPT 2
107 #define DFSR_DWTTRAP 4
108 #define DFSR_VCATCH 8
109
110 #define FPCR_CODE 0
111 #define FPCR_LITERAL 1
112 #define FPCR_REPLACE_REMAP (0<<30)
113 #define FPCR_REPLACE_BKPT_LOW (1<<30)
114 #define FPCR_REPLACE_BKPT_HIGH (2<<30)
115 #define FPCR_REPLACE_BKPT_BOTH (3<<30)
116
117 typedef struct cortex_m3_fp_comparator_s
118 {
119 int used;
120 int type;
121 u32 fpcr_value;
122 u32 fpcr_address;
123 } cortex_m3_fp_comparator_t;
124
125 typedef struct cortex_m3_dwt_comparator_s
126 {
127 int used;
128 u32 comp;
129 u32 mask;
130 u32 function;
131 u32 dwt_comparator_address;
132 } cortex_m3_dwt_comparator_t;
133
134 typedef struct cortex_m3_common_s
135 {
136 int common_magic;
137
138 arm_jtag_t jtag_info;
139
140 /* Context information */
141 u32 dcb_dhcsr;
142 u32 nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
143 u32 nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
144
145 /* Flash Patch and Breakpoint */
146 int fp_num_lit;
147 int fp_num_code;
148 int fp_code_available;
149 int auto_bp_type;
150 cortex_m3_fp_comparator_t *fp_comparator_list;
151
152 /* DWT */
153 int dwt_num_comp;
154 int dwt_comp_available;
155 cortex_m3_dwt_comparator_t *dwt_comparator_list;
156
157 /* Interrupts */
158 int intlinesnum;
159 u32 *intsetenable;
160
161 armv7m_common_t armv7m;
162 swjdp_common_t swjdp_info;
163 void *arch_info;
164 } cortex_m3_common_t;
165
166 extern void cortex_m3_build_reg_cache(target_t *target);
167
168 int cortex_m3_poll(target_t *target);
169 int cortex_m3_halt(target_t *target);
170 int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
171 int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
172
173 int cortex_m3_assert_reset(target_t *target);
174 int cortex_m3_deassert_reset(target_t *target);
175 int cortex_m3_soft_reset_halt(struct target_s *target);
176 int cortex_m3_prepare_reset_halt(struct target_s *target);
177
178 int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
179 int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
180 int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
181
182 int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
183 int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
184 int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
185 int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
186 int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
187 int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
188
189 extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
190 extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, char *variant);
191
192 #endif /* CORTEX_M3_H */