ae772543bff78b223838b6f94e13365fd1672375
[openocd.git] / src / target / cortex_m3.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef CORTEX_M3_H
27 #define CORTEX_M3_H
28
29 #include "register.h"
30 #include "target.h"
31 #include "armv7m.h"
32 //#include "arm_adi_v5.h"
33
34 extern char* cortex_m3_state_strings[];
35
36 #define CORTEX_M3_COMMON_MAGIC 0x1A451A45
37
38 #define SYSTEM_CONTROL_BASE 0x400FE000
39
40 #define CPUID 0xE000ED00
41 /* Debug Control Block */
42 #define DCB_DHCSR 0xE000EDF0
43 #define DCB_DCRSR 0xE000EDF4
44 #define DCB_DCRDR 0xE000EDF8
45 #define DCB_DEMCR 0xE000EDFC
46
47 #define DCRSR_WnR (1<<16)
48
49 #define DWT_CTRL 0xE0001000
50 #define DWT_COMP0 0xE0001020
51 #define DWT_MASK0 0xE0001024
52 #define DWT_FUNCTION0 0xE0001028
53
54 #define FP_CTRL 0xE0002000
55 #define FP_REMAP 0xE0002004
56 #define FP_COMP0 0xE0002008
57 #define FP_COMP1 0xE000200C
58 #define FP_COMP2 0xE0002010
59 #define FP_COMP3 0xE0002014
60 #define FP_COMP4 0xE0002018
61 #define FP_COMP5 0xE000201C
62 #define FP_COMP6 0xE0002020
63 #define FP_COMP7 0xE0002024
64
65 #define DWT_CTRL 0xE0001000
66
67 /* DCB_DHCSR bit and field definitions */
68 #define DBGKEY (0xA05F<<16)
69 #define C_DEBUGEN (1<<0)
70 #define C_HALT (1<<1)
71 #define C_STEP (1<<2)
72 #define C_MASKINTS (1<<3)
73 #define S_REGRDY (1<<16)
74 #define S_HALT (1<<17)
75 #define S_SLEEP (1<<18)
76 #define S_LOCKUP (1<<19)
77 #define S_RETIRE_ST (1<<24)
78 #define S_RESET_ST (1<<25)
79
80 /* DCB_DEMCR bit and field definitions */
81 #define TRCENA (1<<24)
82 #define VC_HARDERR (1<<10)
83 #define VC_BUSERR (1<<8)
84 #define VC_CORERESET (1<<0)
85
86 #define NVIC_ICTR 0xE000E004
87 #define NVIC_ISE0 0xE000E100
88 #define NVIC_ICSR 0xE000ED04
89 #define NVIC_AIRCR 0xE000ED0C
90 #define NVIC_SHCSR 0xE000ED24
91 #define NVIC_CFSR 0xE000ED28
92 #define NVIC_MMFSRb 0xE000ED28
93 #define NVIC_BFSRb 0xE000ED29
94 #define NVIC_USFSRh 0xE000ED2A
95 #define NVIC_HFSR 0xE000ED2C
96 #define NVIC_DFSR 0xE000ED30
97 #define NVIC_MMFAR 0xE000ED34
98 #define NVIC_BFAR 0xE000ED38
99
100 /* NVIC_AIRCR bits */
101 #define AIRCR_VECTKEY (0x5FA<<16)
102 #define AIRCR_SYSRESETREQ (1<<2)
103 #define AIRCR_VECTCLRACTIVE (1<<1)
104 #define AIRCR_VECTRESET (1<<0)
105 /* NVIC_SHCSR bits */
106 #define SHCSR_BUSFAULTENA (1<<17)
107 /* NVIC_DFSR bits */
108 #define DFSR_HALTED 1
109 #define DFSR_BKPT 2
110 #define DFSR_DWTTRAP 4
111 #define DFSR_VCATCH 8
112
113 #define FPCR_CODE 0
114 #define FPCR_LITERAL 1
115 #define FPCR_REPLACE_REMAP (0<<30)
116 #define FPCR_REPLACE_BKPT_LOW (1<<30)
117 #define FPCR_REPLACE_BKPT_HIGH (2<<30)
118 #define FPCR_REPLACE_BKPT_BOTH (3<<30)
119
120 typedef struct cortex_m3_fp_comparator_s
121 {
122 int used;
123 int type;
124 uint32_t fpcr_value;
125 uint32_t fpcr_address;
126 } cortex_m3_fp_comparator_t;
127
128 typedef struct cortex_m3_dwt_comparator_s
129 {
130 int used;
131 uint32_t comp;
132 uint32_t mask;
133 uint32_t function;
134 uint32_t dwt_comparator_address;
135 } cortex_m3_dwt_comparator_t;
136
137 typedef struct cortex_m3_common_s
138 {
139 int common_magic;
140 arm_jtag_t jtag_info;
141
142 /* Context information */
143 uint32_t dcb_dhcsr;
144 uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
145 uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
146
147 /* Flash Patch and Breakpoint (FPB) */
148 int fp_num_lit;
149 int fp_num_code;
150 int fp_code_available;
151 int fpb_enabled;
152 int auto_bp_type;
153 cortex_m3_fp_comparator_t *fp_comparator_list;
154
155 /* Data Watchpoint and Trace (DWT) */
156 int dwt_num_comp;
157 int dwt_comp_available;
158 cortex_m3_dwt_comparator_t *dwt_comparator_list;
159
160 /* Interrupts */
161 int intlinesnum;
162 uint32_t *intsetenable;
163
164 armv7m_common_t armv7m;
165 // swjdp_common_t swjdp_info;
166 void *arch_info;
167 } cortex_m3_common_t;
168
169 extern void cortex_m3_build_reg_cache(target_t *target);
170
171 int cortex_m3_poll(target_t *target);
172 int cortex_m3_halt(target_t *target);
173 int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
174 int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
175
176 int cortex_m3_assert_reset(target_t *target);
177 int cortex_m3_deassert_reset(target_t *target);
178 int cortex_m3_soft_reset_halt(struct target_s *target);
179
180 int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
181 int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
182 int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
183
184 int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
185 int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
186 int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
187 int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
188 int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
189 int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
190
191 //extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
192 extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
193
194 #endif /* CORTEX_M3_H */