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Cortex-M3: don't chain "struct arm" commands
[openocd.git] / src / target / cortex_m3.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 * *
26 * *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
28 * *
29 ***************************************************************************/
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
39 #include "register.h"
40
41
42 /* NOTE: most of this should work fine for the Cortex-M1 and
43 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
44 */
45
46
47 /* forward declarations */
48 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
49 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
50 static void cortex_m3_enable_watchpoints(struct target *target);
51 static int cortex_m3_store_core_reg_u32(struct target *target,
52 enum armv7m_regtype type, uint32_t num, uint32_t value);
53
54 #ifdef ARMV7_GDB_HACKS
55 extern uint8_t armv7m_gdb_dummy_cpsr_value[];
56 extern struct reg armv7m_gdb_dummy_cpsr_reg;
57 #endif
58
59 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
60 uint32_t *value, int regnum)
61 {
62 int retval;
63 uint32_t dcrdr;
64
65 /* because the DCB_DCRDR is used for the emulated dcc channel
66 * we have to save/restore the DCB_DCRDR when used */
67
68 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
69
70 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
71
72 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
73 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
74 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
75
76 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
77 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
78 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
79
80 retval = swjdp_transaction_endcheck(swjdp);
81
82 /* restore DCB_DCRDR - this needs to be in a seperate
83 * transaction otherwise the emulated DCC channel breaks */
84 if (retval == ERROR_OK)
85 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
86
87 return retval;
88 }
89
90 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
91 uint32_t value, int regnum)
92 {
93 int retval;
94 uint32_t dcrdr;
95
96 /* because the DCB_DCRDR is used for the emulated dcc channel
97 * we have to save/restore the DCB_DCRDR when used */
98
99 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
100
101 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
102
103 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
104 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
105 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
106
107 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
108 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
109 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
110
111 retval = swjdp_transaction_endcheck(swjdp);
112
113 /* restore DCB_DCRDR - this needs to be in a seperate
114 * transaction otherwise the emulated DCC channel breaks */
115 if (retval == ERROR_OK)
116 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
117
118 return retval;
119 }
120
121 static int cortex_m3_write_debug_halt_mask(struct target *target,
122 uint32_t mask_on, uint32_t mask_off)
123 {
124 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
125 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
126
127 /* mask off status bits */
128 cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
129 /* create new register mask */
130 cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
131
132 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
133 }
134
135 static int cortex_m3_clear_halt(struct target *target)
136 {
137 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
138 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
139
140 /* clear step if any */
141 cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
142
143 /* Read Debug Fault Status Register */
144 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
145 /* Clear Debug Fault Status */
146 mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
147 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
148
149 return ERROR_OK;
150 }
151
152 static int cortex_m3_single_step_core(struct target *target)
153 {
154 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
155 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
156 uint32_t dhcsr_save;
157
158 /* backup dhcsr reg */
159 dhcsr_save = cortex_m3->dcb_dhcsr;
160
161 /* mask interrupts if not done already */
162 if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
163 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
164 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
165 LOG_DEBUG(" ");
166
167 /* restore dhcsr reg */
168 cortex_m3->dcb_dhcsr = dhcsr_save;
169 cortex_m3_clear_halt(target);
170
171 return ERROR_OK;
172 }
173
174 static int cortex_m3_endreset_event(struct target *target)
175 {
176 int i;
177 uint32_t dcb_demcr;
178 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
179 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
180 struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
181 struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
182
183 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
184 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
185
186 /* this regsiter is used for emulated dcc channel */
187 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
188
189 /* Enable debug requests */
190 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
191 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
192 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
193
194 /* clear any interrupt masking */
195 cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
196
197 /* Enable trace and dwt */
198 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
199 /* Monitor bus faults */
200 mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
201
202 /* Enable FPB */
203 target_write_u32(target, FP_CTRL, 3);
204 cortex_m3->fpb_enabled = 1;
205
206 /* Restore FPB registers */
207 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
208 {
209 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
210 }
211
212 /* Restore DWT registers */
213 for (i = 0; i < cortex_m3->dwt_num_comp; i++)
214 {
215 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
216 dwt_list[i].comp);
217 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
218 dwt_list[i].mask);
219 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
220 dwt_list[i].function);
221 }
222 swjdp_transaction_endcheck(swjdp);
223
224 register_cache_invalidate(cortex_m3->armv7m.core_cache);
225
226 /* make sure we have latest dhcsr flags */
227 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
228
229 return ERROR_OK;
230 }
231
232 static int cortex_m3_examine_debug_reason(struct target *target)
233 {
234 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
235
236 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
237 /* only check the debug reason if we don't know it already */
238
239 if ((target->debug_reason != DBG_REASON_DBGRQ)
240 && (target->debug_reason != DBG_REASON_SINGLESTEP))
241 {
242 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
243 {
244 target->debug_reason = DBG_REASON_BREAKPOINT;
245 if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
246 target->debug_reason = DBG_REASON_WPTANDBKPT;
247 }
248 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
249 target->debug_reason = DBG_REASON_WATCHPOINT;
250 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
251 target->debug_reason = DBG_REASON_BREAKPOINT;
252 else /* EXTERNAL, HALTED */
253 target->debug_reason = DBG_REASON_UNDEFINED;
254 }
255
256 return ERROR_OK;
257 }
258
259 static int cortex_m3_examine_exception_reason(struct target *target)
260 {
261 uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
262 struct armv7m_common *armv7m = target_to_armv7m(target);
263 struct swjdp_common *swjdp = &armv7m->swjdp_info;
264
265 mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
266 switch (armv7m->exception_number)
267 {
268 case 2: /* NMI */
269 break;
270 case 3: /* Hard Fault */
271 mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
272 if (except_sr & 0x40000000)
273 {
274 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
275 }
276 break;
277 case 4: /* Memory Management */
278 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
279 mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
280 break;
281 case 5: /* Bus Fault */
282 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
283 mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
284 break;
285 case 6: /* Usage Fault */
286 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
287 break;
288 case 11: /* SVCall */
289 break;
290 case 12: /* Debug Monitor */
291 mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
292 break;
293 case 14: /* PendSV */
294 break;
295 case 15: /* SysTick */
296 break;
297 default:
298 except_sr = 0;
299 break;
300 }
301 swjdp_transaction_endcheck(swjdp);
302 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
303 shcsr, except_sr, cfsr, except_ar);
304 return ERROR_OK;
305 }
306
307 static int cortex_m3_debug_entry(struct target *target)
308 {
309 int i;
310 uint32_t xPSR;
311 int retval;
312 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
313 struct armv7m_common *armv7m = &cortex_m3->armv7m;
314 struct swjdp_common *swjdp = &armv7m->swjdp_info;
315
316 LOG_DEBUG(" ");
317
318 cortex_m3_clear_halt(target);
319 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
320
321 if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
322 return retval;
323
324 /* Examine target state and mode */
325 /* First load register acessible through core debug port*/
326 int num_regs = armv7m->core_cache->num_regs;
327
328 for (i = 0; i < num_regs; i++)
329 {
330 if (!armv7m->core_cache->reg_list[i].valid)
331 armv7m->read_core_reg(target, i);
332 }
333
334 xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
335
336 #ifdef ARMV7_GDB_HACKS
337 /* FIXME this breaks on scan chains with more than one Cortex-M3.
338 * Instead, each CM3 should have its own dummy value...
339 */
340 /* copy real xpsr reg for gdb, setting thumb bit */
341 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
342 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
343 armv7m_gdb_dummy_cpsr_reg.valid = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
344 armv7m_gdb_dummy_cpsr_reg.dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty;
345 #endif
346
347 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
348 if (xPSR & 0xf00)
349 {
350 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
351 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
352 }
353
354 /* Are we in an exception handler */
355 if (xPSR & 0x1FF)
356 {
357 armv7m->core_mode = ARMV7M_MODE_HANDLER;
358 armv7m->exception_number = (xPSR & 0x1FF);
359 }
360 else
361 {
362 armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
363 armv7m->exception_number = 0;
364 }
365
366 if (armv7m->exception_number)
367 {
368 cortex_m3_examine_exception_reason(target);
369 }
370
371 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
372 armv7m_mode_strings[armv7m->core_mode],
373 *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
374 target_state_name(target));
375
376 if (armv7m->post_debug_entry)
377 armv7m->post_debug_entry(target);
378
379 return ERROR_OK;
380 }
381
382 static int cortex_m3_poll(struct target *target)
383 {
384 int retval;
385 enum target_state prev_target_state = target->state;
386 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
387 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
388
389 /* Read from Debug Halting Control and Status Register */
390 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
391 if (retval != ERROR_OK)
392 {
393 target->state = TARGET_UNKNOWN;
394 return retval;
395 }
396
397 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
398 {
399 /* check if still in reset */
400 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
401
402 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
403 {
404 target->state = TARGET_RESET;
405 return ERROR_OK;
406 }
407 }
408
409 if (target->state == TARGET_RESET)
410 {
411 /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
412 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32 "", cortex_m3->dcb_dhcsr);
413 cortex_m3_endreset_event(target);
414 target->state = TARGET_RUNNING;
415 prev_target_state = TARGET_RUNNING;
416 }
417
418 if (cortex_m3->dcb_dhcsr & S_HALT)
419 {
420 target->state = TARGET_HALTED;
421
422 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
423 {
424 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
425 return retval;
426
427 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
428 }
429 if (prev_target_state == TARGET_DEBUG_RUNNING)
430 {
431 LOG_DEBUG(" ");
432 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
433 return retval;
434
435 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
436 }
437 }
438
439 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
440 * How best to model low power modes?
441 */
442
443 if (target->state == TARGET_UNKNOWN)
444 {
445 /* check if processor is retiring instructions */
446 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
447 {
448 target->state = TARGET_RUNNING;
449 return ERROR_OK;
450 }
451 }
452
453 return ERROR_OK;
454 }
455
456 static int cortex_m3_halt(struct target *target)
457 {
458 LOG_DEBUG("target->state: %s",
459 target_state_name(target));
460
461 if (target->state == TARGET_HALTED)
462 {
463 LOG_DEBUG("target was already halted");
464 return ERROR_OK;
465 }
466
467 if (target->state == TARGET_UNKNOWN)
468 {
469 LOG_WARNING("target was in unknown state when halt was requested");
470 }
471
472 if (target->state == TARGET_RESET)
473 {
474 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
475 {
476 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
477 return ERROR_TARGET_FAILURE;
478 }
479 else
480 {
481 /* we came here in a reset_halt or reset_init sequence
482 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
483 */
484 target->debug_reason = DBG_REASON_DBGRQ;
485
486 return ERROR_OK;
487 }
488 }
489
490 /* Write to Debug Halting Control and Status Register */
491 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
492
493 target->debug_reason = DBG_REASON_DBGRQ;
494
495 return ERROR_OK;
496 }
497
498 static int cortex_m3_soft_reset_halt(struct target *target)
499 {
500 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
501 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
502 uint32_t dcb_dhcsr = 0;
503 int retval, timeout = 0;
504
505 /* Enter debug state on reset, cf. end_reset_event() */
506 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
507
508 /* Request a reset */
509 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
510 target->state = TARGET_RESET;
511
512 /* registers are now invalid */
513 register_cache_invalidate(cortex_m3->armv7m.core_cache);
514
515 while (timeout < 100)
516 {
517 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
518 if (retval == ERROR_OK)
519 {
520 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
521 if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
522 {
523 LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32 ", nvic_dfsr 0x%" PRIx32 "", dcb_dhcsr, cortex_m3->nvic_dfsr);
524 cortex_m3_poll(target);
525 return ERROR_OK;
526 }
527 else
528 LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32 ", %i ms", dcb_dhcsr, timeout);
529 }
530 timeout++;
531 alive_sleep(1);
532 }
533
534 return ERROR_OK;
535 }
536
537 static void cortex_m3_enable_breakpoints(struct target *target)
538 {
539 struct breakpoint *breakpoint = target->breakpoints;
540
541 /* set any pending breakpoints */
542 while (breakpoint)
543 {
544 if (breakpoint->set == 0)
545 cortex_m3_set_breakpoint(target, breakpoint);
546 breakpoint = breakpoint->next;
547 }
548 }
549
550 static int cortex_m3_resume(struct target *target, int current,
551 uint32_t address, int handle_breakpoints, int debug_execution)
552 {
553 struct armv7m_common *armv7m = target_to_armv7m(target);
554 struct breakpoint *breakpoint = NULL;
555 uint32_t resume_pc;
556
557 if (target->state != TARGET_HALTED)
558 {
559 LOG_WARNING("target not halted");
560 return ERROR_TARGET_NOT_HALTED;
561 }
562
563 if (!debug_execution)
564 {
565 target_free_all_working_areas(target);
566 cortex_m3_enable_breakpoints(target);
567 cortex_m3_enable_watchpoints(target);
568 }
569
570 if (debug_execution)
571 {
572 /* Disable interrupts */
573 /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
574 * This is probably the same issue as Cortex-M3 Errata 377493:
575 * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
576 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
577 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
578 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
579
580 /* Make sure we are in Thumb mode */
581 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
582 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
583 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
584 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
585 }
586
587 /* current = 1: continue on current pc, otherwise continue at <address> */
588 if (!current)
589 {
590 buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
591 armv7m->core_cache->reg_list[15].dirty = 1;
592 armv7m->core_cache->reg_list[15].valid = 1;
593 }
594
595 resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32);
596
597 armv7m_restore_context(target);
598
599 /* the front-end may request us not to handle breakpoints */
600 if (handle_breakpoints)
601 {
602 /* Single step past breakpoint at current address */
603 if ((breakpoint = breakpoint_find(target, resume_pc)))
604 {
605 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
606 breakpoint->address,
607 breakpoint->unique_id);
608 cortex_m3_unset_breakpoint(target, breakpoint);
609 cortex_m3_single_step_core(target);
610 cortex_m3_set_breakpoint(target, breakpoint);
611 }
612 }
613
614 /* Restart core */
615 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
616
617 target->debug_reason = DBG_REASON_NOTHALTED;
618
619 /* registers are now invalid */
620 register_cache_invalidate(armv7m->core_cache);
621
622 if (!debug_execution)
623 {
624 target->state = TARGET_RUNNING;
625 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
626 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
627 }
628 else
629 {
630 target->state = TARGET_DEBUG_RUNNING;
631 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
632 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
633 }
634
635 return ERROR_OK;
636 }
637
638 /* int irqstepcount = 0; */
639 static int cortex_m3_step(struct target *target, int current,
640 uint32_t address, int handle_breakpoints)
641 {
642 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
643 struct armv7m_common *armv7m = &cortex_m3->armv7m;
644 struct swjdp_common *swjdp = &armv7m->swjdp_info;
645 struct breakpoint *breakpoint = NULL;
646
647 if (target->state != TARGET_HALTED)
648 {
649 LOG_WARNING("target not halted");
650 return ERROR_TARGET_NOT_HALTED;
651 }
652
653 /* current = 1: continue on current pc, otherwise continue at <address> */
654 if (!current)
655 buf_set_u32(cortex_m3->armv7m.core_cache->reg_list[15].value,
656 0, 32, address);
657
658 /* the front-end may request us not to handle breakpoints */
659 if (handle_breakpoints) {
660 breakpoint = breakpoint_find(target, buf_get_u32(armv7m
661 ->core_cache->reg_list[15].value, 0, 32));
662 if (breakpoint)
663 cortex_m3_unset_breakpoint(target, breakpoint);
664 }
665
666 target->debug_reason = DBG_REASON_SINGLESTEP;
667
668 armv7m_restore_context(target);
669
670 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
671
672 /* set step and clear halt */
673 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
674 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
675
676 /* registers are now invalid */
677 register_cache_invalidate(cortex_m3->armv7m.core_cache);
678
679 if (breakpoint)
680 cortex_m3_set_breakpoint(target, breakpoint);
681
682 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
683
684 cortex_m3_debug_entry(target);
685 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
686
687 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
688 return ERROR_OK;
689 }
690
691 static int cortex_m3_assert_reset(struct target *target)
692 {
693 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
694 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
695 int assert_srst = 1;
696
697 LOG_DEBUG("target->state: %s",
698 target_state_name(target));
699
700 enum reset_types jtag_reset_config = jtag_get_reset_config();
701
702 /*
703 * We can reset Cortex-M3 targets using just the NVIC without
704 * requiring SRST, getting a SoC reset (or a core-only reset)
705 * instead of a system reset.
706 */
707 if (!(jtag_reset_config & RESET_HAS_SRST))
708 assert_srst = 0;
709
710 /* Enable debug requests */
711 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
712 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
713 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
714
715 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
716
717 if (!target->reset_halt)
718 {
719 /* Set/Clear C_MASKINTS in a separate operation */
720 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
721 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
722
723 /* clear any debug flags before resuming */
724 cortex_m3_clear_halt(target);
725
726 /* clear C_HALT in dhcsr reg */
727 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
728
729 /* Enter debug state on reset, cf. end_reset_event() */
730 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
731 }
732 else
733 {
734 /* Enter debug state on reset, cf. end_reset_event() */
735 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
736 }
737
738 /*
739 * When nRST is asserted on most Stellaris devices, it clears some of
740 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
741 * and OpenOCD depends on those TRMs. So we won't use SRST on those
742 * chips. (Only power-on reset should affect debug state, beyond a
743 * few specified bits; not the chip's nRST input, wired to SRST.)
744 *
745 * REVISIT current errata specs don't seem to cover this issue.
746 * Do we have more details than this email?
747 * https://lists.berlios.de/pipermail
748 * /openocd-development/2008-August/003065.html
749 */
750 if (strcmp(target->variant, "lm3s") == 0)
751 {
752 /* Check for silicon revisions with the issue. */
753 uint32_t did0;
754
755 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
756 {
757 switch ((did0 >> 16) & 0xff)
758 {
759 case 0:
760 /* all Sandstorm suffer issue */
761 assert_srst = 0;
762 break;
763
764 case 1:
765 case 3:
766 /* Fury and DustDevil rev A have
767 * this nRST problem. It should
768 * be fixed in rev B silicon.
769 */
770 if (((did0 >> 8) & 0xff) == 0)
771 assert_srst = 0;
772 break;
773 case 4:
774 /* Tempest should be fine. */
775 break;
776 }
777 }
778 }
779
780 if (assert_srst)
781 {
782 /* default to asserting srst */
783 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
784 {
785 jtag_add_reset(1, 1);
786 }
787 else
788 {
789 jtag_add_reset(0, 1);
790 }
791 }
792 else
793 {
794 /* Use a standard Cortex-M3 software reset mechanism.
795 * SYSRESETREQ will reset SoC peripherals outside the
796 * core, like watchdog timers, if the SoC wires it up
797 * correctly. Else VECRESET can reset just the core.
798 */
799 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
800 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
801 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
802
803 {
804 /* I do not know why this is necessary, but it
805 * fixes strange effects (step/resume cause NMI
806 * after reset) on LM3S6918 -- Michael Schwingen
807 */
808 uint32_t tmp;
809 mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
810 }
811 }
812
813 target->state = TARGET_RESET;
814 jtag_add_sleep(50000);
815
816 register_cache_invalidate(cortex_m3->armv7m.core_cache);
817
818 if (target->reset_halt)
819 {
820 int retval;
821 if ((retval = target_halt(target)) != ERROR_OK)
822 return retval;
823 }
824
825 return ERROR_OK;
826 }
827
828 static int cortex_m3_deassert_reset(struct target *target)
829 {
830 LOG_DEBUG("target->state: %s",
831 target_state_name(target));
832
833 /* deassert reset lines */
834 jtag_add_reset(0, 0);
835
836 return ERROR_OK;
837 }
838
839 static int
840 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
841 {
842 int retval;
843 int fp_num = 0;
844 uint32_t hilo;
845 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
846 struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
847
848 if (breakpoint->set)
849 {
850 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
851 return ERROR_OK;
852 }
853
854 if (cortex_m3->auto_bp_type)
855 {
856 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
857 }
858
859 if (breakpoint->type == BKPT_HARD)
860 {
861 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
862 fp_num++;
863 if (fp_num >= cortex_m3->fp_num_code)
864 {
865 LOG_ERROR("Can not find free FPB Comparator!");
866 return ERROR_FAIL;
867 }
868 breakpoint->set = fp_num + 1;
869 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
870 comparator_list[fp_num].used = 1;
871 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
872 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
873 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
874 if (!cortex_m3->fpb_enabled)
875 {
876 LOG_DEBUG("FPB wasn't enabled, do it now");
877 target_write_u32(target, FP_CTRL, 3);
878 }
879 }
880 else if (breakpoint->type == BKPT_SOFT)
881 {
882 uint8_t code[4];
883 buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
884 if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
885 {
886 return retval;
887 }
888 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
889 {
890 return retval;
891 }
892 breakpoint->set = 0x11; /* Any nice value but 0 */
893 }
894
895 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
896 breakpoint->unique_id,
897 (int)(breakpoint->type),
898 breakpoint->address,
899 breakpoint->length,
900 breakpoint->set);
901
902 return ERROR_OK;
903 }
904
905 static int
906 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
907 {
908 int retval;
909 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
910 struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
911
912 if (!breakpoint->set)
913 {
914 LOG_WARNING("breakpoint not set");
915 return ERROR_OK;
916 }
917
918 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
919 breakpoint->unique_id,
920 (int)(breakpoint->type),
921 breakpoint->address,
922 breakpoint->length,
923 breakpoint->set);
924
925 if (breakpoint->type == BKPT_HARD)
926 {
927 int fp_num = breakpoint->set - 1;
928 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
929 {
930 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
931 return ERROR_OK;
932 }
933 comparator_list[fp_num].used = 0;
934 comparator_list[fp_num].fpcr_value = 0;
935 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
936 }
937 else
938 {
939 /* restore original instruction (kept in target endianness) */
940 if (breakpoint->length == 4)
941 {
942 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
943 {
944 return retval;
945 }
946 }
947 else
948 {
949 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
950 {
951 return retval;
952 }
953 }
954 }
955 breakpoint->set = 0;
956
957 return ERROR_OK;
958 }
959
960 static int
961 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
962 {
963 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
964
965 if (cortex_m3->auto_bp_type)
966 {
967 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
968 #ifdef ARMV7_GDB_HACKS
969 if (breakpoint->length != 2) {
970 /* XXX Hack: Replace all breakpoints with length != 2 with
971 * a hardware breakpoint. */
972 breakpoint->type = BKPT_HARD;
973 breakpoint->length = 2;
974 }
975 #endif
976 }
977
978 if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
979 {
980 LOG_INFO("flash patch comparator requested outside code memory region");
981 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
982 }
983
984 if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
985 {
986 LOG_INFO("soft breakpoint requested in code (flash) memory region");
987 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
988 }
989
990 if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
991 {
992 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
993 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
994 }
995
996 if ((breakpoint->length != 2))
997 {
998 LOG_INFO("only breakpoints of two bytes length supported");
999 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1000 }
1001
1002 if (breakpoint->type == BKPT_HARD)
1003 cortex_m3->fp_code_available--;
1004 cortex_m3_set_breakpoint(target, breakpoint);
1005
1006 return ERROR_OK;
1007 }
1008
1009 static int
1010 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1011 {
1012 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1013
1014 /* REVISIT why check? FBP can be updated with core running ... */
1015 if (target->state != TARGET_HALTED)
1016 {
1017 LOG_WARNING("target not halted");
1018 return ERROR_TARGET_NOT_HALTED;
1019 }
1020
1021 if (cortex_m3->auto_bp_type)
1022 {
1023 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1024 }
1025
1026 if (breakpoint->set)
1027 {
1028 cortex_m3_unset_breakpoint(target, breakpoint);
1029 }
1030
1031 if (breakpoint->type == BKPT_HARD)
1032 cortex_m3->fp_code_available++;
1033
1034 return ERROR_OK;
1035 }
1036
1037 static int
1038 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1039 {
1040 int dwt_num = 0;
1041 uint32_t mask, temp;
1042 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1043
1044 /* watchpoint params were validated earlier */
1045 mask = 0;
1046 temp = watchpoint->length;
1047 while (temp) {
1048 temp >>= 1;
1049 mask++;
1050 }
1051 mask--;
1052
1053 /* REVISIT Don't fully trust these "not used" records ... users
1054 * may set up breakpoints by hand, e.g. dual-address data value
1055 * watchpoint using comparator #1; comparator #0 matching cycle
1056 * count; send data trace info through ITM and TPIU; etc
1057 */
1058 struct cortex_m3_dwt_comparator *comparator;
1059
1060 for (comparator = cortex_m3->dwt_comparator_list;
1061 comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1062 comparator++, dwt_num++)
1063 continue;
1064 if (dwt_num >= cortex_m3->dwt_num_comp)
1065 {
1066 LOG_ERROR("Can not find free DWT Comparator");
1067 return ERROR_FAIL;
1068 }
1069 comparator->used = 1;
1070 watchpoint->set = dwt_num + 1;
1071
1072 comparator->comp = watchpoint->address;
1073 target_write_u32(target, comparator->dwt_comparator_address + 0,
1074 comparator->comp);
1075
1076 comparator->mask = mask;
1077 target_write_u32(target, comparator->dwt_comparator_address + 4,
1078 comparator->mask);
1079
1080 switch (watchpoint->rw) {
1081 case WPT_READ:
1082 comparator->function = 5;
1083 break;
1084 case WPT_WRITE:
1085 comparator->function = 6;
1086 break;
1087 case WPT_ACCESS:
1088 comparator->function = 7;
1089 break;
1090 }
1091 target_write_u32(target, comparator->dwt_comparator_address + 8,
1092 comparator->function);
1093
1094 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1095 watchpoint->unique_id, dwt_num,
1096 (unsigned) comparator->comp,
1097 (unsigned) comparator->mask,
1098 (unsigned) comparator->function);
1099 return ERROR_OK;
1100 }
1101
1102 static int
1103 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1104 {
1105 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1106 struct cortex_m3_dwt_comparator *comparator;
1107 int dwt_num;
1108
1109 if (!watchpoint->set)
1110 {
1111 LOG_WARNING("watchpoint (wpid: %d) not set",
1112 watchpoint->unique_id);
1113 return ERROR_OK;
1114 }
1115
1116 dwt_num = watchpoint->set - 1;
1117
1118 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1119 watchpoint->unique_id, dwt_num,
1120 (unsigned) watchpoint->address);
1121
1122 if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1123 {
1124 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1125 return ERROR_OK;
1126 }
1127
1128 comparator = cortex_m3->dwt_comparator_list + dwt_num;
1129 comparator->used = 0;
1130 comparator->function = 0;
1131 target_write_u32(target, comparator->dwt_comparator_address + 8,
1132 comparator->function);
1133
1134 watchpoint->set = 0;
1135
1136 return ERROR_OK;
1137 }
1138
1139 static int
1140 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1141 {
1142 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1143
1144 if (cortex_m3->dwt_comp_available < 1)
1145 {
1146 LOG_DEBUG("no comparators?");
1147 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1148 }
1149
1150 /* hardware doesn't support data value masking */
1151 if (watchpoint->mask != ~(uint32_t)0) {
1152 LOG_DEBUG("watchpoint value masks not supported");
1153 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1154 }
1155
1156 /* hardware allows address masks of up to 32K */
1157 unsigned mask;
1158
1159 for (mask = 0; mask < 16; mask++) {
1160 if ((1u << mask) == watchpoint->length)
1161 break;
1162 }
1163 if (mask == 16) {
1164 LOG_DEBUG("unsupported watchpoint length");
1165 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1166 }
1167 if (watchpoint->address & ((1 << mask) - 1)) {
1168 LOG_DEBUG("watchpoint address is unaligned");
1169 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1170 }
1171
1172 /* Caller doesn't seem to be able to describe watching for data
1173 * values of zero; that flags "no value".
1174 *
1175 * REVISIT This DWT may well be able to watch for specific data
1176 * values. Requires comparator #1 to set DATAVMATCH and match
1177 * the data, and another comparator (DATAVADDR0) matching addr.
1178 */
1179 if (watchpoint->value) {
1180 LOG_DEBUG("data value watchpoint not YET supported");
1181 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1182 }
1183
1184 cortex_m3->dwt_comp_available--;
1185 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1186
1187 return ERROR_OK;
1188 }
1189
1190 static int
1191 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1192 {
1193 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1194
1195 /* REVISIT why check? DWT can be updated with core running ... */
1196 if (target->state != TARGET_HALTED)
1197 {
1198 LOG_WARNING("target not halted");
1199 return ERROR_TARGET_NOT_HALTED;
1200 }
1201
1202 if (watchpoint->set)
1203 {
1204 cortex_m3_unset_watchpoint(target, watchpoint);
1205 }
1206
1207 cortex_m3->dwt_comp_available++;
1208 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1209
1210 return ERROR_OK;
1211 }
1212
1213 static void cortex_m3_enable_watchpoints(struct target *target)
1214 {
1215 struct watchpoint *watchpoint = target->watchpoints;
1216
1217 /* set any pending watchpoints */
1218 while (watchpoint)
1219 {
1220 if (watchpoint->set == 0)
1221 cortex_m3_set_watchpoint(target, watchpoint);
1222 watchpoint = watchpoint->next;
1223 }
1224 }
1225
1226 static int cortex_m3_load_core_reg_u32(struct target *target,
1227 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1228 {
1229 int retval;
1230 struct armv7m_common *armv7m = target_to_armv7m(target);
1231 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1232
1233 /* NOTE: we "know" here that the register identifiers used
1234 * in the v7m header match the Cortex-M3 Debug Core Register
1235 * Selector values for R0..R15, xPSR, MSP, and PSP.
1236 */
1237 switch (num) {
1238 case 0 ... 18:
1239 /* read a normal core register */
1240 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1241
1242 if (retval != ERROR_OK)
1243 {
1244 LOG_ERROR("JTAG failure %i",retval);
1245 return ERROR_JTAG_DEVICE_ERROR;
1246 }
1247 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
1248 break;
1249
1250 case ARMV7M_PRIMASK:
1251 case ARMV7M_BASEPRI:
1252 case ARMV7M_FAULTMASK:
1253 case ARMV7M_CONTROL:
1254 /* Cortex-M3 packages these four registers as bitfields
1255 * in one Debug Core register. So say r0 and r2 docs;
1256 * it was removed from r1 docs, but still works.
1257 */
1258 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1259
1260 switch (num)
1261 {
1262 case ARMV7M_PRIMASK:
1263 *value = buf_get_u32((uint8_t*)value, 0, 1);
1264 break;
1265
1266 case ARMV7M_BASEPRI:
1267 *value = buf_get_u32((uint8_t*)value, 8, 8);
1268 break;
1269
1270 case ARMV7M_FAULTMASK:
1271 *value = buf_get_u32((uint8_t*)value, 16, 1);
1272 break;
1273
1274 case ARMV7M_CONTROL:
1275 *value = buf_get_u32((uint8_t*)value, 24, 2);
1276 break;
1277 }
1278
1279 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1280 break;
1281
1282 default:
1283 return ERROR_INVALID_ARGUMENTS;
1284 }
1285
1286 return ERROR_OK;
1287 }
1288
1289 static int cortex_m3_store_core_reg_u32(struct target *target,
1290 enum armv7m_regtype type, uint32_t num, uint32_t value)
1291 {
1292 int retval;
1293 uint32_t reg;
1294 struct armv7m_common *armv7m = target_to_armv7m(target);
1295 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1296
1297 #ifdef ARMV7_GDB_HACKS
1298 /* If the LR register is being modified, make sure it will put us
1299 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1300 * hack to deal with the fact that gdb will sometimes "forge"
1301 * return addresses, and doesn't set the LSB correctly (i.e., when
1302 * printing expressions containing function calls, it sets LR = 0.)
1303 * Valid exception return codes have bit 0 set too.
1304 */
1305 if (num == ARMV7M_R14)
1306 value |= 0x01;
1307 #endif
1308
1309 /* NOTE: we "know" here that the register identifiers used
1310 * in the v7m header match the Cortex-M3 Debug Core Register
1311 * Selector values for R0..R15, xPSR, MSP, and PSP.
1312 */
1313 switch (num) {
1314 case 0 ... 18:
1315 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1316 if (retval != ERROR_OK)
1317 {
1318 LOG_ERROR("JTAG failure %i", retval);
1319 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
1320 return ERROR_JTAG_DEVICE_ERROR;
1321 }
1322 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1323 break;
1324
1325 case ARMV7M_PRIMASK:
1326 case ARMV7M_BASEPRI:
1327 case ARMV7M_FAULTMASK:
1328 case ARMV7M_CONTROL:
1329 /* Cortex-M3 packages these four registers as bitfields
1330 * in one Debug Core register. So say r0 and r2 docs;
1331 * it was removed from r1 docs, but still works.
1332 */
1333 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1334
1335 switch (num)
1336 {
1337 case ARMV7M_PRIMASK:
1338 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1339 break;
1340
1341 case ARMV7M_BASEPRI:
1342 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1343 break;
1344
1345 case ARMV7M_FAULTMASK:
1346 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1347 break;
1348
1349 case ARMV7M_CONTROL:
1350 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1351 break;
1352 }
1353
1354 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1355
1356 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1357 break;
1358
1359 default:
1360 return ERROR_INVALID_ARGUMENTS;
1361 }
1362
1363 return ERROR_OK;
1364 }
1365
1366 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1367 uint32_t size, uint32_t count, uint8_t *buffer)
1368 {
1369 struct armv7m_common *armv7m = target_to_armv7m(target);
1370 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1371 int retval = ERROR_INVALID_ARGUMENTS;
1372
1373 /* cortex_m3 handles unaligned memory access */
1374 if (count && buffer) {
1375 switch (size) {
1376 case 4:
1377 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1378 break;
1379 case 2:
1380 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1381 break;
1382 case 1:
1383 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1384 break;
1385 }
1386 }
1387
1388 return retval;
1389 }
1390
1391 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1392 uint32_t size, uint32_t count, uint8_t *buffer)
1393 {
1394 struct armv7m_common *armv7m = target_to_armv7m(target);
1395 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1396 int retval = ERROR_INVALID_ARGUMENTS;
1397
1398 if (count && buffer) {
1399 switch (size) {
1400 case 4:
1401 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1402 break;
1403 case 2:
1404 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1405 break;
1406 case 1:
1407 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1408 break;
1409 }
1410 }
1411
1412 return retval;
1413 }
1414
1415 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1416 uint32_t count, uint8_t *buffer)
1417 {
1418 return cortex_m3_write_memory(target, address, 4, count, buffer);
1419 }
1420
1421 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1422 struct target *target)
1423 {
1424 armv7m_build_reg_cache(target);
1425 return ERROR_OK;
1426 }
1427
1428 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1429 * on r/w if the core is not running, and clear on resume or reset ... or
1430 * at least, in a post_restore_context() method.
1431 */
1432
1433 struct dwt_reg_state {
1434 struct target *target;
1435 uint32_t addr;
1436 uint32_t value; /* scratch/cache */
1437 };
1438
1439 static int cortex_m3_dwt_get_reg(struct reg *reg)
1440 {
1441 struct dwt_reg_state *state = reg->arch_info;
1442
1443 return target_read_u32(state->target, state->addr, &state->value);
1444 }
1445
1446 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1447 {
1448 struct dwt_reg_state *state = reg->arch_info;
1449
1450 return target_write_u32(state->target, state->addr,
1451 buf_get_u32(buf, 0, reg->size));
1452 }
1453
1454 struct dwt_reg {
1455 uint32_t addr;
1456 char *name;
1457 unsigned size;
1458 };
1459
1460 static struct dwt_reg dwt_base_regs[] = {
1461 { DWT_CTRL, "dwt_ctrl", 32, },
1462 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1463 /* plus some 8 bit counters, useful for profiling with TPIU */
1464 };
1465
1466 static struct dwt_reg dwt_comp[] = {
1467 #define DWT_COMPARATOR(i) \
1468 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1469 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1470 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1471 DWT_COMPARATOR(0),
1472 DWT_COMPARATOR(1),
1473 DWT_COMPARATOR(2),
1474 DWT_COMPARATOR(3),
1475 #undef DWT_COMPARATOR
1476 };
1477
1478 static const struct reg_arch_type dwt_reg_type = {
1479 .get = cortex_m3_dwt_get_reg,
1480 .set = cortex_m3_dwt_set_reg,
1481 };
1482
1483 static void
1484 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1485 {
1486 struct dwt_reg_state *state;
1487
1488 state = calloc(1, sizeof *state);
1489 if (!state)
1490 return;
1491 state->addr = d->addr;
1492 state->target = t;
1493
1494 r->name = d->name;
1495 r->size = d->size;
1496 r->value = &state->value;
1497 r->arch_info = state;
1498 r->type = &dwt_reg_type;
1499 }
1500
1501 static void
1502 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1503 {
1504 uint32_t dwtcr;
1505 struct reg_cache *cache;
1506 struct cortex_m3_dwt_comparator *comparator;
1507 int reg, i;
1508
1509 target_read_u32(target, DWT_CTRL, &dwtcr);
1510 if (!dwtcr) {
1511 LOG_DEBUG("no DWT");
1512 return;
1513 }
1514
1515 cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1516 cm3->dwt_comp_available = cm3->dwt_num_comp;
1517 cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1518 sizeof(struct cortex_m3_dwt_comparator));
1519 if (!cm3->dwt_comparator_list) {
1520 fail0:
1521 cm3->dwt_num_comp = 0;
1522 LOG_ERROR("out of mem");
1523 return;
1524 }
1525
1526 cache = calloc(1, sizeof *cache);
1527 if (!cache) {
1528 fail1:
1529 free(cm3->dwt_comparator_list);
1530 goto fail0;
1531 }
1532 cache->name = "cortex-m3 dwt registers";
1533 cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1534 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1535 if (!cache->reg_list) {
1536 free(cache);
1537 goto fail1;
1538 }
1539
1540 for (reg = 0; reg < 2; reg++)
1541 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1542 dwt_base_regs + reg);
1543
1544 comparator = cm3->dwt_comparator_list;
1545 for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1546 int j;
1547
1548 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1549 for (j = 0; j < 3; j++, reg++)
1550 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1551 dwt_comp + 3 * i + j);
1552 }
1553
1554 *register_get_last_cache_p(&target->reg_cache) = cache;
1555 cm3->dwt_cache = cache;
1556
1557 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1558 dwtcr, cm3->dwt_num_comp,
1559 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1560
1561 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1562 * implement single-address data value watchpoints ... so we
1563 * won't need to check it later, when asked to set one up.
1564 */
1565 }
1566
1567 static int cortex_m3_examine(struct target *target)
1568 {
1569 int retval;
1570 uint32_t cpuid, fpcr;
1571 int i;
1572 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1573 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
1574
1575 if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1576 return retval;
1577
1578 if (!target_was_examined(target))
1579 {
1580 target_set_examined(target);
1581
1582 /* Read from Device Identification Registers */
1583 retval = target_read_u32(target, CPUID, &cpuid);
1584 if (retval != ERROR_OK)
1585 return retval;
1586
1587 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1588 LOG_DEBUG("CORTEX-M3 processor detected");
1589 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1590
1591 /* NOTE: FPB and DWT are both optional. */
1592
1593 /* Setup FPB */
1594 target_read_u32(target, FP_CTRL, &fpcr);
1595 cortex_m3->auto_bp_type = 1;
1596 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1597 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1598 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1599 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1600 cortex_m3->fpb_enabled = fpcr & 1;
1601 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1602 {
1603 cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1604 cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1605 }
1606 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1607
1608 /* Setup DWT */
1609 cortex_m3_dwt_setup(cortex_m3, target);
1610 }
1611
1612 return ERROR_OK;
1613 }
1614
1615 static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1616 {
1617 uint16_t dcrdr;
1618
1619 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1620 *ctrl = (uint8_t)dcrdr;
1621 *value = (uint8_t)(dcrdr >> 8);
1622
1623 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1624
1625 /* write ack back to software dcc register
1626 * signify we have read data */
1627 if (dcrdr & (1 << 0))
1628 {
1629 dcrdr = 0;
1630 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1631 }
1632
1633 return ERROR_OK;
1634 }
1635
1636 static int cortex_m3_target_request_data(struct target *target,
1637 uint32_t size, uint8_t *buffer)
1638 {
1639 struct armv7m_common *armv7m = target_to_armv7m(target);
1640 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1641 uint8_t data;
1642 uint8_t ctrl;
1643 uint32_t i;
1644
1645 for (i = 0; i < (size * 4); i++)
1646 {
1647 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1648 buffer[i] = data;
1649 }
1650
1651 return ERROR_OK;
1652 }
1653
1654 static int cortex_m3_handle_target_request(void *priv)
1655 {
1656 struct target *target = priv;
1657 if (!target_was_examined(target))
1658 return ERROR_OK;
1659 struct armv7m_common *armv7m = target_to_armv7m(target);
1660 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1661
1662 if (!target->dbg_msg_enabled)
1663 return ERROR_OK;
1664
1665 if (target->state == TARGET_RUNNING)
1666 {
1667 uint8_t data;
1668 uint8_t ctrl;
1669
1670 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1671
1672 /* check if we have data */
1673 if (ctrl & (1 << 0))
1674 {
1675 uint32_t request;
1676
1677 /* we assume target is quick enough */
1678 request = data;
1679 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1680 request |= (data << 8);
1681 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1682 request |= (data << 16);
1683 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1684 request |= (data << 24);
1685 target_request(target, request);
1686 }
1687 }
1688
1689 return ERROR_OK;
1690 }
1691
1692 static int cortex_m3_init_arch_info(struct target *target,
1693 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1694 {
1695 int retval;
1696 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1697
1698 armv7m_init_arch_info(target, armv7m);
1699
1700 /* prepare JTAG information for the new target */
1701 cortex_m3->jtag_info.tap = tap;
1702 cortex_m3->jtag_info.scann_size = 4;
1703
1704 armv7m->swjdp_info.dp_select_value = -1;
1705 armv7m->swjdp_info.ap_csw_value = -1;
1706 armv7m->swjdp_info.ap_tar_value = -1;
1707 armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1708 armv7m->swjdp_info.memaccess_tck = 8;
1709 armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
1710
1711 /* register arch-specific functions */
1712 armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1713
1714 armv7m->post_debug_entry = NULL;
1715
1716 armv7m->pre_restore_context = NULL;
1717 armv7m->post_restore_context = NULL;
1718
1719 armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1720 armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1721
1722 target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1723
1724 if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1725 {
1726 return retval;
1727 }
1728
1729 return ERROR_OK;
1730 }
1731
1732 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1733 {
1734 struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1735
1736 cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1737 cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1738
1739 return ERROR_OK;
1740 }
1741
1742 /*--------------------------------------------------------------------------*/
1743
1744 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1745 struct cortex_m3_common *cm3)
1746 {
1747 if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1748 command_print(cmd_ctx, "target is not a Cortex-M3");
1749 return ERROR_TARGET_INVALID;
1750 }
1751 return ERROR_OK;
1752 }
1753
1754 /*
1755 * Only stuff below this line should need to verify that its target
1756 * is a Cortex-M3. Everything else should have indirected through the
1757 * cortexm3_target structure, which is only used with CM3 targets.
1758 */
1759
1760 /*
1761 * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1762 * as at least ARM-1156T2. The interesting thing about Cortex-M is
1763 * that *only* Thumb2 disassembly matters. There are also some small
1764 * additions to Thumb2 that are specific to ARMv7-M.
1765 */
1766 COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
1767 {
1768 int retval;
1769 struct target *target = get_current_target(CMD_CTX);
1770 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1771 uint32_t address;
1772 unsigned long count = 1;
1773 struct arm_instruction cur_instruction;
1774
1775 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1776 if (retval != ERROR_OK)
1777 return retval;
1778
1779 errno = 0;
1780 switch (CMD_ARGC) {
1781 case 2:
1782 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count);
1783 /* FALL THROUGH */
1784 case 1:
1785 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1786 break;
1787 default:
1788 command_print(CMD_CTX,
1789 "usage: cortex_m3 disassemble <address> [<count>]");
1790 return ERROR_OK;
1791 }
1792
1793 while (count--) {
1794 retval = thumb2_opcode(target, address, &cur_instruction);
1795 if (retval != ERROR_OK)
1796 return retval;
1797 command_print(CMD_CTX, "%s", cur_instruction.text);
1798 address += cur_instruction.instruction_size;
1799 }
1800
1801 return ERROR_OK;
1802 }
1803
1804 static const struct {
1805 char name[10];
1806 unsigned mask;
1807 } vec_ids[] = {
1808 { "hard_err", VC_HARDERR, },
1809 { "int_err", VC_INTERR, },
1810 { "bus_err", VC_BUSERR, },
1811 { "state_err", VC_STATERR, },
1812 { "chk_err", VC_CHKERR, },
1813 { "nocp_err", VC_NOCPERR, },
1814 { "mm_err", VC_MMERR, },
1815 { "reset", VC_CORERESET, },
1816 };
1817
1818 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1819 {
1820 struct target *target = get_current_target(CMD_CTX);
1821 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1822 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1823 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1824 uint32_t demcr = 0;
1825 int retval;
1826
1827 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1828 if (retval != ERROR_OK)
1829 return retval;
1830
1831 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1832
1833 if (CMD_ARGC > 0) {
1834 unsigned catch = 0;
1835
1836 if (CMD_ARGC == 1) {
1837 if (strcmp(CMD_ARGV[0], "all") == 0) {
1838 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1839 | VC_STATERR | VC_CHKERR | VC_NOCPERR
1840 | VC_MMERR | VC_CORERESET;
1841 goto write;
1842 } else if (strcmp(CMD_ARGV[0], "none") == 0) {
1843 goto write;
1844 }
1845 }
1846 while (CMD_ARGC-- > 0) {
1847 unsigned i;
1848 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1849 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
1850 continue;
1851 catch |= vec_ids[i].mask;
1852 break;
1853 }
1854 if (i == ARRAY_SIZE(vec_ids)) {
1855 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
1856 return ERROR_INVALID_ARGUMENTS;
1857 }
1858 }
1859 write:
1860 demcr &= ~0xffff;
1861 demcr |= catch;
1862
1863 /* write, but don't assume it stuck */
1864 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
1865 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1866 }
1867
1868 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
1869 {
1870 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
1871 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
1872 }
1873
1874 return ERROR_OK;
1875 }
1876
1877 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
1878 {
1879 struct target *target = get_current_target(CMD_CTX);
1880 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1881 int retval;
1882
1883 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1884 if (retval != ERROR_OK)
1885 return retval;
1886
1887 if (target->state != TARGET_HALTED)
1888 {
1889 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1890 return ERROR_OK;
1891 }
1892
1893 if (CMD_ARGC > 0)
1894 {
1895 bool enable;
1896 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
1897 uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
1898 uint32_t mask_off = enable ? 0 : C_MASKINTS;
1899 cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
1900 }
1901
1902 command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
1903 (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
1904
1905 return ERROR_OK;
1906 }
1907
1908 static const struct command_registration cortex_m3_exec_command_handlers[] = {
1909 {
1910 .name = "disassemble",
1911 .handler = &handle_cortex_m3_disassemble_command,
1912 .mode = COMMAND_EXEC,
1913 .help = "disassemble Thumb2 instructions",
1914 .usage = "<address> [<count>]",
1915 },
1916 {
1917 .name = "maskisr",
1918 .handler = &handle_cortex_m3_mask_interrupts_command,
1919 .mode = COMMAND_EXEC,
1920 .help = "mask cortex_m3 interrupts",
1921 .usage = "['on'|'off']",
1922 },
1923 {
1924 .name = "vector_catch",
1925 .handler = &handle_cortex_m3_vector_catch_command,
1926 .mode = COMMAND_EXEC,
1927 .help = "catch hardware vectors",
1928 .usage = "['all'|'none'|<list>]",
1929 },
1930 COMMAND_REGISTRATION_DONE
1931 };
1932 static const struct command_registration cortex_m3_command_handlers[] = {
1933 {
1934 .chain = armv7m_command_handlers,
1935 },
1936 {
1937 .name = "cortex_m3",
1938 .mode = COMMAND_ANY,
1939 .help = "Cortex-M3 command group",
1940 .chain = cortex_m3_exec_command_handlers,
1941 },
1942 COMMAND_REGISTRATION_DONE
1943 };
1944
1945 struct target_type cortexm3_target =
1946 {
1947 .name = "cortex_m3",
1948
1949 .poll = cortex_m3_poll,
1950 .arch_state = armv7m_arch_state,
1951
1952 .target_request_data = cortex_m3_target_request_data,
1953
1954 .halt = cortex_m3_halt,
1955 .resume = cortex_m3_resume,
1956 .step = cortex_m3_step,
1957
1958 .assert_reset = cortex_m3_assert_reset,
1959 .deassert_reset = cortex_m3_deassert_reset,
1960 .soft_reset_halt = cortex_m3_soft_reset_halt,
1961
1962 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
1963
1964 .read_memory = cortex_m3_read_memory,
1965 .write_memory = cortex_m3_write_memory,
1966 .bulk_write_memory = cortex_m3_bulk_write_memory,
1967 .checksum_memory = armv7m_checksum_memory,
1968 .blank_check_memory = armv7m_blank_check_memory,
1969
1970 .run_algorithm = armv7m_run_algorithm,
1971
1972 .add_breakpoint = cortex_m3_add_breakpoint,
1973 .remove_breakpoint = cortex_m3_remove_breakpoint,
1974 .add_watchpoint = cortex_m3_add_watchpoint,
1975 .remove_watchpoint = cortex_m3_remove_watchpoint,
1976
1977 .commands = cortex_m3_command_handlers,
1978 .target_create = cortex_m3_target_create,
1979 .init_target = cortex_m3_init_target,
1980 .examine = cortex_m3_examine,
1981 };
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