1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
42 /* NOTE: most of this should work fine for the Cortex-M1 and
43 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
46 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
49 /* forward declarations */
50 static int cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
51 static int cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
52 static void cortex_m3_enable_watchpoints(struct target
*target
);
53 static int cortex_m3_store_core_reg_u32(struct target
*target
,
54 enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
56 #ifdef ARMV7_GDB_HACKS
57 extern uint8_t armv7m_gdb_dummy_cpsr_value
[];
58 extern struct reg armv7m_gdb_dummy_cpsr_reg
;
61 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common
*swjdp
,
62 uint32_t *value
, int regnum
)
67 /* because the DCB_DCRDR is used for the emulated dcc channel
68 * we have to save/restore the DCB_DCRDR when used */
70 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
72 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
74 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
75 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
76 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
78 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
79 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
80 dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
82 retval
= swjdp_transaction_endcheck(swjdp
);
84 /* restore DCB_DCRDR - this needs to be in a seperate
85 * transaction otherwise the emulated DCC channel breaks */
86 if (retval
== ERROR_OK
)
87 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
92 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common
*swjdp
,
93 uint32_t value
, int regnum
)
98 /* because the DCB_DCRDR is used for the emulated dcc channel
99 * we have to save/restore the DCB_DCRDR when used */
101 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
103 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
105 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
106 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
107 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
109 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
110 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
111 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
113 retval
= swjdp_transaction_endcheck(swjdp
);
115 /* restore DCB_DCRDR - this needs to be in a seperate
116 * transaction otherwise the emulated DCC channel breaks */
117 if (retval
== ERROR_OK
)
118 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
123 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
124 uint32_t mask_on
, uint32_t mask_off
)
126 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
127 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
129 /* mask off status bits */
130 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
131 /* create new register mask */
132 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
134 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
137 static int cortex_m3_clear_halt(struct target
*target
)
139 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
140 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
142 /* clear step if any */
143 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
145 /* Read Debug Fault Status Register */
146 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
147 /* Clear Debug Fault Status */
148 mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
149 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
154 static int cortex_m3_single_step_core(struct target
*target
)
156 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
157 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
160 /* backup dhcsr reg */
161 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
163 /* mask interrupts if not done already */
164 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
))
165 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
166 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
169 /* restore dhcsr reg */
170 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
171 cortex_m3_clear_halt(target
);
176 static int cortex_m3_endreset_event(struct target
*target
)
180 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
181 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
182 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
183 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
185 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
186 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"",dcb_demcr
);
188 /* this regsiter is used for emulated dcc channel */
189 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
191 /* Enable debug requests */
192 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
193 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
194 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
196 /* clear any interrupt masking */
197 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
199 /* Enable trace and dwt */
200 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
);
201 /* Monitor bus faults */
202 mem_ap_write_u32(swjdp
, NVIC_SHCSR
, SHCSR_BUSFAULTENA
);
205 target_write_u32(target
, FP_CTRL
, 3);
206 cortex_m3
->fpb_enabled
= 1;
208 /* Restore FPB registers */
209 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
211 target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
214 /* Restore DWT registers */
215 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++)
217 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
219 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
221 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
222 dwt_list
[i
].function
);
224 swjdp_transaction_endcheck(swjdp
);
226 armv7m_invalidate_core_regs(target
);
228 /* make sure we have latest dhcsr flags */
229 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
234 static int cortex_m3_examine_debug_reason(struct target
*target
)
236 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
238 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
239 /* only check the debug reason if we don't know it already */
241 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
242 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
244 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
)
246 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
247 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
248 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
250 else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
251 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
252 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
253 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
254 else /* EXTERNAL, HALTED */
255 target
->debug_reason
= DBG_REASON_UNDEFINED
;
261 static int cortex_m3_examine_exception_reason(struct target
*target
)
263 uint32_t shcsr
, except_sr
, cfsr
= -1, except_ar
= -1;
264 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
265 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
267 mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
268 switch (armv7m
->exception_number
)
272 case 3: /* Hard Fault */
273 mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
274 if (except_sr
& 0x40000000)
276 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
279 case 4: /* Memory Management */
280 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
281 mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
283 case 5: /* Bus Fault */
284 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
285 mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
287 case 6: /* Usage Fault */
288 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
290 case 11: /* SVCall */
292 case 12: /* Debug Monitor */
293 mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
295 case 14: /* PendSV */
297 case 15: /* SysTick */
303 swjdp_transaction_endcheck(swjdp
);
304 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
"", armv7m_exception_string(armv7m
->exception_number
), \
305 shcsr
, except_sr
, cfsr
, except_ar
);
309 static int cortex_m3_debug_entry(struct target
*target
)
314 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
315 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
316 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
320 cortex_m3_clear_halt(target
);
321 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
323 if ((retval
= armv7m
->examine_debug_reason(target
)) != ERROR_OK
)
326 /* Examine target state and mode */
327 /* First load register acessible through core debug port*/
328 int num_regs
= armv7m
->core_cache
->num_regs
;
330 for (i
= 0; i
< num_regs
; i
++)
332 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
333 armv7m
->read_core_reg(target
, i
);
336 xPSR
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32);
338 #ifdef ARMV7_GDB_HACKS
339 /* copy real xpsr reg for gdb, setting thumb bit */
340 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
341 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
342 armv7m_gdb_dummy_cpsr_reg
.valid
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
;
343 armv7m_gdb_dummy_cpsr_reg
.dirty
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
;
346 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
349 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
;
350 cortex_m3_store_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 16, xPSR
&~ 0xff);
353 /* Are we in an exception handler */
356 armv7m
->core_mode
= ARMV7M_MODE_HANDLER
;
357 armv7m
->exception_number
= (xPSR
& 0x1FF);
361 armv7m
->core_mode
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
, 0, 1);
362 armv7m
->exception_number
= 0;
365 if (armv7m
->exception_number
)
367 cortex_m3_examine_exception_reason(target
);
370 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
371 armv7m_mode_strings
[armv7m
->core_mode
],
372 *(uint32_t*)(armv7m
->core_cache
->reg_list
[15].value
),
373 target_state_name(target
));
375 if (armv7m
->post_debug_entry
)
376 armv7m
->post_debug_entry(target
);
381 static int cortex_m3_poll(struct target
*target
)
384 enum target_state prev_target_state
= target
->state
;
385 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
386 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
388 /* Read from Debug Halting Control and Status Register */
389 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
390 if (retval
!= ERROR_OK
)
392 target
->state
= TARGET_UNKNOWN
;
396 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
398 /* check if still in reset */
399 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
401 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
403 target
->state
= TARGET_RESET
;
408 if (target
->state
== TARGET_RESET
)
410 /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
411 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
);
412 cortex_m3_endreset_event(target
);
413 target
->state
= TARGET_RUNNING
;
414 prev_target_state
= TARGET_RUNNING
;
417 if (cortex_m3
->dcb_dhcsr
& S_HALT
)
419 target
->state
= TARGET_HALTED
;
421 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
))
423 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
426 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
428 if (prev_target_state
== TARGET_DEBUG_RUNNING
)
431 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
434 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
438 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
439 * How best to model low power modes?
442 if (target
->state
== TARGET_UNKNOWN
)
444 /* check if processor is retiring instructions */
445 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
)
447 target
->state
= TARGET_RUNNING
;
455 static int cortex_m3_halt(struct target
*target
)
457 LOG_DEBUG("target->state: %s",
458 target_state_name(target
));
460 if (target
->state
== TARGET_HALTED
)
462 LOG_DEBUG("target was already halted");
466 if (target
->state
== TARGET_UNKNOWN
)
468 LOG_WARNING("target was in unknown state when halt was requested");
471 if (target
->state
== TARGET_RESET
)
473 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
475 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
476 return ERROR_TARGET_FAILURE
;
480 /* we came here in a reset_halt or reset_init sequence
481 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
483 target
->debug_reason
= DBG_REASON_DBGRQ
;
489 /* Write to Debug Halting Control and Status Register */
490 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
492 target
->debug_reason
= DBG_REASON_DBGRQ
;
497 static int cortex_m3_soft_reset_halt(struct target
*target
)
499 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
500 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
501 uint32_t dcb_dhcsr
= 0;
502 int retval
, timeout
= 0;
504 /* Enter debug state on reset, cf. end_reset_event() */
505 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
507 /* Request a reset */
508 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
, AIRCR_VECTKEY
| AIRCR_VECTRESET
);
509 target
->state
= TARGET_RESET
;
511 /* registers are now invalid */
512 armv7m_invalidate_core_regs(target
);
514 while (timeout
< 100)
516 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
517 if (retval
== ERROR_OK
)
519 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
520 if ((dcb_dhcsr
& S_HALT
) && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
))
522 LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32
", nvic_dfsr 0x%" PRIx32
"", dcb_dhcsr
, cortex_m3
->nvic_dfsr
);
523 cortex_m3_poll(target
);
527 LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32
", %i ms", dcb_dhcsr
, timeout
);
536 static void cortex_m3_enable_breakpoints(struct target
*target
)
538 struct breakpoint
*breakpoint
= target
->breakpoints
;
540 /* set any pending breakpoints */
543 if (breakpoint
->set
== 0)
544 cortex_m3_set_breakpoint(target
, breakpoint
);
545 breakpoint
= breakpoint
->next
;
549 static int cortex_m3_resume(struct target
*target
, int current
,
550 uint32_t address
, int handle_breakpoints
, int debug_execution
)
552 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
553 struct breakpoint
*breakpoint
= NULL
;
556 if (target
->state
!= TARGET_HALTED
)
558 LOG_WARNING("target not halted");
559 return ERROR_TARGET_NOT_HALTED
;
562 if (!debug_execution
)
564 target_free_all_working_areas(target
);
565 cortex_m3_enable_breakpoints(target
);
566 cortex_m3_enable_watchpoints(target
);
571 /* Disable interrupts */
572 /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
573 * This is probably the same issue as Cortex-M3 Errata 377493:
574 * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
575 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
576 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
577 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
579 /* Make sure we are in Thumb mode */
580 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
581 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32) | (1 << 24));
582 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
583 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
586 /* current = 1: continue on current pc, otherwise continue at <address> */
589 buf_set_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32, address
);
590 armv7m
->core_cache
->reg_list
[15].dirty
= 1;
591 armv7m
->core_cache
->reg_list
[15].valid
= 1;
594 resume_pc
= buf_get_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32);
596 armv7m_restore_context(target
);
598 /* the front-end may request us not to handle breakpoints */
599 if (handle_breakpoints
)
601 /* Single step past breakpoint at current address */
602 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
604 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
606 breakpoint
->unique_id
);
607 cortex_m3_unset_breakpoint(target
, breakpoint
);
608 cortex_m3_single_step_core(target
);
609 cortex_m3_set_breakpoint(target
, breakpoint
);
614 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
616 target
->debug_reason
= DBG_REASON_NOTHALTED
;
618 /* registers are now invalid */
619 armv7m_invalidate_core_regs(target
);
620 if (!debug_execution
)
622 target
->state
= TARGET_RUNNING
;
623 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
624 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
628 target
->state
= TARGET_DEBUG_RUNNING
;
629 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
630 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
636 /* int irqstepcount = 0; */
637 static int cortex_m3_step(struct target
*target
, int current
,
638 uint32_t address
, int handle_breakpoints
)
640 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
641 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
642 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
643 struct breakpoint
*breakpoint
= NULL
;
645 if (target
->state
!= TARGET_HALTED
)
647 LOG_WARNING("target not halted");
648 return ERROR_TARGET_NOT_HALTED
;
651 /* current = 1: continue on current pc, otherwise continue at <address> */
653 buf_set_u32(cortex_m3
->armv7m
.core_cache
->reg_list
[15].value
,
656 /* the front-end may request us not to handle breakpoints */
657 if (handle_breakpoints
) {
658 breakpoint
= breakpoint_find(target
, buf_get_u32(armv7m
659 ->core_cache
->reg_list
[15].value
, 0, 32));
661 cortex_m3_unset_breakpoint(target
, breakpoint
);
664 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
666 armv7m_restore_context(target
);
668 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
670 /* set step and clear halt */
671 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
672 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
674 /* registers are now invalid */
675 armv7m_invalidate_core_regs(target
);
678 cortex_m3_set_breakpoint(target
, breakpoint
);
680 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
" nvic_icsr = 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
682 cortex_m3_debug_entry(target
);
683 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
685 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
" nvic_icsr = 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
689 static int cortex_m3_assert_reset(struct target
*target
)
691 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
692 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
695 LOG_DEBUG("target->state: %s",
696 target_state_name(target
));
698 enum reset_types jtag_reset_config
= jtag_get_reset_config();
701 * We can reset Cortex-M3 targets using just the NVIC without
702 * requiring SRST, getting a SoC reset (or a core-only reset)
703 * instead of a system reset.
705 if (!(jtag_reset_config
& RESET_HAS_SRST
))
708 /* Enable debug requests */
709 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
710 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
711 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
713 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
715 if (!target
->reset_halt
)
717 /* Set/Clear C_MASKINTS in a separate operation */
718 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
)
719 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
| C_HALT
);
721 /* clear any debug flags before resuming */
722 cortex_m3_clear_halt(target
);
724 /* clear C_HALT in dhcsr reg */
725 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
727 /* Enter debug state on reset, cf. end_reset_event() */
728 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
);
732 /* Enter debug state on reset, cf. end_reset_event() */
733 mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
737 * When nRST is asserted on most Stellaris devices, it clears some of
738 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
739 * and OpenOCD depends on those TRMs. So we won't use SRST on those
740 * chips. (Only power-on reset should affect debug state, beyond a
741 * few specified bits; not the chip's nRST input, wired to SRST.)
743 * REVISIT current errata specs don't seem to cover this issue.
744 * Do we have more details than this email?
745 * https://lists.berlios.de/pipermail
746 * /openocd-development/2008-August/003065.html
748 if (strcmp(target
->variant
, "lm3s") == 0)
750 /* Check for silicon revisions with the issue. */
753 if (target_read_u32(target
, 0x400fe000, &did0
) == ERROR_OK
)
755 switch ((did0
>> 16) & 0xff)
758 /* all Sandstorm suffer issue */
764 /* Fury and DustDevil rev A have
765 * this nRST problem. It should
766 * be fixed in rev B silicon.
768 if (((did0
>> 8) & 0xff) == 0)
772 /* Tempest should be fine. */
780 /* default to asserting srst */
781 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
783 jtag_add_reset(1, 1);
787 jtag_add_reset(0, 1);
792 /* Use a standard Cortex-M3 software reset mechanism.
793 * SYSRESETREQ will reset SoC peripherals outside the
794 * core, like watchdog timers, if the SoC wires it up
795 * correctly. Else VECRESET can reset just the core.
797 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
798 AIRCR_VECTKEY
| AIRCR_SYSRESETREQ
);
799 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
802 /* I do not know why this is necessary, but it
803 * fixes strange effects (step/resume cause NMI
804 * after reset) on LM3S6918 -- Michael Schwingen
807 mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
811 target
->state
= TARGET_RESET
;
812 jtag_add_sleep(50000);
814 armv7m_invalidate_core_regs(target
);
816 if (target
->reset_halt
)
819 if ((retval
= target_halt(target
)) != ERROR_OK
)
826 static int cortex_m3_deassert_reset(struct target
*target
)
828 LOG_DEBUG("target->state: %s",
829 target_state_name(target
));
831 /* deassert reset lines */
832 jtag_add_reset(0, 0);
838 cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
843 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
844 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
848 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
852 if (cortex_m3
->auto_bp_type
)
854 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
857 if (breakpoint
->type
== BKPT_HARD
)
859 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
861 if (fp_num
>= cortex_m3
->fp_num_code
)
863 LOG_DEBUG("ERROR Can not find free FP Comparator");
864 LOG_WARNING("ERROR Can not find free FP Comparator");
867 breakpoint
->set
= fp_num
+ 1;
868 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
869 comparator_list
[fp_num
].used
= 1;
870 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
871 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
872 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"", fp_num
, comparator_list
[fp_num
].fpcr_value
);
873 if (!cortex_m3
->fpb_enabled
)
875 LOG_DEBUG("FPB wasn't enabled, do it now");
876 target_write_u32(target
, FP_CTRL
, 3);
879 else if (breakpoint
->type
== BKPT_SOFT
)
882 buf_set_u32(code
, 0, 32, ARMV7M_T_BKPT(0x11));
883 if ((retval
= target_read_memory(target
, breakpoint
->address
& 0xFFFFFFFE, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
887 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, breakpoint
->length
, 1, code
)) != ERROR_OK
)
891 breakpoint
->set
= 0x11; /* Any nice value but 0 */
894 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
895 breakpoint
->unique_id
,
896 (int)(breakpoint
->type
),
905 cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
908 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
909 struct cortex_m3_fp_comparator
* comparator_list
= cortex_m3
->fp_comparator_list
;
911 if (!breakpoint
->set
)
913 LOG_WARNING("breakpoint not set");
917 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
918 breakpoint
->unique_id
,
919 (int)(breakpoint
->type
),
924 if (breakpoint
->type
== BKPT_HARD
)
926 int fp_num
= breakpoint
->set
- 1;
927 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
))
929 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
932 comparator_list
[fp_num
].used
= 0;
933 comparator_list
[fp_num
].fpcr_value
= 0;
934 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
938 /* restore original instruction (kept in target endianness) */
939 if (breakpoint
->length
== 4)
941 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
948 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
960 cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
962 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
964 if (cortex_m3
->auto_bp_type
)
966 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
967 #ifdef ARMV7_GDB_HACKS
968 if (breakpoint
->length
!= 2) {
969 /* XXX Hack: Replace all breakpoints with length != 2 with
970 * a hardware breakpoint. */
971 breakpoint
->type
= BKPT_HARD
;
972 breakpoint
->length
= 2;
977 if ((breakpoint
->type
== BKPT_HARD
) && (breakpoint
->address
>= 0x20000000))
979 LOG_INFO("flash patch comparator requested outside code memory region");
980 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
983 if ((breakpoint
->type
== BKPT_SOFT
) && (breakpoint
->address
< 0x20000000))
985 LOG_INFO("soft breakpoint requested in code (flash) memory region");
986 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
989 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1))
991 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
992 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
995 if ((breakpoint
->length
!= 2))
997 LOG_INFO("only breakpoints of two bytes length supported");
998 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1001 if (breakpoint
->type
== BKPT_HARD
)
1002 cortex_m3
->fp_code_available
--;
1003 cortex_m3_set_breakpoint(target
, breakpoint
);
1009 cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1011 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1013 /* REVISIT why check? FBP can be updated with core running ... */
1014 if (target
->state
!= TARGET_HALTED
)
1016 LOG_WARNING("target not halted");
1017 return ERROR_TARGET_NOT_HALTED
;
1020 if (cortex_m3
->auto_bp_type
)
1022 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
1025 if (breakpoint
->set
)
1027 cortex_m3_unset_breakpoint(target
, breakpoint
);
1030 if (breakpoint
->type
== BKPT_HARD
)
1031 cortex_m3
->fp_code_available
++;
1037 cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1040 uint32_t mask
, temp
;
1041 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1043 /* watchpoint params were validated earlier */
1045 temp
= watchpoint
->length
;
1052 /* REVISIT Don't fully trust these "not used" records ... users
1053 * may set up breakpoints by hand, e.g. dual-address data value
1054 * watchpoint using comparator #1; comparator #0 matching cycle
1055 * count; send data trace info through ITM and TPIU; etc
1057 struct cortex_m3_dwt_comparator
*comparator
;
1059 for (comparator
= cortex_m3
->dwt_comparator_list
;
1060 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1061 comparator
++, dwt_num
++)
1063 if (dwt_num
>= cortex_m3
->dwt_num_comp
)
1065 LOG_ERROR("Can not find free DWT Comparator");
1068 comparator
->used
= 1;
1069 watchpoint
->set
= dwt_num
+ 1;
1071 comparator
->comp
= watchpoint
->address
;
1072 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1075 comparator
->mask
= mask
;
1076 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1079 switch (watchpoint
->rw
) {
1081 comparator
->function
= 5;
1084 comparator
->function
= 6;
1087 comparator
->function
= 7;
1090 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1091 comparator
->function
);
1093 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1094 watchpoint
->unique_id
, dwt_num
,
1095 (unsigned) comparator
->comp
,
1096 (unsigned) comparator
->mask
,
1097 (unsigned) comparator
->function
);
1102 cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1104 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1105 struct cortex_m3_dwt_comparator
*comparator
;
1108 if (!watchpoint
->set
)
1110 LOG_WARNING("watchpoint (wpid: %d) not set",
1111 watchpoint
->unique_id
);
1115 dwt_num
= watchpoint
->set
- 1;
1117 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1118 watchpoint
->unique_id
, dwt_num
,
1119 (unsigned) watchpoint
->address
);
1121 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
))
1123 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1127 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1128 comparator
->used
= 0;
1129 comparator
->function
= 0;
1130 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1131 comparator
->function
);
1133 watchpoint
->set
= 0;
1139 cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1141 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1143 /* REVISIT why check? DWT can be updated with core running ... */
1144 if (target
->state
!= TARGET_HALTED
)
1146 LOG_WARNING("target not halted");
1147 return ERROR_TARGET_NOT_HALTED
;
1150 if (cortex_m3
->dwt_comp_available
< 1)
1152 LOG_DEBUG("no comparators?");
1153 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1156 /* hardware doesn't support data value masking */
1157 if (watchpoint
->mask
!= ~(uint32_t)0) {
1158 LOG_DEBUG("watchpoint value masks not supported");
1159 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1162 /* hardware allows address masks of up to 32K */
1165 for (mask
= 0; mask
< 16; mask
++) {
1166 if ((1u << mask
) == watchpoint
->length
)
1170 LOG_DEBUG("unsupported watchpoint length");
1171 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1173 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1174 LOG_DEBUG("watchpoint address is unaligned");
1175 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1178 /* Caller doesn't seem to be able to describe watching for data
1179 * values of zero; that flags "no value".
1181 * REVISIT This DWT may well be able to watch for specific data
1182 * values. Requires comparator #1 to set DATAVMATCH and match
1183 * the data, and another comparator (DATAVADDR0) matching addr.
1185 if (watchpoint
->value
) {
1186 LOG_DEBUG("data value watchpoint not YET supported");
1187 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1190 cortex_m3
->dwt_comp_available
--;
1191 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1197 cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1199 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1201 /* REVISIT why check? DWT can be updated with core running ... */
1202 if (target
->state
!= TARGET_HALTED
)
1204 LOG_WARNING("target not halted");
1205 return ERROR_TARGET_NOT_HALTED
;
1208 if (watchpoint
->set
)
1210 cortex_m3_unset_watchpoint(target
, watchpoint
);
1213 cortex_m3
->dwt_comp_available
++;
1214 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1219 static void cortex_m3_enable_watchpoints(struct target
*target
)
1221 struct watchpoint
*watchpoint
= target
->watchpoints
;
1223 /* set any pending watchpoints */
1226 if (watchpoint
->set
== 0)
1227 cortex_m3_set_watchpoint(target
, watchpoint
);
1228 watchpoint
= watchpoint
->next
;
1232 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1233 enum armv7m_regtype type
, uint32_t num
, uint32_t * value
)
1236 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1237 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1239 /* NOTE: we "know" here that the register identifiers used
1240 * in the v7m header match the Cortex-M3 Debug Core Register
1241 * Selector values for R0..R15, xPSR, MSP, and PSP.
1245 /* read a normal core register */
1246 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1248 if (retval
!= ERROR_OK
)
1250 LOG_ERROR("JTAG failure %i",retval
);
1251 return ERROR_JTAG_DEVICE_ERROR
;
1253 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"",(int)num
,*value
);
1256 case ARMV7M_PRIMASK
:
1257 case ARMV7M_BASEPRI
:
1258 case ARMV7M_FAULTMASK
:
1259 case ARMV7M_CONTROL
:
1260 /* Cortex-M3 packages these four registers as bitfields
1261 * in one Debug Core register. So say r0 and r2 docs;
1262 * it was removed from r1 docs, but still works.
1264 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1268 case ARMV7M_PRIMASK
:
1269 *value
= buf_get_u32((uint8_t*)value
, 0, 1);
1272 case ARMV7M_BASEPRI
:
1273 *value
= buf_get_u32((uint8_t*)value
, 8, 8);
1276 case ARMV7M_FAULTMASK
:
1277 *value
= buf_get_u32((uint8_t*)value
, 16, 1);
1280 case ARMV7M_CONTROL
:
1281 *value
= buf_get_u32((uint8_t*)value
, 24, 2);
1285 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1289 return ERROR_INVALID_ARGUMENTS
;
1295 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1296 enum armv7m_regtype type
, uint32_t num
, uint32_t value
)
1300 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1301 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1303 #ifdef ARMV7_GDB_HACKS
1304 /* If the LR register is being modified, make sure it will put us
1305 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1306 * hack to deal with the fact that gdb will sometimes "forge"
1307 * return addresses, and doesn't set the LSB correctly (i.e., when
1308 * printing expressions containing function calls, it sets LR = 0.)
1309 * Valid exception return codes have bit 0 set too.
1311 if (num
== ARMV7M_R14
)
1315 /* NOTE: we "know" here that the register identifiers used
1316 * in the v7m header match the Cortex-M3 Debug Core Register
1317 * Selector values for R0..R15, xPSR, MSP, and PSP.
1321 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1322 if (retval
!= ERROR_OK
)
1324 LOG_ERROR("JTAG failure %i", retval
);
1325 armv7m
->core_cache
->reg_list
[num
].dirty
= armv7m
->core_cache
->reg_list
[num
].valid
;
1326 return ERROR_JTAG_DEVICE_ERROR
;
1328 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1331 case ARMV7M_PRIMASK
:
1332 case ARMV7M_BASEPRI
:
1333 case ARMV7M_FAULTMASK
:
1334 case ARMV7M_CONTROL
:
1335 /* Cortex-M3 packages these four registers as bitfields
1336 * in one Debug Core register. So say r0 and r2 docs;
1337 * it was removed from r1 docs, but still works.
1339 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1343 case ARMV7M_PRIMASK
:
1344 buf_set_u32((uint8_t*)®
, 0, 1, value
);
1347 case ARMV7M_BASEPRI
:
1348 buf_set_u32((uint8_t*)®
, 8, 8, value
);
1351 case ARMV7M_FAULTMASK
:
1352 buf_set_u32((uint8_t*)®
, 16, 1, value
);
1355 case ARMV7M_CONTROL
:
1356 buf_set_u32((uint8_t*)®
, 24, 2, value
);
1360 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1362 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1366 return ERROR_INVALID_ARGUMENTS
;
1372 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1373 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1375 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1376 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1379 /* sanitize arguments */
1380 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1381 return ERROR_INVALID_ARGUMENTS
;
1383 /* cortex_m3 handles unaligned memory access */
1388 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1391 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1394 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1397 LOG_ERROR("BUG: we shouldn't get here");
1404 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1405 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1407 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1408 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1411 /* sanitize arguments */
1412 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1413 return ERROR_INVALID_ARGUMENTS
;
1418 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1421 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1424 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1427 LOG_ERROR("BUG: we shouldn't get here");
1434 static int cortex_m3_bulk_write_memory(struct target
*target
, uint32_t address
,
1435 uint32_t count
, uint8_t *buffer
)
1437 return cortex_m3_write_memory(target
, address
, 4, count
, buffer
);
1440 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1441 struct target
*target
)
1443 armv7m_build_reg_cache(target
);
1447 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1448 * on r/w if the core is not running, and clear on resume or reset ... or
1449 * at least, in a post_restore_context() method.
1452 struct dwt_reg_state
{
1453 struct target
*target
;
1455 uint32_t value
; /* scratch/cache */
1458 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1460 struct dwt_reg_state
*state
= reg
->arch_info
;
1462 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1465 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1467 struct dwt_reg_state
*state
= reg
->arch_info
;
1469 return target_write_u32(state
->target
, state
->addr
,
1470 buf_get_u32(buf
, 0, reg
->size
));
1479 static struct dwt_reg dwt_base_regs
[] = {
1480 { DWT_CTRL
, "dwt_ctrl", 32, },
1481 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1482 /* plus some 8 bit counters, useful for profiling with TPIU */
1485 static struct dwt_reg dwt_comp
[] = {
1486 #define DWT_COMPARATOR(i) \
1487 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1488 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1489 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1494 #undef DWT_COMPARATOR
1497 static int dwt_reg_type
= -1;
1500 cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1502 struct dwt_reg_state
*state
;
1504 state
= calloc(1, sizeof *state
);
1507 state
->addr
= d
->addr
;
1512 r
->value
= &state
->value
;
1513 r
->arch_info
= state
;
1514 r
->arch_type
= dwt_reg_type
;
1518 cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1521 struct reg_cache
*cache
;
1522 struct cortex_m3_dwt_comparator
*comparator
;
1525 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1527 LOG_DEBUG("no DWT");
1531 if (dwt_reg_type
< 0)
1532 dwt_reg_type
= register_reg_arch_type(cortex_m3_dwt_get_reg
,
1533 cortex_m3_dwt_set_reg
);
1535 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1536 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1537 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1538 sizeof(struct cortex_m3_dwt_comparator
));
1539 if (!cm3
->dwt_comparator_list
) {
1541 cm3
->dwt_num_comp
= 0;
1542 LOG_ERROR("out of mem");
1546 cache
= calloc(1, sizeof *cache
);
1549 free(cm3
->dwt_comparator_list
);
1552 cache
->name
= "cortex-m3 dwt registers";
1553 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1554 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1555 if (!cache
->reg_list
) {
1560 for (reg
= 0; reg
< 2; reg
++)
1561 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1562 dwt_base_regs
+ reg
);
1564 comparator
= cm3
->dwt_comparator_list
;
1565 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1568 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1569 for (j
= 0; j
< 3; j
++, reg
++)
1570 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1571 dwt_comp
+ 3 * i
+ j
);
1574 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1575 cm3
->dwt_cache
= cache
;
1577 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1578 dwtcr
, cm3
->dwt_num_comp
,
1579 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1581 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1582 * implement single-address data value watchpoints ... so we
1583 * won't need to check it later, when asked to set one up.
1587 static int cortex_m3_examine(struct target
*target
)
1590 uint32_t cpuid
, fpcr
;
1592 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1593 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
1595 if ((retval
= ahbap_debugport_init(swjdp
)) != ERROR_OK
)
1598 if (!target_was_examined(target
))
1600 target_set_examined(target
);
1602 /* Read from Device Identification Registers */
1603 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1604 if (retval
!= ERROR_OK
)
1607 if (((cpuid
>> 4) & 0xc3f) == 0xc23)
1608 LOG_DEBUG("CORTEX-M3 processor detected");
1609 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1611 /* NOTE: FPB and DWT are both optional. */
1614 target_read_u32(target
, FP_CTRL
, &fpcr
);
1615 cortex_m3
->auto_bp_type
= 1;
1616 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits [14:12] and [7:4] */
1617 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1618 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1619 cortex_m3
->fp_comparator_list
= calloc(cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
, sizeof(struct cortex_m3_fp_comparator
));
1620 cortex_m3
->fpb_enabled
= fpcr
& 1;
1621 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
1623 cortex_m3
->fp_comparator_list
[i
].type
= (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1624 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1626 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i", fpcr
, cortex_m3
->fp_num_code
, cortex_m3
->fp_num_lit
);
1629 cortex_m3_dwt_setup(cortex_m3
, target
);
1635 static int cortex_m3_dcc_read(struct swjdp_common
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1639 mem_ap_read_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1640 *ctrl
= (uint8_t)dcrdr
;
1641 *value
= (uint8_t)(dcrdr
>> 8);
1643 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1645 /* write ack back to software dcc register
1646 * signify we have read data */
1647 if (dcrdr
& (1 << 0))
1650 mem_ap_write_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1656 static int cortex_m3_target_request_data(struct target
*target
,
1657 uint32_t size
, uint8_t *buffer
)
1659 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1660 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1665 for (i
= 0; i
< (size
* 4); i
++)
1667 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1674 static int cortex_m3_handle_target_request(void *priv
)
1676 struct target
*target
= priv
;
1677 if (!target_was_examined(target
))
1679 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1680 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1682 if (!target
->dbg_msg_enabled
)
1685 if (target
->state
== TARGET_RUNNING
)
1690 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1692 /* check if we have data */
1693 if (ctrl
& (1 << 0))
1697 /* we assume target is quick enough */
1699 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1700 request
|= (data
<< 8);
1701 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1702 request
|= (data
<< 16);
1703 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1704 request
|= (data
<< 24);
1705 target_request(target
, request
);
1712 static int cortex_m3_init_arch_info(struct target
*target
,
1713 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
1716 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1718 armv7m_init_arch_info(target
, armv7m
);
1720 /* prepare JTAG information for the new target */
1721 cortex_m3
->jtag_info
.tap
= tap
;
1722 cortex_m3
->jtag_info
.scann_size
= 4;
1724 armv7m
->swjdp_info
.dp_select_value
= -1;
1725 armv7m
->swjdp_info
.ap_csw_value
= -1;
1726 armv7m
->swjdp_info
.ap_tar_value
= -1;
1727 armv7m
->swjdp_info
.jtag_info
= &cortex_m3
->jtag_info
;
1728 armv7m
->swjdp_info
.memaccess_tck
= 8;
1729 armv7m
->swjdp_info
.tar_autoincr_block
= (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
1731 /* register arch-specific functions */
1732 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
1734 armv7m
->post_debug_entry
= NULL
;
1736 armv7m
->pre_restore_context
= NULL
;
1737 armv7m
->post_restore_context
= NULL
;
1739 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
1740 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
1742 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
1744 if ((retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
)) != ERROR_OK
)
1752 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
1754 struct cortex_m3_common
*cortex_m3
= calloc(1,sizeof(struct cortex_m3_common
));
1756 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
1757 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
1762 /*--------------------------------------------------------------------------*/
1764 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
1765 struct cortex_m3_common
*cm3
)
1767 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
1768 command_print(cmd_ctx
, "target is not a Cortex-M3");
1769 return ERROR_TARGET_INVALID
;
1775 * Only stuff below this line should need to verify that its target
1776 * is a Cortex-M3. Everything else should have indirected through the
1777 * cortexm3_target structure, which is only used with CM3 targets.
1781 * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1782 * as at least ARM-1156T2. The interesting thing about Cortex-M is
1783 * that *only* Thumb2 disassembly matters. There are also some small
1784 * additions to Thumb2 that are specific to ARMv7-M.
1786 COMMAND_HANDLER(handle_cortex_m3_disassemble_command
)
1789 struct target
*target
= get_current_target(cmd_ctx
);
1790 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1792 unsigned long count
= 1;
1793 struct arm_instruction cur_instruction
;
1795 retval
= cortex_m3_verify_pointer(cmd_ctx
, cortex_m3
);
1796 if (retval
!= ERROR_OK
)
1802 COMMAND_PARSE_NUMBER(ulong
, args
[1], count
);
1805 COMMAND_PARSE_NUMBER(u32
, args
[0], address
);
1808 command_print(cmd_ctx
,
1809 "usage: cortex_m3 disassemble <address> [<count>]");
1814 retval
= thumb2_opcode(target
, address
, &cur_instruction
);
1815 if (retval
!= ERROR_OK
)
1817 command_print(cmd_ctx
, "%s", cur_instruction
.text
);
1818 address
+= cur_instruction
.instruction_size
;
1824 static const struct {
1828 { "hard_err", VC_HARDERR
, },
1829 { "int_err", VC_INTERR
, },
1830 { "bus_err", VC_BUSERR
, },
1831 { "state_err", VC_STATERR
, },
1832 { "chk_err", VC_CHKERR
, },
1833 { "nocp_err", VC_NOCPERR
, },
1834 { "mm_err", VC_MMERR
, },
1835 { "reset", VC_CORERESET
, },
1838 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
1840 struct target
*target
= get_current_target(cmd_ctx
);
1841 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1842 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1843 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1848 retval
= cortex_m3_verify_pointer(cmd_ctx
, cortex_m3
);
1849 if (retval
!= ERROR_OK
)
1852 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1858 if (strcmp(args
[0], "all") == 0) {
1859 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
1860 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
1861 | VC_MMERR
| VC_CORERESET
;
1863 } else if (strcmp(args
[0], "none") == 0) {
1867 while (argc
-- > 0) {
1868 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
1869 if (strcmp(args
[argc
], vec_ids
[i
].name
) != 0)
1871 catch |= vec_ids
[i
].mask
;
1874 if (i
== ARRAY_SIZE(vec_ids
)) {
1875 LOG_ERROR("No CM3 vector '%s'", args
[argc
]);
1876 return ERROR_INVALID_ARGUMENTS
;
1883 /* write, but don't assume it stuck */
1884 mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
1885 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1888 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++)
1889 command_print(cmd_ctx
, "%9s: %s", vec_ids
[i
].name
,
1890 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
1895 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
1897 struct target
*target
= get_current_target(cmd_ctx
);
1898 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1901 retval
= cortex_m3_verify_pointer(cmd_ctx
, cortex_m3
);
1902 if (retval
!= ERROR_OK
)
1905 if (target
->state
!= TARGET_HALTED
)
1907 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", CMD_NAME
);
1913 if (!strcmp(args
[0], "on"))
1915 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
1917 else if (!strcmp(args
[0], "off"))
1919 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
1923 command_print(cmd_ctx
, "usage: cortex_m3 maskisr ['on'|'off']");
1927 command_print(cmd_ctx
, "cortex_m3 interrupt mask %s",
1928 (cortex_m3
->dcb_dhcsr
& C_MASKINTS
) ? "on" : "off");
1933 static int cortex_m3_register_commands(struct command_context
*cmd_ctx
)
1936 struct command
*cortex_m3_cmd
;
1938 retval
= armv7m_register_commands(cmd_ctx
);
1940 cortex_m3_cmd
= register_command(cmd_ctx
, NULL
, "cortex_m3",
1941 NULL
, COMMAND_ANY
, "cortex_m3 specific commands");
1943 register_command(cmd_ctx
, cortex_m3_cmd
, "disassemble",
1944 handle_cortex_m3_disassemble_command
, COMMAND_EXEC
,
1945 "disassemble Thumb2 instructions <address> [<count>]");
1946 register_command(cmd_ctx
, cortex_m3_cmd
, "maskisr",
1947 handle_cortex_m3_mask_interrupts_command
, COMMAND_EXEC
,
1948 "mask cortex_m3 interrupts ['on'|'off']");
1949 register_command(cmd_ctx
, cortex_m3_cmd
, "vector_catch",
1950 handle_cortex_m3_vector_catch_command
, COMMAND_EXEC
,
1951 "catch hardware vectors ['all'|'none'|<list>]");
1956 struct target_type cortexm3_target
=
1958 .name
= "cortex_m3",
1960 .poll
= cortex_m3_poll
,
1961 .arch_state
= armv7m_arch_state
,
1963 .target_request_data
= cortex_m3_target_request_data
,
1965 .halt
= cortex_m3_halt
,
1966 .resume
= cortex_m3_resume
,
1967 .step
= cortex_m3_step
,
1969 .assert_reset
= cortex_m3_assert_reset
,
1970 .deassert_reset
= cortex_m3_deassert_reset
,
1971 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
1973 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
1975 .read_memory
= cortex_m3_read_memory
,
1976 .write_memory
= cortex_m3_write_memory
,
1977 .bulk_write_memory
= cortex_m3_bulk_write_memory
,
1978 .checksum_memory
= armv7m_checksum_memory
,
1979 .blank_check_memory
= armv7m_blank_check_memory
,
1981 .run_algorithm
= armv7m_run_algorithm
,
1983 .add_breakpoint
= cortex_m3_add_breakpoint
,
1984 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
1985 .add_watchpoint
= cortex_m3_add_watchpoint
,
1986 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
1988 .register_commands
= cortex_m3_register_commands
,
1989 .target_create
= cortex_m3_target_create
,
1990 .init_target
= cortex_m3_init_target
,
1991 .examine
= cortex_m3_examine
,
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