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[openocd.git] / src / target / cortex_m3.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 * *
26 * *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
28 * *
29 ***************************************************************************/
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
39 #include "register.h"
40
41
42 /* NOTE: most of this should work fine for the Cortex-M1 and
43 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
44 */
45
46
47 /* forward declarations */
48 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
49 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
50 static void cortex_m3_enable_watchpoints(struct target *target);
51 static int cortex_m3_store_core_reg_u32(struct target *target,
52 enum armv7m_regtype type, uint32_t num, uint32_t value);
53
54 #ifdef ARMV7_GDB_HACKS
55 extern uint8_t armv7m_gdb_dummy_cpsr_value[];
56 extern struct reg armv7m_gdb_dummy_cpsr_reg;
57 #endif
58
59 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
60 uint32_t *value, int regnum)
61 {
62 int retval;
63 uint32_t dcrdr;
64
65 /* because the DCB_DCRDR is used for the emulated dcc channel
66 * we have to save/restore the DCB_DCRDR when used */
67
68 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
69
70 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
71
72 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
73 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
74 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
75
76 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
77 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
78 dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
79
80 retval = swjdp_transaction_endcheck(swjdp);
81
82 /* restore DCB_DCRDR - this needs to be in a seperate
83 * transaction otherwise the emulated DCC channel breaks */
84 if (retval == ERROR_OK)
85 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
86
87 return retval;
88 }
89
90 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
91 uint32_t value, int regnum)
92 {
93 int retval;
94 uint32_t dcrdr;
95
96 /* because the DCB_DCRDR is used for the emulated dcc channel
97 * we have to save/restore the DCB_DCRDR when used */
98
99 mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
100
101 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
102
103 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
104 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
105 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
106
107 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
108 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
109 dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
110
111 retval = swjdp_transaction_endcheck(swjdp);
112
113 /* restore DCB_DCRDR - this needs to be in a seperate
114 * transaction otherwise the emulated DCC channel breaks */
115 if (retval == ERROR_OK)
116 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
117
118 return retval;
119 }
120
121 static int cortex_m3_write_debug_halt_mask(struct target *target,
122 uint32_t mask_on, uint32_t mask_off)
123 {
124 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
125 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
126
127 /* mask off status bits */
128 cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
129 /* create new register mask */
130 cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
131
132 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
133 }
134
135 static int cortex_m3_clear_halt(struct target *target)
136 {
137 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
138 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
139
140 /* clear step if any */
141 cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
142
143 /* Read Debug Fault Status Register */
144 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
145 /* Clear Debug Fault Status */
146 mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
147 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
148
149 return ERROR_OK;
150 }
151
152 static int cortex_m3_single_step_core(struct target *target)
153 {
154 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
155 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
156 uint32_t dhcsr_save;
157
158 /* backup dhcsr reg */
159 dhcsr_save = cortex_m3->dcb_dhcsr;
160
161 /* mask interrupts if not done already */
162 if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
163 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
164 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
165 LOG_DEBUG(" ");
166
167 /* restore dhcsr reg */
168 cortex_m3->dcb_dhcsr = dhcsr_save;
169 cortex_m3_clear_halt(target);
170
171 return ERROR_OK;
172 }
173
174 static int cortex_m3_endreset_event(struct target *target)
175 {
176 int i;
177 uint32_t dcb_demcr;
178 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
179 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
180 struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
181 struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
182
183 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
184 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
185
186 /* this regsiter is used for emulated dcc channel */
187 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
188
189 /* Enable debug requests */
190 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
191 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
192 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
193
194 /* clear any interrupt masking */
195 cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
196
197 /* Enable trace and dwt */
198 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
199 /* Monitor bus faults */
200 mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
201
202 /* Enable FPB */
203 target_write_u32(target, FP_CTRL, 3);
204 cortex_m3->fpb_enabled = 1;
205
206 /* Restore FPB registers */
207 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
208 {
209 target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
210 }
211
212 /* Restore DWT registers */
213 for (i = 0; i < cortex_m3->dwt_num_comp; i++)
214 {
215 target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
216 dwt_list[i].comp);
217 target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
218 dwt_list[i].mask);
219 target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
220 dwt_list[i].function);
221 }
222 swjdp_transaction_endcheck(swjdp);
223
224 armv7m_invalidate_core_regs(target);
225
226 /* make sure we have latest dhcsr flags */
227 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
228
229 return ERROR_OK;
230 }
231
232 static int cortex_m3_examine_debug_reason(struct target *target)
233 {
234 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
235
236 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
237 /* only check the debug reason if we don't know it already */
238
239 if ((target->debug_reason != DBG_REASON_DBGRQ)
240 && (target->debug_reason != DBG_REASON_SINGLESTEP))
241 {
242 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
243 {
244 target->debug_reason = DBG_REASON_BREAKPOINT;
245 if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
246 target->debug_reason = DBG_REASON_WPTANDBKPT;
247 }
248 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
249 target->debug_reason = DBG_REASON_WATCHPOINT;
250 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
251 target->debug_reason = DBG_REASON_BREAKPOINT;
252 else /* EXTERNAL, HALTED */
253 target->debug_reason = DBG_REASON_UNDEFINED;
254 }
255
256 return ERROR_OK;
257 }
258
259 static int cortex_m3_examine_exception_reason(struct target *target)
260 {
261 uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
262 struct armv7m_common *armv7m = target_to_armv7m(target);
263 struct swjdp_common *swjdp = &armv7m->swjdp_info;
264
265 mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
266 switch (armv7m->exception_number)
267 {
268 case 2: /* NMI */
269 break;
270 case 3: /* Hard Fault */
271 mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
272 if (except_sr & 0x40000000)
273 {
274 mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
275 }
276 break;
277 case 4: /* Memory Management */
278 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
279 mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
280 break;
281 case 5: /* Bus Fault */
282 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
283 mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
284 break;
285 case 6: /* Usage Fault */
286 mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
287 break;
288 case 11: /* SVCall */
289 break;
290 case 12: /* Debug Monitor */
291 mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
292 break;
293 case 14: /* PendSV */
294 break;
295 case 15: /* SysTick */
296 break;
297 default:
298 except_sr = 0;
299 break;
300 }
301 swjdp_transaction_endcheck(swjdp);
302 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
303 shcsr, except_sr, cfsr, except_ar);
304 return ERROR_OK;
305 }
306
307 static int cortex_m3_debug_entry(struct target *target)
308 {
309 int i;
310 uint32_t xPSR;
311 int retval;
312 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
313 struct armv7m_common *armv7m = &cortex_m3->armv7m;
314 struct swjdp_common *swjdp = &armv7m->swjdp_info;
315
316 LOG_DEBUG(" ");
317
318 cortex_m3_clear_halt(target);
319 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
320
321 if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
322 return retval;
323
324 /* Examine target state and mode */
325 /* First load register acessible through core debug port*/
326 int num_regs = armv7m->core_cache->num_regs;
327
328 for (i = 0; i < num_regs; i++)
329 {
330 if (!armv7m->core_cache->reg_list[i].valid)
331 armv7m->read_core_reg(target, i);
332 }
333
334 xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
335
336 #ifdef ARMV7_GDB_HACKS
337 /* copy real xpsr reg for gdb, setting thumb bit */
338 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
339 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
340 armv7m_gdb_dummy_cpsr_reg.valid = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
341 armv7m_gdb_dummy_cpsr_reg.dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty;
342 #endif
343
344 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
345 if (xPSR & 0xf00)
346 {
347 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
348 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
349 }
350
351 /* Are we in an exception handler */
352 if (xPSR & 0x1FF)
353 {
354 armv7m->core_mode = ARMV7M_MODE_HANDLER;
355 armv7m->exception_number = (xPSR & 0x1FF);
356 }
357 else
358 {
359 armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
360 armv7m->exception_number = 0;
361 }
362
363 if (armv7m->exception_number)
364 {
365 cortex_m3_examine_exception_reason(target);
366 }
367
368 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
369 armv7m_mode_strings[armv7m->core_mode],
370 *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
371 target_state_name(target));
372
373 if (armv7m->post_debug_entry)
374 armv7m->post_debug_entry(target);
375
376 return ERROR_OK;
377 }
378
379 static int cortex_m3_poll(struct target *target)
380 {
381 int retval;
382 enum target_state prev_target_state = target->state;
383 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
384 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
385
386 /* Read from Debug Halting Control and Status Register */
387 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
388 if (retval != ERROR_OK)
389 {
390 target->state = TARGET_UNKNOWN;
391 return retval;
392 }
393
394 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
395 {
396 /* check if still in reset */
397 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
398
399 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
400 {
401 target->state = TARGET_RESET;
402 return ERROR_OK;
403 }
404 }
405
406 if (target->state == TARGET_RESET)
407 {
408 /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
409 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32 "", cortex_m3->dcb_dhcsr);
410 cortex_m3_endreset_event(target);
411 target->state = TARGET_RUNNING;
412 prev_target_state = TARGET_RUNNING;
413 }
414
415 if (cortex_m3->dcb_dhcsr & S_HALT)
416 {
417 target->state = TARGET_HALTED;
418
419 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
420 {
421 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
422 return retval;
423
424 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
425 }
426 if (prev_target_state == TARGET_DEBUG_RUNNING)
427 {
428 LOG_DEBUG(" ");
429 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
430 return retval;
431
432 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
433 }
434 }
435
436 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
437 * How best to model low power modes?
438 */
439
440 if (target->state == TARGET_UNKNOWN)
441 {
442 /* check if processor is retiring instructions */
443 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
444 {
445 target->state = TARGET_RUNNING;
446 return ERROR_OK;
447 }
448 }
449
450 return ERROR_OK;
451 }
452
453 static int cortex_m3_halt(struct target *target)
454 {
455 LOG_DEBUG("target->state: %s",
456 target_state_name(target));
457
458 if (target->state == TARGET_HALTED)
459 {
460 LOG_DEBUG("target was already halted");
461 return ERROR_OK;
462 }
463
464 if (target->state == TARGET_UNKNOWN)
465 {
466 LOG_WARNING("target was in unknown state when halt was requested");
467 }
468
469 if (target->state == TARGET_RESET)
470 {
471 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
472 {
473 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
474 return ERROR_TARGET_FAILURE;
475 }
476 else
477 {
478 /* we came here in a reset_halt or reset_init sequence
479 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
480 */
481 target->debug_reason = DBG_REASON_DBGRQ;
482
483 return ERROR_OK;
484 }
485 }
486
487 /* Write to Debug Halting Control and Status Register */
488 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
489
490 target->debug_reason = DBG_REASON_DBGRQ;
491
492 return ERROR_OK;
493 }
494
495 static int cortex_m3_soft_reset_halt(struct target *target)
496 {
497 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
498 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
499 uint32_t dcb_dhcsr = 0;
500 int retval, timeout = 0;
501
502 /* Enter debug state on reset, cf. end_reset_event() */
503 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
504
505 /* Request a reset */
506 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
507 target->state = TARGET_RESET;
508
509 /* registers are now invalid */
510 armv7m_invalidate_core_regs(target);
511
512 while (timeout < 100)
513 {
514 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
515 if (retval == ERROR_OK)
516 {
517 mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
518 if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
519 {
520 LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32 ", nvic_dfsr 0x%" PRIx32 "", dcb_dhcsr, cortex_m3->nvic_dfsr);
521 cortex_m3_poll(target);
522 return ERROR_OK;
523 }
524 else
525 LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32 ", %i ms", dcb_dhcsr, timeout);
526 }
527 timeout++;
528 alive_sleep(1);
529 }
530
531 return ERROR_OK;
532 }
533
534 static void cortex_m3_enable_breakpoints(struct target *target)
535 {
536 struct breakpoint *breakpoint = target->breakpoints;
537
538 /* set any pending breakpoints */
539 while (breakpoint)
540 {
541 if (breakpoint->set == 0)
542 cortex_m3_set_breakpoint(target, breakpoint);
543 breakpoint = breakpoint->next;
544 }
545 }
546
547 static int cortex_m3_resume(struct target *target, int current,
548 uint32_t address, int handle_breakpoints, int debug_execution)
549 {
550 struct armv7m_common *armv7m = target_to_armv7m(target);
551 struct breakpoint *breakpoint = NULL;
552 uint32_t resume_pc;
553
554 if (target->state != TARGET_HALTED)
555 {
556 LOG_WARNING("target not halted");
557 return ERROR_TARGET_NOT_HALTED;
558 }
559
560 if (!debug_execution)
561 {
562 target_free_all_working_areas(target);
563 cortex_m3_enable_breakpoints(target);
564 cortex_m3_enable_watchpoints(target);
565 }
566
567 if (debug_execution)
568 {
569 /* Disable interrupts */
570 /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
571 * This is probably the same issue as Cortex-M3 Errata 377493:
572 * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
573 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
574 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
575 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
576
577 /* Make sure we are in Thumb mode */
578 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
579 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
580 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
581 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
582 }
583
584 /* current = 1: continue on current pc, otherwise continue at <address> */
585 if (!current)
586 {
587 buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
588 armv7m->core_cache->reg_list[15].dirty = 1;
589 armv7m->core_cache->reg_list[15].valid = 1;
590 }
591
592 resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32);
593
594 armv7m_restore_context(target);
595
596 /* the front-end may request us not to handle breakpoints */
597 if (handle_breakpoints)
598 {
599 /* Single step past breakpoint at current address */
600 if ((breakpoint = breakpoint_find(target, resume_pc)))
601 {
602 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
603 breakpoint->address,
604 breakpoint->unique_id);
605 cortex_m3_unset_breakpoint(target, breakpoint);
606 cortex_m3_single_step_core(target);
607 cortex_m3_set_breakpoint(target, breakpoint);
608 }
609 }
610
611 /* Restart core */
612 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
613
614 target->debug_reason = DBG_REASON_NOTHALTED;
615
616 /* registers are now invalid */
617 armv7m_invalidate_core_regs(target);
618 if (!debug_execution)
619 {
620 target->state = TARGET_RUNNING;
621 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
622 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
623 }
624 else
625 {
626 target->state = TARGET_DEBUG_RUNNING;
627 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
628 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
629 }
630
631 return ERROR_OK;
632 }
633
634 /* int irqstepcount = 0; */
635 static int cortex_m3_step(struct target *target, int current,
636 uint32_t address, int handle_breakpoints)
637 {
638 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
639 struct armv7m_common *armv7m = &cortex_m3->armv7m;
640 struct swjdp_common *swjdp = &armv7m->swjdp_info;
641 struct breakpoint *breakpoint = NULL;
642
643 if (target->state != TARGET_HALTED)
644 {
645 LOG_WARNING("target not halted");
646 return ERROR_TARGET_NOT_HALTED;
647 }
648
649 /* current = 1: continue on current pc, otherwise continue at <address> */
650 if (!current)
651 buf_set_u32(cortex_m3->armv7m.core_cache->reg_list[15].value,
652 0, 32, address);
653
654 /* the front-end may request us not to handle breakpoints */
655 if (handle_breakpoints) {
656 breakpoint = breakpoint_find(target, buf_get_u32(armv7m
657 ->core_cache->reg_list[15].value, 0, 32));
658 if (breakpoint)
659 cortex_m3_unset_breakpoint(target, breakpoint);
660 }
661
662 target->debug_reason = DBG_REASON_SINGLESTEP;
663
664 armv7m_restore_context(target);
665
666 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
667
668 /* set step and clear halt */
669 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
670 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
671
672 /* registers are now invalid */
673 armv7m_invalidate_core_regs(target);
674
675 if (breakpoint)
676 cortex_m3_set_breakpoint(target, breakpoint);
677
678 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
679
680 cortex_m3_debug_entry(target);
681 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
682
683 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
684 return ERROR_OK;
685 }
686
687 static int cortex_m3_assert_reset(struct target *target)
688 {
689 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
690 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
691 int assert_srst = 1;
692
693 LOG_DEBUG("target->state: %s",
694 target_state_name(target));
695
696 enum reset_types jtag_reset_config = jtag_get_reset_config();
697
698 /*
699 * We can reset Cortex-M3 targets using just the NVIC without
700 * requiring SRST, getting a SoC reset (or a core-only reset)
701 * instead of a system reset.
702 */
703 if (!(jtag_reset_config & RESET_HAS_SRST))
704 assert_srst = 0;
705
706 /* Enable debug requests */
707 mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
708 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
709 mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
710
711 mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
712
713 if (!target->reset_halt)
714 {
715 /* Set/Clear C_MASKINTS in a separate operation */
716 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
717 mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
718
719 /* clear any debug flags before resuming */
720 cortex_m3_clear_halt(target);
721
722 /* clear C_HALT in dhcsr reg */
723 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
724
725 /* Enter debug state on reset, cf. end_reset_event() */
726 mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
727 }
728 else
729 {
730 /* Enter debug state on reset, cf. end_reset_event() */
731 mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
732 }
733
734 /*
735 * When nRST is asserted on most Stellaris devices, it clears some of
736 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
737 * and OpenOCD depends on those TRMs. So we won't use SRST on those
738 * chips. (Only power-on reset should affect debug state, beyond a
739 * few specified bits; not the chip's nRST input, wired to SRST.)
740 *
741 * REVISIT current errata specs don't seem to cover this issue.
742 * Do we have more details than this email?
743 * https://lists.berlios.de/pipermail
744 * /openocd-development/2008-August/003065.html
745 */
746 if (strcmp(target->variant, "lm3s") == 0)
747 {
748 /* Check for silicon revisions with the issue. */
749 uint32_t did0;
750
751 if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
752 {
753 switch ((did0 >> 16) & 0xff)
754 {
755 case 0:
756 /* all Sandstorm suffer issue */
757 assert_srst = 0;
758 break;
759
760 case 1:
761 case 3:
762 /* Fury and DustDevil rev A have
763 * this nRST problem. It should
764 * be fixed in rev B silicon.
765 */
766 if (((did0 >> 8) & 0xff) == 0)
767 assert_srst = 0;
768 break;
769 case 4:
770 /* Tempest should be fine. */
771 break;
772 }
773 }
774 }
775
776 if (assert_srst)
777 {
778 /* default to asserting srst */
779 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
780 {
781 jtag_add_reset(1, 1);
782 }
783 else
784 {
785 jtag_add_reset(0, 1);
786 }
787 }
788 else
789 {
790 /* Use a standard Cortex-M3 software reset mechanism.
791 * SYSRESETREQ will reset SoC peripherals outside the
792 * core, like watchdog timers, if the SoC wires it up
793 * correctly. Else VECRESET can reset just the core.
794 */
795 mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
796 AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
797 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
798
799 {
800 /* I do not know why this is necessary, but it
801 * fixes strange effects (step/resume cause NMI
802 * after reset) on LM3S6918 -- Michael Schwingen
803 */
804 uint32_t tmp;
805 mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
806 }
807 }
808
809 target->state = TARGET_RESET;
810 jtag_add_sleep(50000);
811
812 armv7m_invalidate_core_regs(target);
813
814 if (target->reset_halt)
815 {
816 int retval;
817 if ((retval = target_halt(target)) != ERROR_OK)
818 return retval;
819 }
820
821 return ERROR_OK;
822 }
823
824 static int cortex_m3_deassert_reset(struct target *target)
825 {
826 LOG_DEBUG("target->state: %s",
827 target_state_name(target));
828
829 /* deassert reset lines */
830 jtag_add_reset(0, 0);
831
832 return ERROR_OK;
833 }
834
835 static int
836 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
837 {
838 int retval;
839 int fp_num = 0;
840 uint32_t hilo;
841 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
842 struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
843
844 if (breakpoint->set)
845 {
846 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
847 return ERROR_OK;
848 }
849
850 if (cortex_m3->auto_bp_type)
851 {
852 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
853 }
854
855 if (breakpoint->type == BKPT_HARD)
856 {
857 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
858 fp_num++;
859 if (fp_num >= cortex_m3->fp_num_code)
860 {
861 LOG_ERROR("Can not find free FPB Comparator!");
862 return ERROR_FAIL;
863 }
864 breakpoint->set = fp_num + 1;
865 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
866 comparator_list[fp_num].used = 1;
867 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
868 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
869 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
870 if (!cortex_m3->fpb_enabled)
871 {
872 LOG_DEBUG("FPB wasn't enabled, do it now");
873 target_write_u32(target, FP_CTRL, 3);
874 }
875 }
876 else if (breakpoint->type == BKPT_SOFT)
877 {
878 uint8_t code[4];
879 buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
880 if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
881 {
882 return retval;
883 }
884 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
885 {
886 return retval;
887 }
888 breakpoint->set = 0x11; /* Any nice value but 0 */
889 }
890
891 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
892 breakpoint->unique_id,
893 (int)(breakpoint->type),
894 breakpoint->address,
895 breakpoint->length,
896 breakpoint->set);
897
898 return ERROR_OK;
899 }
900
901 static int
902 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
903 {
904 int retval;
905 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
906 struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
907
908 if (!breakpoint->set)
909 {
910 LOG_WARNING("breakpoint not set");
911 return ERROR_OK;
912 }
913
914 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
915 breakpoint->unique_id,
916 (int)(breakpoint->type),
917 breakpoint->address,
918 breakpoint->length,
919 breakpoint->set);
920
921 if (breakpoint->type == BKPT_HARD)
922 {
923 int fp_num = breakpoint->set - 1;
924 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
925 {
926 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
927 return ERROR_OK;
928 }
929 comparator_list[fp_num].used = 0;
930 comparator_list[fp_num].fpcr_value = 0;
931 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
932 }
933 else
934 {
935 /* restore original instruction (kept in target endianness) */
936 if (breakpoint->length == 4)
937 {
938 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
939 {
940 return retval;
941 }
942 }
943 else
944 {
945 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
946 {
947 return retval;
948 }
949 }
950 }
951 breakpoint->set = 0;
952
953 return ERROR_OK;
954 }
955
956 static int
957 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
958 {
959 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
960
961 if (cortex_m3->auto_bp_type)
962 {
963 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
964 #ifdef ARMV7_GDB_HACKS
965 if (breakpoint->length != 2) {
966 /* XXX Hack: Replace all breakpoints with length != 2 with
967 * a hardware breakpoint. */
968 breakpoint->type = BKPT_HARD;
969 breakpoint->length = 2;
970 }
971 #endif
972 }
973
974 if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
975 {
976 LOG_INFO("flash patch comparator requested outside code memory region");
977 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
978 }
979
980 if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
981 {
982 LOG_INFO("soft breakpoint requested in code (flash) memory region");
983 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
984 }
985
986 if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
987 {
988 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
989 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
990 }
991
992 if ((breakpoint->length != 2))
993 {
994 LOG_INFO("only breakpoints of two bytes length supported");
995 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
996 }
997
998 if (breakpoint->type == BKPT_HARD)
999 cortex_m3->fp_code_available--;
1000 cortex_m3_set_breakpoint(target, breakpoint);
1001
1002 return ERROR_OK;
1003 }
1004
1005 static int
1006 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1007 {
1008 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1009
1010 /* REVISIT why check? FBP can be updated with core running ... */
1011 if (target->state != TARGET_HALTED)
1012 {
1013 LOG_WARNING("target not halted");
1014 return ERROR_TARGET_NOT_HALTED;
1015 }
1016
1017 if (cortex_m3->auto_bp_type)
1018 {
1019 breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
1020 }
1021
1022 if (breakpoint->set)
1023 {
1024 cortex_m3_unset_breakpoint(target, breakpoint);
1025 }
1026
1027 if (breakpoint->type == BKPT_HARD)
1028 cortex_m3->fp_code_available++;
1029
1030 return ERROR_OK;
1031 }
1032
1033 static int
1034 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1035 {
1036 int dwt_num = 0;
1037 uint32_t mask, temp;
1038 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1039
1040 /* watchpoint params were validated earlier */
1041 mask = 0;
1042 temp = watchpoint->length;
1043 while (temp) {
1044 temp >>= 1;
1045 mask++;
1046 }
1047 mask--;
1048
1049 /* REVISIT Don't fully trust these "not used" records ... users
1050 * may set up breakpoints by hand, e.g. dual-address data value
1051 * watchpoint using comparator #1; comparator #0 matching cycle
1052 * count; send data trace info through ITM and TPIU; etc
1053 */
1054 struct cortex_m3_dwt_comparator *comparator;
1055
1056 for (comparator = cortex_m3->dwt_comparator_list;
1057 comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1058 comparator++, dwt_num++)
1059 continue;
1060 if (dwt_num >= cortex_m3->dwt_num_comp)
1061 {
1062 LOG_ERROR("Can not find free DWT Comparator");
1063 return ERROR_FAIL;
1064 }
1065 comparator->used = 1;
1066 watchpoint->set = dwt_num + 1;
1067
1068 comparator->comp = watchpoint->address;
1069 target_write_u32(target, comparator->dwt_comparator_address + 0,
1070 comparator->comp);
1071
1072 comparator->mask = mask;
1073 target_write_u32(target, comparator->dwt_comparator_address + 4,
1074 comparator->mask);
1075
1076 switch (watchpoint->rw) {
1077 case WPT_READ:
1078 comparator->function = 5;
1079 break;
1080 case WPT_WRITE:
1081 comparator->function = 6;
1082 break;
1083 case WPT_ACCESS:
1084 comparator->function = 7;
1085 break;
1086 }
1087 target_write_u32(target, comparator->dwt_comparator_address + 8,
1088 comparator->function);
1089
1090 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1091 watchpoint->unique_id, dwt_num,
1092 (unsigned) comparator->comp,
1093 (unsigned) comparator->mask,
1094 (unsigned) comparator->function);
1095 return ERROR_OK;
1096 }
1097
1098 static int
1099 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1100 {
1101 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1102 struct cortex_m3_dwt_comparator *comparator;
1103 int dwt_num;
1104
1105 if (!watchpoint->set)
1106 {
1107 LOG_WARNING("watchpoint (wpid: %d) not set",
1108 watchpoint->unique_id);
1109 return ERROR_OK;
1110 }
1111
1112 dwt_num = watchpoint->set - 1;
1113
1114 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1115 watchpoint->unique_id, dwt_num,
1116 (unsigned) watchpoint->address);
1117
1118 if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1119 {
1120 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1121 return ERROR_OK;
1122 }
1123
1124 comparator = cortex_m3->dwt_comparator_list + dwt_num;
1125 comparator->used = 0;
1126 comparator->function = 0;
1127 target_write_u32(target, comparator->dwt_comparator_address + 8,
1128 comparator->function);
1129
1130 watchpoint->set = 0;
1131
1132 return ERROR_OK;
1133 }
1134
1135 static int
1136 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1137 {
1138 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1139
1140 /* REVISIT why check? DWT can be updated with core running ... */
1141 if (target->state != TARGET_HALTED)
1142 {
1143 LOG_WARNING("target not halted");
1144 return ERROR_TARGET_NOT_HALTED;
1145 }
1146
1147 if (cortex_m3->dwt_comp_available < 1)
1148 {
1149 LOG_DEBUG("no comparators?");
1150 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1151 }
1152
1153 /* hardware doesn't support data value masking */
1154 if (watchpoint->mask != ~(uint32_t)0) {
1155 LOG_DEBUG("watchpoint value masks not supported");
1156 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1157 }
1158
1159 /* hardware allows address masks of up to 32K */
1160 unsigned mask;
1161
1162 for (mask = 0; mask < 16; mask++) {
1163 if ((1u << mask) == watchpoint->length)
1164 break;
1165 }
1166 if (mask == 16) {
1167 LOG_DEBUG("unsupported watchpoint length");
1168 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1169 }
1170 if (watchpoint->address & ((1 << mask) - 1)) {
1171 LOG_DEBUG("watchpoint address is unaligned");
1172 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1173 }
1174
1175 /* Caller doesn't seem to be able to describe watching for data
1176 * values of zero; that flags "no value".
1177 *
1178 * REVISIT This DWT may well be able to watch for specific data
1179 * values. Requires comparator #1 to set DATAVMATCH and match
1180 * the data, and another comparator (DATAVADDR0) matching addr.
1181 */
1182 if (watchpoint->value) {
1183 LOG_DEBUG("data value watchpoint not YET supported");
1184 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1185 }
1186
1187 cortex_m3->dwt_comp_available--;
1188 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1189
1190 return ERROR_OK;
1191 }
1192
1193 static int
1194 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1195 {
1196 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1197
1198 /* REVISIT why check? DWT can be updated with core running ... */
1199 if (target->state != TARGET_HALTED)
1200 {
1201 LOG_WARNING("target not halted");
1202 return ERROR_TARGET_NOT_HALTED;
1203 }
1204
1205 if (watchpoint->set)
1206 {
1207 cortex_m3_unset_watchpoint(target, watchpoint);
1208 }
1209
1210 cortex_m3->dwt_comp_available++;
1211 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1212
1213 return ERROR_OK;
1214 }
1215
1216 static void cortex_m3_enable_watchpoints(struct target *target)
1217 {
1218 struct watchpoint *watchpoint = target->watchpoints;
1219
1220 /* set any pending watchpoints */
1221 while (watchpoint)
1222 {
1223 if (watchpoint->set == 0)
1224 cortex_m3_set_watchpoint(target, watchpoint);
1225 watchpoint = watchpoint->next;
1226 }
1227 }
1228
1229 static int cortex_m3_load_core_reg_u32(struct target *target,
1230 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1231 {
1232 int retval;
1233 struct armv7m_common *armv7m = target_to_armv7m(target);
1234 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1235
1236 /* NOTE: we "know" here that the register identifiers used
1237 * in the v7m header match the Cortex-M3 Debug Core Register
1238 * Selector values for R0..R15, xPSR, MSP, and PSP.
1239 */
1240 switch (num) {
1241 case 0 ... 18:
1242 /* read a normal core register */
1243 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1244
1245 if (retval != ERROR_OK)
1246 {
1247 LOG_ERROR("JTAG failure %i",retval);
1248 return ERROR_JTAG_DEVICE_ERROR;
1249 }
1250 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
1251 break;
1252
1253 case ARMV7M_PRIMASK:
1254 case ARMV7M_BASEPRI:
1255 case ARMV7M_FAULTMASK:
1256 case ARMV7M_CONTROL:
1257 /* Cortex-M3 packages these four registers as bitfields
1258 * in one Debug Core register. So say r0 and r2 docs;
1259 * it was removed from r1 docs, but still works.
1260 */
1261 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1262
1263 switch (num)
1264 {
1265 case ARMV7M_PRIMASK:
1266 *value = buf_get_u32((uint8_t*)value, 0, 1);
1267 break;
1268
1269 case ARMV7M_BASEPRI:
1270 *value = buf_get_u32((uint8_t*)value, 8, 8);
1271 break;
1272
1273 case ARMV7M_FAULTMASK:
1274 *value = buf_get_u32((uint8_t*)value, 16, 1);
1275 break;
1276
1277 case ARMV7M_CONTROL:
1278 *value = buf_get_u32((uint8_t*)value, 24, 2);
1279 break;
1280 }
1281
1282 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1283 break;
1284
1285 default:
1286 return ERROR_INVALID_ARGUMENTS;
1287 }
1288
1289 return ERROR_OK;
1290 }
1291
1292 static int cortex_m3_store_core_reg_u32(struct target *target,
1293 enum armv7m_regtype type, uint32_t num, uint32_t value)
1294 {
1295 int retval;
1296 uint32_t reg;
1297 struct armv7m_common *armv7m = target_to_armv7m(target);
1298 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1299
1300 #ifdef ARMV7_GDB_HACKS
1301 /* If the LR register is being modified, make sure it will put us
1302 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1303 * hack to deal with the fact that gdb will sometimes "forge"
1304 * return addresses, and doesn't set the LSB correctly (i.e., when
1305 * printing expressions containing function calls, it sets LR = 0.)
1306 * Valid exception return codes have bit 0 set too.
1307 */
1308 if (num == ARMV7M_R14)
1309 value |= 0x01;
1310 #endif
1311
1312 /* NOTE: we "know" here that the register identifiers used
1313 * in the v7m header match the Cortex-M3 Debug Core Register
1314 * Selector values for R0..R15, xPSR, MSP, and PSP.
1315 */
1316 switch (num) {
1317 case 0 ... 18:
1318 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1319 if (retval != ERROR_OK)
1320 {
1321 LOG_ERROR("JTAG failure %i", retval);
1322 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
1323 return ERROR_JTAG_DEVICE_ERROR;
1324 }
1325 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1326 break;
1327
1328 case ARMV7M_PRIMASK:
1329 case ARMV7M_BASEPRI:
1330 case ARMV7M_FAULTMASK:
1331 case ARMV7M_CONTROL:
1332 /* Cortex-M3 packages these four registers as bitfields
1333 * in one Debug Core register. So say r0 and r2 docs;
1334 * it was removed from r1 docs, but still works.
1335 */
1336 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1337
1338 switch (num)
1339 {
1340 case ARMV7M_PRIMASK:
1341 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1342 break;
1343
1344 case ARMV7M_BASEPRI:
1345 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1346 break;
1347
1348 case ARMV7M_FAULTMASK:
1349 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1350 break;
1351
1352 case ARMV7M_CONTROL:
1353 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1354 break;
1355 }
1356
1357 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1358
1359 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1360 break;
1361
1362 default:
1363 return ERROR_INVALID_ARGUMENTS;
1364 }
1365
1366 return ERROR_OK;
1367 }
1368
1369 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1370 uint32_t size, uint32_t count, uint8_t *buffer)
1371 {
1372 struct armv7m_common *armv7m = target_to_armv7m(target);
1373 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1374 int retval = ERROR_INVALID_ARGUMENTS;
1375
1376 /* cortex_m3 handles unaligned memory access */
1377 if (count && buffer) {
1378 switch (size) {
1379 case 4:
1380 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1381 break;
1382 case 2:
1383 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1384 break;
1385 case 1:
1386 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1387 break;
1388 }
1389 }
1390
1391 return retval;
1392 }
1393
1394 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1395 uint32_t size, uint32_t count, uint8_t *buffer)
1396 {
1397 struct armv7m_common *armv7m = target_to_armv7m(target);
1398 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1399 int retval = ERROR_INVALID_ARGUMENTS;
1400
1401 if (count && buffer) {
1402 switch (size) {
1403 case 4:
1404 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1405 break;
1406 case 2:
1407 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1408 break;
1409 case 1:
1410 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1411 break;
1412 }
1413 }
1414
1415 return retval;
1416 }
1417
1418 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1419 uint32_t count, uint8_t *buffer)
1420 {
1421 return cortex_m3_write_memory(target, address, 4, count, buffer);
1422 }
1423
1424 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1425 struct target *target)
1426 {
1427 armv7m_build_reg_cache(target);
1428 return ERROR_OK;
1429 }
1430
1431 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1432 * on r/w if the core is not running, and clear on resume or reset ... or
1433 * at least, in a post_restore_context() method.
1434 */
1435
1436 struct dwt_reg_state {
1437 struct target *target;
1438 uint32_t addr;
1439 uint32_t value; /* scratch/cache */
1440 };
1441
1442 static int cortex_m3_dwt_get_reg(struct reg *reg)
1443 {
1444 struct dwt_reg_state *state = reg->arch_info;
1445
1446 return target_read_u32(state->target, state->addr, &state->value);
1447 }
1448
1449 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1450 {
1451 struct dwt_reg_state *state = reg->arch_info;
1452
1453 return target_write_u32(state->target, state->addr,
1454 buf_get_u32(buf, 0, reg->size));
1455 }
1456
1457 struct dwt_reg {
1458 uint32_t addr;
1459 char *name;
1460 unsigned size;
1461 };
1462
1463 static struct dwt_reg dwt_base_regs[] = {
1464 { DWT_CTRL, "dwt_ctrl", 32, },
1465 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1466 /* plus some 8 bit counters, useful for profiling with TPIU */
1467 };
1468
1469 static struct dwt_reg dwt_comp[] = {
1470 #define DWT_COMPARATOR(i) \
1471 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1472 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1473 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1474 DWT_COMPARATOR(0),
1475 DWT_COMPARATOR(1),
1476 DWT_COMPARATOR(2),
1477 DWT_COMPARATOR(3),
1478 #undef DWT_COMPARATOR
1479 };
1480
1481 static const struct reg_arch_type dwt_reg_type = {
1482 .get = cortex_m3_dwt_get_reg,
1483 .set = cortex_m3_dwt_set_reg,
1484 };
1485
1486 static void
1487 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1488 {
1489 struct dwt_reg_state *state;
1490
1491 state = calloc(1, sizeof *state);
1492 if (!state)
1493 return;
1494 state->addr = d->addr;
1495 state->target = t;
1496
1497 r->name = d->name;
1498 r->size = d->size;
1499 r->value = &state->value;
1500 r->arch_info = state;
1501 r->type = &dwt_reg_type;
1502 }
1503
1504 static void
1505 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1506 {
1507 uint32_t dwtcr;
1508 struct reg_cache *cache;
1509 struct cortex_m3_dwt_comparator *comparator;
1510 int reg, i;
1511
1512 target_read_u32(target, DWT_CTRL, &dwtcr);
1513 if (!dwtcr) {
1514 LOG_DEBUG("no DWT");
1515 return;
1516 }
1517
1518 cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1519 cm3->dwt_comp_available = cm3->dwt_num_comp;
1520 cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1521 sizeof(struct cortex_m3_dwt_comparator));
1522 if (!cm3->dwt_comparator_list) {
1523 fail0:
1524 cm3->dwt_num_comp = 0;
1525 LOG_ERROR("out of mem");
1526 return;
1527 }
1528
1529 cache = calloc(1, sizeof *cache);
1530 if (!cache) {
1531 fail1:
1532 free(cm3->dwt_comparator_list);
1533 goto fail0;
1534 }
1535 cache->name = "cortex-m3 dwt registers";
1536 cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1537 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1538 if (!cache->reg_list) {
1539 free(cache);
1540 goto fail1;
1541 }
1542
1543 for (reg = 0; reg < 2; reg++)
1544 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1545 dwt_base_regs + reg);
1546
1547 comparator = cm3->dwt_comparator_list;
1548 for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1549 int j;
1550
1551 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1552 for (j = 0; j < 3; j++, reg++)
1553 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1554 dwt_comp + 3 * i + j);
1555 }
1556
1557 *register_get_last_cache_p(&target->reg_cache) = cache;
1558 cm3->dwt_cache = cache;
1559
1560 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1561 dwtcr, cm3->dwt_num_comp,
1562 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1563
1564 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1565 * implement single-address data value watchpoints ... so we
1566 * won't need to check it later, when asked to set one up.
1567 */
1568 }
1569
1570 static int cortex_m3_examine(struct target *target)
1571 {
1572 int retval;
1573 uint32_t cpuid, fpcr;
1574 int i;
1575 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1576 struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
1577
1578 if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1579 return retval;
1580
1581 if (!target_was_examined(target))
1582 {
1583 target_set_examined(target);
1584
1585 /* Read from Device Identification Registers */
1586 retval = target_read_u32(target, CPUID, &cpuid);
1587 if (retval != ERROR_OK)
1588 return retval;
1589
1590 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1591 LOG_DEBUG("CORTEX-M3 processor detected");
1592 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1593
1594 /* NOTE: FPB and DWT are both optional. */
1595
1596 /* Setup FPB */
1597 target_read_u32(target, FP_CTRL, &fpcr);
1598 cortex_m3->auto_bp_type = 1;
1599 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1600 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1601 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1602 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1603 cortex_m3->fpb_enabled = fpcr & 1;
1604 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1605 {
1606 cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1607 cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1608 }
1609 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1610
1611 /* Setup DWT */
1612 cortex_m3_dwt_setup(cortex_m3, target);
1613 }
1614
1615 return ERROR_OK;
1616 }
1617
1618 static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1619 {
1620 uint16_t dcrdr;
1621
1622 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1623 *ctrl = (uint8_t)dcrdr;
1624 *value = (uint8_t)(dcrdr >> 8);
1625
1626 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1627
1628 /* write ack back to software dcc register
1629 * signify we have read data */
1630 if (dcrdr & (1 << 0))
1631 {
1632 dcrdr = 0;
1633 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1634 }
1635
1636 return ERROR_OK;
1637 }
1638
1639 static int cortex_m3_target_request_data(struct target *target,
1640 uint32_t size, uint8_t *buffer)
1641 {
1642 struct armv7m_common *armv7m = target_to_armv7m(target);
1643 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1644 uint8_t data;
1645 uint8_t ctrl;
1646 uint32_t i;
1647
1648 for (i = 0; i < (size * 4); i++)
1649 {
1650 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1651 buffer[i] = data;
1652 }
1653
1654 return ERROR_OK;
1655 }
1656
1657 static int cortex_m3_handle_target_request(void *priv)
1658 {
1659 struct target *target = priv;
1660 if (!target_was_examined(target))
1661 return ERROR_OK;
1662 struct armv7m_common *armv7m = target_to_armv7m(target);
1663 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1664
1665 if (!target->dbg_msg_enabled)
1666 return ERROR_OK;
1667
1668 if (target->state == TARGET_RUNNING)
1669 {
1670 uint8_t data;
1671 uint8_t ctrl;
1672
1673 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1674
1675 /* check if we have data */
1676 if (ctrl & (1 << 0))
1677 {
1678 uint32_t request;
1679
1680 /* we assume target is quick enough */
1681 request = data;
1682 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1683 request |= (data << 8);
1684 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1685 request |= (data << 16);
1686 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1687 request |= (data << 24);
1688 target_request(target, request);
1689 }
1690 }
1691
1692 return ERROR_OK;
1693 }
1694
1695 static int cortex_m3_init_arch_info(struct target *target,
1696 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1697 {
1698 int retval;
1699 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1700
1701 armv7m_init_arch_info(target, armv7m);
1702
1703 /* prepare JTAG information for the new target */
1704 cortex_m3->jtag_info.tap = tap;
1705 cortex_m3->jtag_info.scann_size = 4;
1706
1707 armv7m->swjdp_info.dp_select_value = -1;
1708 armv7m->swjdp_info.ap_csw_value = -1;
1709 armv7m->swjdp_info.ap_tar_value = -1;
1710 armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
1711 armv7m->swjdp_info.memaccess_tck = 8;
1712 armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
1713
1714 /* register arch-specific functions */
1715 armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1716
1717 armv7m->post_debug_entry = NULL;
1718
1719 armv7m->pre_restore_context = NULL;
1720 armv7m->post_restore_context = NULL;
1721
1722 armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1723 armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1724
1725 target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1726
1727 if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
1728 {
1729 return retval;
1730 }
1731
1732 return ERROR_OK;
1733 }
1734
1735 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1736 {
1737 struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
1738
1739 cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1740 cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1741
1742 return ERROR_OK;
1743 }
1744
1745 /*--------------------------------------------------------------------------*/
1746
1747 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1748 struct cortex_m3_common *cm3)
1749 {
1750 if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1751 command_print(cmd_ctx, "target is not a Cortex-M3");
1752 return ERROR_TARGET_INVALID;
1753 }
1754 return ERROR_OK;
1755 }
1756
1757 /*
1758 * Only stuff below this line should need to verify that its target
1759 * is a Cortex-M3. Everything else should have indirected through the
1760 * cortexm3_target structure, which is only used with CM3 targets.
1761 */
1762
1763 /*
1764 * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1765 * as at least ARM-1156T2. The interesting thing about Cortex-M is
1766 * that *only* Thumb2 disassembly matters. There are also some small
1767 * additions to Thumb2 that are specific to ARMv7-M.
1768 */
1769 COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
1770 {
1771 int retval;
1772 struct target *target = get_current_target(CMD_CTX);
1773 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1774 uint32_t address;
1775 unsigned long count = 1;
1776 struct arm_instruction cur_instruction;
1777
1778 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1779 if (retval != ERROR_OK)
1780 return retval;
1781
1782 errno = 0;
1783 switch (CMD_ARGC) {
1784 case 2:
1785 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count);
1786 /* FALL THROUGH */
1787 case 1:
1788 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1789 break;
1790 default:
1791 command_print(CMD_CTX,
1792 "usage: cortex_m3 disassemble <address> [<count>]");
1793 return ERROR_OK;
1794 }
1795
1796 while (count--) {
1797 retval = thumb2_opcode(target, address, &cur_instruction);
1798 if (retval != ERROR_OK)
1799 return retval;
1800 command_print(CMD_CTX, "%s", cur_instruction.text);
1801 address += cur_instruction.instruction_size;
1802 }
1803
1804 return ERROR_OK;
1805 }
1806
1807 static const struct {
1808 char name[10];
1809 unsigned mask;
1810 } vec_ids[] = {
1811 { "hard_err", VC_HARDERR, },
1812 { "int_err", VC_INTERR, },
1813 { "bus_err", VC_BUSERR, },
1814 { "state_err", VC_STATERR, },
1815 { "chk_err", VC_CHKERR, },
1816 { "nocp_err", VC_NOCPERR, },
1817 { "mm_err", VC_MMERR, },
1818 { "reset", VC_CORERESET, },
1819 };
1820
1821 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1822 {
1823 struct target *target = get_current_target(CMD_CTX);
1824 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1825 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1826 struct swjdp_common *swjdp = &armv7m->swjdp_info;
1827 uint32_t demcr = 0;
1828 int retval;
1829
1830 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1831 if (retval != ERROR_OK)
1832 return retval;
1833
1834 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1835
1836 if (CMD_ARGC > 0) {
1837 unsigned catch = 0;
1838
1839 if (CMD_ARGC == 1) {
1840 if (strcmp(CMD_ARGV[0], "all") == 0) {
1841 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
1842 | VC_STATERR | VC_CHKERR | VC_NOCPERR
1843 | VC_MMERR | VC_CORERESET;
1844 goto write;
1845 } else if (strcmp(CMD_ARGV[0], "none") == 0) {
1846 goto write;
1847 }
1848 }
1849 while (CMD_ARGC-- > 0) {
1850 unsigned i;
1851 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
1852 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
1853 continue;
1854 catch |= vec_ids[i].mask;
1855 break;
1856 }
1857 if (i == ARRAY_SIZE(vec_ids)) {
1858 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
1859 return ERROR_INVALID_ARGUMENTS;
1860 }
1861 }
1862 write:
1863 demcr &= ~0xffff;
1864 demcr |= catch;
1865
1866 /* write, but don't assume it stuck */
1867 mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
1868 mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1869 }
1870
1871 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
1872 {
1873 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
1874 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
1875 }
1876
1877 return ERROR_OK;
1878 }
1879
1880 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
1881 {
1882 struct target *target = get_current_target(CMD_CTX);
1883 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1884 int retval;
1885
1886 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1887 if (retval != ERROR_OK)
1888 return retval;
1889
1890 if (target->state != TARGET_HALTED)
1891 {
1892 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1893 return ERROR_OK;
1894 }
1895
1896 if (CMD_ARGC > 0)
1897 {
1898 if (!strcmp(CMD_ARGV[0], "on"))
1899 {
1900 cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
1901 }
1902 else if (!strcmp(CMD_ARGV[0], "off"))
1903 {
1904 cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
1905 }
1906 else
1907 {
1908 command_print(CMD_CTX, "usage: cortex_m3 maskisr ['on'|'off']");
1909 }
1910 }
1911
1912 command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
1913 (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
1914
1915 return ERROR_OK;
1916 }
1917
1918 static int cortex_m3_register_commands(struct command_context *cmd_ctx)
1919 {
1920 int retval;
1921 struct command *cortex_m3_cmd;
1922
1923 retval = armv7m_register_commands(cmd_ctx);
1924
1925 cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3",
1926 NULL, COMMAND_ANY, "cortex_m3 specific commands");
1927
1928 register_command(cmd_ctx, cortex_m3_cmd, "disassemble",
1929 handle_cortex_m3_disassemble_command, COMMAND_EXEC,
1930 "disassemble Thumb2 instructions <address> [<count>]");
1931 register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
1932 handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC,
1933 "mask cortex_m3 interrupts ['on'|'off']");
1934 register_command(cmd_ctx, cortex_m3_cmd, "vector_catch",
1935 handle_cortex_m3_vector_catch_command, COMMAND_EXEC,
1936 "catch hardware vectors ['all'|'none'|<list>]");
1937
1938 return retval;
1939 }
1940
1941 struct target_type cortexm3_target =
1942 {
1943 .name = "cortex_m3",
1944
1945 .poll = cortex_m3_poll,
1946 .arch_state = armv7m_arch_state,
1947
1948 .target_request_data = cortex_m3_target_request_data,
1949
1950 .halt = cortex_m3_halt,
1951 .resume = cortex_m3_resume,
1952 .step = cortex_m3_step,
1953
1954 .assert_reset = cortex_m3_assert_reset,
1955 .deassert_reset = cortex_m3_deassert_reset,
1956 .soft_reset_halt = cortex_m3_soft_reset_halt,
1957
1958 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
1959
1960 .read_memory = cortex_m3_read_memory,
1961 .write_memory = cortex_m3_write_memory,
1962 .bulk_write_memory = cortex_m3_bulk_write_memory,
1963 .checksum_memory = armv7m_checksum_memory,
1964 .blank_check_memory = armv7m_blank_check_memory,
1965
1966 .run_algorithm = armv7m_run_algorithm,
1967
1968 .add_breakpoint = cortex_m3_add_breakpoint,
1969 .remove_breakpoint = cortex_m3_remove_breakpoint,
1970 .add_watchpoint = cortex_m3_add_watchpoint,
1971 .remove_watchpoint = cortex_m3_remove_watchpoint,
1972
1973 .register_commands = cortex_m3_register_commands,
1974 .target_create = cortex_m3_target_create,
1975 .init_target = cortex_m3_init_target,
1976 .examine = cortex_m3_examine,
1977 };
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