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[openocd.git] / src / target / cortex_m3.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 * *
26 * *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
28 * *
29 ***************************************************************************/
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
39 #include "register.h"
40 #include "arm_opcodes.h"
41 #include "arm_semihosting.h"
42 #include <helper/time_support.h>
43
44 /* NOTE: most of this should work fine for the Cortex-M1 and
45 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
46 * Some differences: M0/M1 doesn't have FBP remapping or the
47 * DWT tracing/profiling support. (So the cycle counter will
48 * not be usable; the other stuff isn't currently used here.)
49 *
50 * Although there are some workarounds for errata seen only in r0p0
51 * silicon, such old parts are hard to find and thus not much tested
52 * any longer.
53 */
54
55 /**
56 * Returns the type of a break point required by address location
57 */
58 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
59
60
61 /* forward declarations */
62 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
63 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
64 static void cortex_m3_enable_watchpoints(struct target *target);
65 static int cortex_m3_store_core_reg_u32(struct target *target,
66 enum armv7m_regtype type, uint32_t num, uint32_t value);
67
68 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
69 uint32_t *value, int regnum)
70 {
71 int retval;
72 uint32_t dcrdr;
73
74 /* because the DCB_DCRDR is used for the emulated dcc channel
75 * we have to save/restore the DCB_DCRDR when used */
76
77 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
78 if (retval != ERROR_OK)
79 return retval;
80
81 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
82 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
83 if (retval != ERROR_OK)
84 return retval;
85 retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
86 if (retval != ERROR_OK)
87 return retval;
88
89 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
90 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
91 if (retval != ERROR_OK)
92 return retval;
93 retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
94 if (retval != ERROR_OK)
95 return retval;
96
97 retval = dap_run(swjdp);
98 if (retval != ERROR_OK)
99 return retval;
100
101 /* restore DCB_DCRDR - this needs to be in a seperate
102 * transaction otherwise the emulated DCC channel breaks */
103 if (retval == ERROR_OK)
104 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
105
106 return retval;
107 }
108
109 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
110 uint32_t value, int regnum)
111 {
112 int retval;
113 uint32_t dcrdr;
114
115 /* because the DCB_DCRDR is used for the emulated dcc channel
116 * we have to save/restore the DCB_DCRDR when used */
117
118 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
119 if (retval != ERROR_OK)
120 return retval;
121
122 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
123 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
124 if (retval != ERROR_OK)
125 return retval;
126 retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
127 // XXX check retval
128
129 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
130 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
131 if (retval != ERROR_OK)
132 return retval;
133 retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
134 // XXX check retval
135
136 retval = dap_run(swjdp);
137
138 /* restore DCB_DCRDR - this needs to be in a seperate
139 * transaction otherwise the emulated DCC channel breaks */
140 if (retval == ERROR_OK)
141 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
142
143 return retval;
144 }
145
146 static int cortex_m3_write_debug_halt_mask(struct target *target,
147 uint32_t mask_on, uint32_t mask_off)
148 {
149 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
150 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
151
152 /* mask off status bits */
153 cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
154 /* create new register mask */
155 cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
156
157 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
158 }
159
160 static int cortex_m3_clear_halt(struct target *target)
161 {
162 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
163 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
164 int retval;
165
166 /* clear step if any */
167 cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
168
169 /* Read Debug Fault Status Register */
170 retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
171 if (retval != ERROR_OK)
172 return retval;
173
174 /* Clear Debug Fault Status */
175 retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
176 if (retval != ERROR_OK)
177 return retval;
178 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
179
180 return ERROR_OK;
181 }
182
183 static int cortex_m3_single_step_core(struct target *target)
184 {
185 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
186 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
187 uint32_t dhcsr_save;
188 int retval;
189
190 /* backup dhcsr reg */
191 dhcsr_save = cortex_m3->dcb_dhcsr;
192
193 /* Mask interrupts before clearing halt, if done already. This avoids
194 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
195 * HALT can put the core into an unknown state.
196 */
197 if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
198 {
199 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
200 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
201 if (retval != ERROR_OK)
202 return retval;
203 }
204 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
205 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
206 if (retval != ERROR_OK)
207 return retval;
208 LOG_DEBUG(" ");
209
210 /* restore dhcsr reg */
211 cortex_m3->dcb_dhcsr = dhcsr_save;
212 cortex_m3_clear_halt(target);
213
214 return ERROR_OK;
215 }
216
217 static int cortex_m3_endreset_event(struct target *target)
218 {
219 int i;
220 int retval;
221 uint32_t dcb_demcr;
222 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
223 struct armv7m_common *armv7m = &cortex_m3->armv7m;
224 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
225 struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
226 struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
227
228 /* REVISIT The four debug monitor bits are currently ignored... */
229 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
230 if (retval != ERROR_OK)
231 return retval;
232 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
233
234 /* this register is used for emulated dcc channel */
235 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
236 if (retval != ERROR_OK)
237 return retval;
238
239 /* Enable debug requests */
240 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
241 if (retval != ERROR_OK)
242 return retval;
243 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
244 {
245 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
246 if (retval != ERROR_OK)
247 return retval;
248 }
249
250 /* clear any interrupt masking */
251 cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
252
253 /* Enable features controlled by ITM and DWT blocks, and catch only
254 * the vectors we were told to pay attention to.
255 *
256 * Target firmware is responsible for all fault handling policy
257 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
258 * or manual updates to the NVIC SHCSR and CCR registers.
259 */
260 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
261 if (retval != ERROR_OK)
262 return retval;
263
264 /* Paranoia: evidently some (early?) chips don't preserve all the
265 * debug state (including FBP, DWT, etc) across reset...
266 */
267
268 /* Enable FPB */
269 retval = target_write_u32(target, FP_CTRL, 3);
270 if (retval != ERROR_OK)
271 return retval;
272
273 cortex_m3->fpb_enabled = 1;
274
275 /* Restore FPB registers */
276 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
277 {
278 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
279 if (retval != ERROR_OK)
280 return retval;
281 }
282
283 /* Restore DWT registers */
284 for (i = 0; i < cortex_m3->dwt_num_comp; i++)
285 {
286 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
287 dwt_list[i].comp);
288 if (retval != ERROR_OK)
289 return retval;
290 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
291 dwt_list[i].mask);
292 if (retval != ERROR_OK)
293 return retval;
294 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
295 dwt_list[i].function);
296 if (retval != ERROR_OK)
297 return retval;
298 }
299 retval = dap_run(swjdp);
300 if (retval != ERROR_OK)
301 return retval;
302
303 register_cache_invalidate(cortex_m3->armv7m.core_cache);
304
305 /* make sure we have latest dhcsr flags */
306 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
307
308 return retval;
309 }
310
311 static int cortex_m3_examine_debug_reason(struct target *target)
312 {
313 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
314
315 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
316 /* only check the debug reason if we don't know it already */
317
318 if ((target->debug_reason != DBG_REASON_DBGRQ)
319 && (target->debug_reason != DBG_REASON_SINGLESTEP))
320 {
321 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
322 {
323 target->debug_reason = DBG_REASON_BREAKPOINT;
324 if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
325 target->debug_reason = DBG_REASON_WPTANDBKPT;
326 }
327 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
328 target->debug_reason = DBG_REASON_WATCHPOINT;
329 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
330 target->debug_reason = DBG_REASON_BREAKPOINT;
331 else /* EXTERNAL, HALTED */
332 target->debug_reason = DBG_REASON_UNDEFINED;
333 }
334
335 return ERROR_OK;
336 }
337
338 static int cortex_m3_examine_exception_reason(struct target *target)
339 {
340 uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
341 struct armv7m_common *armv7m = target_to_armv7m(target);
342 struct adiv5_dap *swjdp = &armv7m->dap;
343 int retval;
344
345 retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
346 if (retval != ERROR_OK)
347 return retval;
348 switch (armv7m->exception_number)
349 {
350 case 2: /* NMI */
351 break;
352 case 3: /* Hard Fault */
353 retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
354 if (retval != ERROR_OK)
355 return retval;
356 if (except_sr & 0x40000000)
357 {
358 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
359 if (retval != ERROR_OK)
360 return retval;
361 }
362 break;
363 case 4: /* Memory Management */
364 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
365 if (retval != ERROR_OK)
366 return retval;
367 retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
368 if (retval != ERROR_OK)
369 return retval;
370 break;
371 case 5: /* Bus Fault */
372 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
373 if (retval != ERROR_OK)
374 return retval;
375 retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
376 if (retval != ERROR_OK)
377 return retval;
378 break;
379 case 6: /* Usage Fault */
380 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
381 if (retval != ERROR_OK)
382 return retval;
383 break;
384 case 11: /* SVCall */
385 break;
386 case 12: /* Debug Monitor */
387 retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
388 if (retval != ERROR_OK)
389 return retval;
390 break;
391 case 14: /* PendSV */
392 break;
393 case 15: /* SysTick */
394 break;
395 default:
396 except_sr = 0;
397 break;
398 }
399 retval = dap_run(swjdp);
400 if (retval == ERROR_OK)
401 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
402 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
403 armv7m_exception_string(armv7m->exception_number),
404 shcsr, except_sr, cfsr, except_ar);
405 return retval;
406 }
407
408 /* PSP is used in some thread modes */
409 static const int armv7m_psp_reg_map[17] = {
410 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
411 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
412 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
413 ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
414 ARMV7M_xPSR,
415 };
416
417 /* MSP is used in handler and some thread modes */
418 static const int armv7m_msp_reg_map[17] = {
419 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
420 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
421 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
422 ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
423 ARMV7M_xPSR,
424 };
425
426 static int cortex_m3_debug_entry(struct target *target)
427 {
428 int i;
429 uint32_t xPSR;
430 int retval;
431 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
432 struct armv7m_common *armv7m = &cortex_m3->armv7m;
433 struct arm *arm = &armv7m->arm;
434 struct adiv5_dap *swjdp = &armv7m->dap;
435 struct reg *r;
436
437 LOG_DEBUG(" ");
438
439 cortex_m3_clear_halt(target);
440 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
441 if (retval != ERROR_OK)
442 return retval;
443
444 if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
445 return retval;
446
447 /* Examine target state and mode */
448 /* First load register acessible through core debug port*/
449 int num_regs = armv7m->core_cache->num_regs;
450
451 for (i = 0; i < num_regs; i++)
452 {
453 if (!armv7m->core_cache->reg_list[i].valid)
454 armv7m->read_core_reg(target, i);
455 }
456
457 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
458 xPSR = buf_get_u32(r->value, 0, 32);
459
460 #ifdef ARMV7_GDB_HACKS
461 /* FIXME this breaks on scan chains with more than one Cortex-M3.
462 * Instead, each CM3 should have its own dummy value...
463 */
464 /* copy real xpsr reg for gdb, setting thumb bit */
465 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
466 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
467 armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
468 armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
469 #endif
470
471 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
472 if (xPSR & 0xf00)
473 {
474 r->dirty = r->valid;
475 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
476 }
477
478 /* Are we in an exception handler */
479 if (xPSR & 0x1FF)
480 {
481 armv7m->core_mode = ARMV7M_MODE_HANDLER;
482 armv7m->exception_number = (xPSR & 0x1FF);
483
484 arm->core_mode = ARM_MODE_HANDLER;
485 arm->map = armv7m_msp_reg_map;
486 }
487 else
488 {
489 unsigned control = buf_get_u32(armv7m->core_cache
490 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
491
492 /* is this thread privileged? */
493 armv7m->core_mode = control & 1;
494 arm->core_mode = armv7m->core_mode
495 ? ARM_MODE_USER_THREAD
496 : ARM_MODE_THREAD;
497
498 /* which stack is it using? */
499 if (control & 2)
500 arm->map = armv7m_psp_reg_map;
501 else
502 arm->map = armv7m_msp_reg_map;
503
504 armv7m->exception_number = 0;
505 }
506
507 if (armv7m->exception_number)
508 {
509 cortex_m3_examine_exception_reason(target);
510 }
511
512 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
513 armv7m_mode_strings[armv7m->core_mode],
514 *(uint32_t*)(arm->pc->value),
515 target_state_name(target));
516
517 if (armv7m->post_debug_entry)
518 {
519 retval = armv7m->post_debug_entry(target);
520 if (retval != ERROR_OK)
521 return retval;
522 }
523
524 return ERROR_OK;
525 }
526
527 static int cortex_m3_poll(struct target *target)
528 {
529 int detected_failure = ERROR_OK;
530 int retval = ERROR_OK;
531 enum target_state prev_target_state = target->state;
532 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
533 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
534
535 /* Read from Debug Halting Control and Status Register */
536 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
537 if (retval != ERROR_OK)
538 {
539 target->state = TARGET_UNKNOWN;
540 return retval;
541 }
542
543 /* Recover from lockup. See ARMv7-M architecture spec,
544 * section B1.5.15 "Unrecoverable exception cases".
545 */
546 if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
547 LOG_ERROR("%s -- clearing lockup after double fault",
548 target_name(target));
549 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
550 target->debug_reason = DBG_REASON_DBGRQ;
551
552 /* We have to execute the rest (the "finally" equivalent, but
553 * still throw this exception again).
554 */
555 detected_failure = ERROR_FAIL;
556
557 /* refresh status bits */
558 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
559 if (retval != ERROR_OK)
560 return retval;
561 }
562
563 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
564 {
565 /* check if still in reset */
566 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
567 if (retval != ERROR_OK)
568 return retval;
569
570 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
571 {
572 target->state = TARGET_RESET;
573 return ERROR_OK;
574 }
575 }
576
577 if (target->state == TARGET_RESET)
578 {
579 /* Cannot switch context while running so endreset is
580 * called with target->state == TARGET_RESET
581 */
582 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
583 cortex_m3->dcb_dhcsr);
584 cortex_m3_endreset_event(target);
585 target->state = TARGET_RUNNING;
586 prev_target_state = TARGET_RUNNING;
587 }
588
589 if (cortex_m3->dcb_dhcsr & S_HALT)
590 {
591 target->state = TARGET_HALTED;
592
593 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
594 {
595 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
596 return retval;
597
598 if (arm_semihosting(target, &retval) != 0)
599 return retval;
600
601 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
602 }
603 if (prev_target_state == TARGET_DEBUG_RUNNING)
604 {
605 LOG_DEBUG(" ");
606 if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
607 return retval;
608
609 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
610 }
611 }
612
613 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
614 * How best to model low power modes?
615 */
616
617 if (target->state == TARGET_UNKNOWN)
618 {
619 /* check if processor is retiring instructions */
620 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
621 {
622 target->state = TARGET_RUNNING;
623 retval = ERROR_OK;
624 }
625 }
626
627 /* Did we detect a failure condition that we cleared? */
628 if (detected_failure != ERROR_OK)
629 retval = detected_failure;
630 return retval;
631 }
632
633 static int cortex_m3_halt(struct target *target)
634 {
635 LOG_DEBUG("target->state: %s",
636 target_state_name(target));
637
638 if (target->state == TARGET_HALTED)
639 {
640 LOG_DEBUG("target was already halted");
641 return ERROR_OK;
642 }
643
644 if (target->state == TARGET_UNKNOWN)
645 {
646 LOG_WARNING("target was in unknown state when halt was requested");
647 }
648
649 if (target->state == TARGET_RESET)
650 {
651 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
652 {
653 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
654 return ERROR_TARGET_FAILURE;
655 }
656 else
657 {
658 /* we came here in a reset_halt or reset_init sequence
659 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
660 */
661 target->debug_reason = DBG_REASON_DBGRQ;
662
663 return ERROR_OK;
664 }
665 }
666
667 /* Write to Debug Halting Control and Status Register */
668 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
669
670 target->debug_reason = DBG_REASON_DBGRQ;
671
672 return ERROR_OK;
673 }
674
675 static int cortex_m3_soft_reset_halt(struct target *target)
676 {
677 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
678 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
679 uint32_t dcb_dhcsr = 0;
680 int retval, timeout = 0;
681
682 /* Enter debug state on reset; restore DEMCR in endreset_event() */
683 retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
684 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
685 if (retval != ERROR_OK)
686 return retval;
687
688 /* Request a core-only reset */
689 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
690 AIRCR_VECTKEY | AIRCR_VECTRESET);
691 if (retval != ERROR_OK)
692 return retval;
693 target->state = TARGET_RESET;
694
695 /* registers are now invalid */
696 register_cache_invalidate(cortex_m3->armv7m.core_cache);
697
698 while (timeout < 100)
699 {
700 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
701 if (retval == ERROR_OK)
702 {
703 retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
704 &cortex_m3->nvic_dfsr);
705 if (retval != ERROR_OK)
706 return retval;
707 if ((dcb_dhcsr & S_HALT)
708 && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
709 {
710 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
711 "DFSR 0x%08x",
712 (unsigned) dcb_dhcsr,
713 (unsigned) cortex_m3->nvic_dfsr);
714 cortex_m3_poll(target);
715 /* FIXME restore user's vector catch config */
716 return ERROR_OK;
717 }
718 else
719 LOG_DEBUG("waiting for system reset-halt, "
720 "DHCSR 0x%08x, %d ms",
721 (unsigned) dcb_dhcsr, timeout);
722 }
723 timeout++;
724 alive_sleep(1);
725 }
726
727 return ERROR_OK;
728 }
729
730 static void cortex_m3_enable_breakpoints(struct target *target)
731 {
732 struct breakpoint *breakpoint = target->breakpoints;
733
734 /* set any pending breakpoints */
735 while (breakpoint)
736 {
737 if (!breakpoint->set)
738 cortex_m3_set_breakpoint(target, breakpoint);
739 breakpoint = breakpoint->next;
740 }
741 }
742
743 static int cortex_m3_resume(struct target *target, int current,
744 uint32_t address, int handle_breakpoints, int debug_execution)
745 {
746 struct armv7m_common *armv7m = target_to_armv7m(target);
747 struct breakpoint *breakpoint = NULL;
748 uint32_t resume_pc;
749 struct reg *r;
750
751 if (target->state != TARGET_HALTED)
752 {
753 LOG_WARNING("target not halted");
754 return ERROR_TARGET_NOT_HALTED;
755 }
756
757 if (!debug_execution)
758 {
759 target_free_all_working_areas(target);
760 cortex_m3_enable_breakpoints(target);
761 cortex_m3_enable_watchpoints(target);
762 }
763
764 if (debug_execution)
765 {
766 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
767
768 /* Disable interrupts */
769 /* We disable interrupts in the PRIMASK register instead of
770 * masking with C_MASKINTS. This is probably the same issue
771 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
772 * in parallel with disabled interrupts can cause local faults
773 * to not be taken.
774 *
775 * REVISIT this clearly breaks non-debug execution, since the
776 * PRIMASK register state isn't saved/restored... workaround
777 * by never resuming app code after debug execution.
778 */
779 buf_set_u32(r->value, 0, 1, 1);
780 r->dirty = true;
781 r->valid = true;
782
783 /* Make sure we are in Thumb mode */
784 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
785 buf_set_u32(r->value, 24, 1, 1);
786 r->dirty = true;
787 r->valid = true;
788 }
789
790 /* current = 1: continue on current pc, otherwise continue at <address> */
791 r = armv7m->arm.pc;
792 if (!current)
793 {
794 buf_set_u32(r->value, 0, 32, address);
795 r->dirty = true;
796 r->valid = true;
797 }
798
799 /* if we halted last time due to a bkpt instruction
800 * then we have to manually step over it, otherwise
801 * the core will break again */
802
803 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
804 && !debug_execution)
805 {
806 armv7m_maybe_skip_bkpt_inst(target, NULL);
807 }
808
809 resume_pc = buf_get_u32(r->value, 0, 32);
810
811 armv7m_restore_context(target);
812
813 /* the front-end may request us not to handle breakpoints */
814 if (handle_breakpoints)
815 {
816 /* Single step past breakpoint at current address */
817 if ((breakpoint = breakpoint_find(target, resume_pc)))
818 {
819 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
820 breakpoint->address,
821 breakpoint->unique_id);
822 cortex_m3_unset_breakpoint(target, breakpoint);
823 cortex_m3_single_step_core(target);
824 cortex_m3_set_breakpoint(target, breakpoint);
825 }
826 }
827
828 /* Restart core */
829 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
830
831 target->debug_reason = DBG_REASON_NOTHALTED;
832
833 /* registers are now invalid */
834 register_cache_invalidate(armv7m->core_cache);
835
836 if (!debug_execution)
837 {
838 target->state = TARGET_RUNNING;
839 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
840 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
841 }
842 else
843 {
844 target->state = TARGET_DEBUG_RUNNING;
845 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
846 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
847 }
848
849 return ERROR_OK;
850 }
851
852 /* int irqstepcount = 0; */
853 static int cortex_m3_step(struct target *target, int current,
854 uint32_t address, int handle_breakpoints)
855 {
856 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
857 struct armv7m_common *armv7m = &cortex_m3->armv7m;
858 struct adiv5_dap *swjdp = &armv7m->dap;
859 struct breakpoint *breakpoint = NULL;
860 struct reg *pc = armv7m->arm.pc;
861 bool bkpt_inst_found = false;
862 int retval;
863 bool isr_timed_out = false;
864
865 if (target->state != TARGET_HALTED)
866 {
867 LOG_WARNING("target not halted");
868 return ERROR_TARGET_NOT_HALTED;
869 }
870
871 /* current = 1: continue on current pc, otherwise continue at <address> */
872 if (!current)
873 buf_set_u32(pc->value, 0, 32, address);
874
875 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
876
877 /* the front-end may request us not to handle breakpoints */
878 if (handle_breakpoints) {
879 breakpoint = breakpoint_find(target, pc_value);
880 if (breakpoint)
881 cortex_m3_unset_breakpoint(target, breakpoint);
882 }
883
884 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
885
886 target->debug_reason = DBG_REASON_SINGLESTEP;
887
888 armv7m_restore_context(target);
889
890 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
891
892 /* if no bkpt instruction is found at pc then we can perform
893 * a normal step, otherwise we have to manually step over the bkpt
894 * instruction - as such simulate a step */
895 if (bkpt_inst_found == false)
896 {
897 /* Automatic ISR masking mode off: Just step over the next instruction */
898 if ((cortex_m3->isrmasking_mode != CORTEX_M3_ISRMASK_AUTO))
899 {
900 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
901 }
902 else
903 {
904 /* Process interrupts during stepping in a way they don't interfere
905 * debugging.
906 *
907 * Principle:
908 *
909 * Set a temporary break point at the current pc and let the core run
910 * with interrupts enabled. Pending interrupts get served and we run
911 * into the breakpoint again afterwards. Then we step over the next
912 * instruction with interrupts disabled.
913 *
914 * If the pending interrupts don't complete within time, we leave the
915 * core running. This may happen if the interrupts trigger faster
916 * than the core can process them or the handler doesn't return.
917 *
918 * If no more breakpoints are available we simply do a step with
919 * interrupts enabled.
920 *
921 */
922
923 /* Set a temporary break point */
924 retval = breakpoint_add(target, pc_value , 2, BKPT_TYPE_BY_ADDR(pc_value));
925 bool tmp_bp_set = (retval == ERROR_OK);
926
927 /* No more breakpoints left, just do a step */
928 if (!tmp_bp_set)
929 {
930 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
931 }
932 else
933 {
934 /* Start the core */
935 LOG_DEBUG("Starting core to serve pending interrupts");
936 int64_t t_start = timeval_ms();
937 cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
938
939 /* Wait for pending handlers to complete or timeout */
940 do {
941 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
942 if (retval != ERROR_OK)
943 {
944 target->state = TARGET_UNKNOWN;
945 return retval;
946 }
947 isr_timed_out = ((timeval_ms() - t_start) > 500);
948 } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out));
949
950 /* Remove the temporary breakpoint */
951 breakpoint_remove(target, pc_value);
952
953 if (isr_timed_out)
954 {
955 LOG_DEBUG("Interrupt handlers didn't complete within time, "
956 "leaving target running");
957 }
958 else
959 {
960 /* Step over next instruction with interrupts disabled */
961 cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
962 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
963 /* Re-enable interrupts */
964 cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
965 }
966 }
967 }
968 }
969
970 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
971 if (retval != ERROR_OK)
972 return retval;
973
974 /* registers are now invalid */
975 register_cache_invalidate(cortex_m3->armv7m.core_cache);
976
977 if (breakpoint)
978 cortex_m3_set_breakpoint(target, breakpoint);
979
980 if (isr_timed_out) {
981 /* Leave the core running. The user has to stop execution manually. */
982 target->debug_reason = DBG_REASON_NOTHALTED;
983 target->state = TARGET_RUNNING;
984 return ERROR_OK;
985 }
986
987 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
988 " nvic_icsr = 0x%" PRIx32,
989 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
990
991 retval = cortex_m3_debug_entry(target);
992 if (retval != ERROR_OK)
993 return retval;
994 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
995
996 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
997 " nvic_icsr = 0x%" PRIx32,
998 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
999
1000 return ERROR_OK;
1001 }
1002
1003 static int cortex_m3_assert_reset(struct target *target)
1004 {
1005 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1006 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
1007 enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
1008
1009 LOG_DEBUG("target->state: %s",
1010 target_state_name(target));
1011
1012 enum reset_types jtag_reset_config = jtag_get_reset_config();
1013
1014 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1015 /* allow scripts to override the reset event */
1016
1017 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1018 register_cache_invalidate(cortex_m3->armv7m.core_cache);
1019 target->state = TARGET_RESET;
1020
1021 return ERROR_OK;
1022 }
1023
1024 /* Enable debug requests */
1025 int retval;
1026 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
1027 if (retval != ERROR_OK)
1028 return retval;
1029 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
1030 {
1031 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
1032 if (retval != ERROR_OK)
1033 return retval;
1034 }
1035
1036 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
1037 if (retval != ERROR_OK)
1038 return retval;
1039
1040 if (!target->reset_halt)
1041 {
1042 /* Set/Clear C_MASKINTS in a separate operation */
1043 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
1044 {
1045 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
1046 DBGKEY | C_DEBUGEN | C_HALT);
1047 if (retval != ERROR_OK)
1048 return retval;
1049 }
1050
1051 /* clear any debug flags before resuming */
1052 cortex_m3_clear_halt(target);
1053
1054 /* clear C_HALT in dhcsr reg */
1055 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
1056 }
1057 else
1058 {
1059 /* Halt in debug on reset; endreset_event() restores DEMCR.
1060 *
1061 * REVISIT catching BUSERR presumably helps to defend against
1062 * bad vector table entries. Should this include MMERR or
1063 * other flags too?
1064 */
1065 retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
1066 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1067 if (retval != ERROR_OK)
1068 return retval;
1069 }
1070
1071 if (jtag_reset_config & RESET_HAS_SRST)
1072 {
1073 /* default to asserting srst */
1074 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1075 {
1076 jtag_add_reset(1, 1);
1077 }
1078 else
1079 {
1080 jtag_add_reset(0, 1);
1081 }
1082 }
1083 else
1084 {
1085 /* Use a standard Cortex-M3 software reset mechanism.
1086 * We default to using VECRESET as it is supported on all current cores.
1087 * This has the disadvantage of not resetting the peripherals, so a
1088 * reset-init event handler is needed to perform any peripheral resets.
1089 */
1090 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
1091 AIRCR_VECTKEY | ((reset_config == CORTEX_M3_RESET_SYSRESETREQ)
1092 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1093 if (retval != ERROR_OK)
1094 return retval;
1095
1096 LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
1097 ? "SYSRESETREQ" : "VECTRESET");
1098
1099 if (reset_config == CORTEX_M3_RESET_VECTRESET) {
1100 LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
1101 "handler to reset any peripherals");
1102 }
1103
1104 {
1105 /* I do not know why this is necessary, but it
1106 * fixes strange effects (step/resume cause NMI
1107 * after reset) on LM3S6918 -- Michael Schwingen
1108 */
1109 uint32_t tmp;
1110 retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
1111 if (retval != ERROR_OK)
1112 return retval;
1113 }
1114 }
1115
1116 target->state = TARGET_RESET;
1117 jtag_add_sleep(50000);
1118
1119 register_cache_invalidate(cortex_m3->armv7m.core_cache);
1120
1121 if (target->reset_halt)
1122 {
1123 if ((retval = target_halt(target)) != ERROR_OK)
1124 return retval;
1125 }
1126
1127 return ERROR_OK;
1128 }
1129
1130 static int cortex_m3_deassert_reset(struct target *target)
1131 {
1132 LOG_DEBUG("target->state: %s",
1133 target_state_name(target));
1134
1135 /* deassert reset lines */
1136 jtag_add_reset(0, 0);
1137
1138 return ERROR_OK;
1139 }
1140
1141 static int
1142 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1143 {
1144 int retval;
1145 int fp_num = 0;
1146 uint32_t hilo;
1147 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1148 struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
1149
1150 if (breakpoint->set)
1151 {
1152 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
1153 return ERROR_OK;
1154 }
1155
1156 if (cortex_m3->auto_bp_type)
1157 {
1158 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1159 }
1160
1161 if (breakpoint->type == BKPT_HARD)
1162 {
1163 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
1164 fp_num++;
1165 if (fp_num >= cortex_m3->fp_num_code)
1166 {
1167 LOG_ERROR("Can not find free FPB Comparator!");
1168 return ERROR_FAIL;
1169 }
1170 breakpoint->set = fp_num + 1;
1171 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1172 comparator_list[fp_num].used = 1;
1173 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1174 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1175 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
1176 if (!cortex_m3->fpb_enabled)
1177 {
1178 LOG_DEBUG("FPB wasn't enabled, do it now");
1179 target_write_u32(target, FP_CTRL, 3);
1180 }
1181 }
1182 else if (breakpoint->type == BKPT_SOFT)
1183 {
1184 uint8_t code[4];
1185
1186 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1187 * semihosting; don't use that. Otherwise the BKPT
1188 * parameter is arbitrary.
1189 */
1190 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1191 retval = target_read_memory(target,
1192 breakpoint->address & 0xFFFFFFFE,
1193 breakpoint->length, 1,
1194 breakpoint->orig_instr);
1195 if (retval != ERROR_OK)
1196 return retval;
1197 retval = target_write_memory(target,
1198 breakpoint->address & 0xFFFFFFFE,
1199 breakpoint->length, 1,
1200 code);
1201 if (retval != ERROR_OK)
1202 return retval;
1203 breakpoint->set = true;
1204 }
1205
1206 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1207 breakpoint->unique_id,
1208 (int)(breakpoint->type),
1209 breakpoint->address,
1210 breakpoint->length,
1211 breakpoint->set);
1212
1213 return ERROR_OK;
1214 }
1215
1216 static int
1217 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1218 {
1219 int retval;
1220 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1221 struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
1222
1223 if (!breakpoint->set)
1224 {
1225 LOG_WARNING("breakpoint not set");
1226 return ERROR_OK;
1227 }
1228
1229 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1230 breakpoint->unique_id,
1231 (int)(breakpoint->type),
1232 breakpoint->address,
1233 breakpoint->length,
1234 breakpoint->set);
1235
1236 if (breakpoint->type == BKPT_HARD)
1237 {
1238 int fp_num = breakpoint->set - 1;
1239 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
1240 {
1241 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1242 return ERROR_OK;
1243 }
1244 comparator_list[fp_num].used = 0;
1245 comparator_list[fp_num].fpcr_value = 0;
1246 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1247 }
1248 else
1249 {
1250 /* restore original instruction (kept in target endianness) */
1251 if (breakpoint->length == 4)
1252 {
1253 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1254 {
1255 return retval;
1256 }
1257 }
1258 else
1259 {
1260 if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1261 {
1262 return retval;
1263 }
1264 }
1265 }
1266 breakpoint->set = false;
1267
1268 return ERROR_OK;
1269 }
1270
1271 static int
1272 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1273 {
1274 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1275
1276 if (cortex_m3->auto_bp_type)
1277 {
1278 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1279 #ifdef ARMV7_GDB_HACKS
1280 if (breakpoint->length != 2) {
1281 /* XXX Hack: Replace all breakpoints with length != 2 with
1282 * a hardware breakpoint. */
1283 breakpoint->type = BKPT_HARD;
1284 breakpoint->length = 2;
1285 }
1286 #endif
1287 }
1288
1289 if(breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
1290 if (breakpoint->type == BKPT_HARD)
1291 {
1292 LOG_INFO("flash patch comparator requested outside code memory region");
1293 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1294 }
1295
1296 if (breakpoint->type == BKPT_SOFT)
1297 {
1298 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1299 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1300 }
1301 }
1302
1303 if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1304 {
1305 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1306 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1307 }
1308
1309 if ((breakpoint->length != 2))
1310 {
1311 LOG_INFO("only breakpoints of two bytes length supported");
1312 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1313 }
1314
1315 if (breakpoint->type == BKPT_HARD)
1316 cortex_m3->fp_code_available--;
1317
1318 return cortex_m3_set_breakpoint(target, breakpoint);
1319 }
1320
1321 static int
1322 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1323 {
1324 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1325
1326 /* REVISIT why check? FBP can be updated with core running ... */
1327 if (target->state != TARGET_HALTED)
1328 {
1329 LOG_WARNING("target not halted");
1330 return ERROR_TARGET_NOT_HALTED;
1331 }
1332
1333 if (cortex_m3->auto_bp_type)
1334 {
1335 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1336 }
1337
1338 if (breakpoint->set)
1339 {
1340 cortex_m3_unset_breakpoint(target, breakpoint);
1341 }
1342
1343 if (breakpoint->type == BKPT_HARD)
1344 cortex_m3->fp_code_available++;
1345
1346 return ERROR_OK;
1347 }
1348
1349 static int
1350 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1351 {
1352 int dwt_num = 0;
1353 uint32_t mask, temp;
1354 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1355
1356 /* watchpoint params were validated earlier */
1357 mask = 0;
1358 temp = watchpoint->length;
1359 while (temp) {
1360 temp >>= 1;
1361 mask++;
1362 }
1363 mask--;
1364
1365 /* REVISIT Don't fully trust these "not used" records ... users
1366 * may set up breakpoints by hand, e.g. dual-address data value
1367 * watchpoint using comparator #1; comparator #0 matching cycle
1368 * count; send data trace info through ITM and TPIU; etc
1369 */
1370 struct cortex_m3_dwt_comparator *comparator;
1371
1372 for (comparator = cortex_m3->dwt_comparator_list;
1373 comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1374 comparator++, dwt_num++)
1375 continue;
1376 if (dwt_num >= cortex_m3->dwt_num_comp)
1377 {
1378 LOG_ERROR("Can not find free DWT Comparator");
1379 return ERROR_FAIL;
1380 }
1381 comparator->used = 1;
1382 watchpoint->set = dwt_num + 1;
1383
1384 comparator->comp = watchpoint->address;
1385 target_write_u32(target, comparator->dwt_comparator_address + 0,
1386 comparator->comp);
1387
1388 comparator->mask = mask;
1389 target_write_u32(target, comparator->dwt_comparator_address + 4,
1390 comparator->mask);
1391
1392 switch (watchpoint->rw) {
1393 case WPT_READ:
1394 comparator->function = 5;
1395 break;
1396 case WPT_WRITE:
1397 comparator->function = 6;
1398 break;
1399 case WPT_ACCESS:
1400 comparator->function = 7;
1401 break;
1402 }
1403 target_write_u32(target, comparator->dwt_comparator_address + 8,
1404 comparator->function);
1405
1406 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1407 watchpoint->unique_id, dwt_num,
1408 (unsigned) comparator->comp,
1409 (unsigned) comparator->mask,
1410 (unsigned) comparator->function);
1411 return ERROR_OK;
1412 }
1413
1414 static int
1415 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1416 {
1417 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1418 struct cortex_m3_dwt_comparator *comparator;
1419 int dwt_num;
1420
1421 if (!watchpoint->set)
1422 {
1423 LOG_WARNING("watchpoint (wpid: %d) not set",
1424 watchpoint->unique_id);
1425 return ERROR_OK;
1426 }
1427
1428 dwt_num = watchpoint->set - 1;
1429
1430 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1431 watchpoint->unique_id, dwt_num,
1432 (unsigned) watchpoint->address);
1433
1434 if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1435 {
1436 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1437 return ERROR_OK;
1438 }
1439
1440 comparator = cortex_m3->dwt_comparator_list + dwt_num;
1441 comparator->used = 0;
1442 comparator->function = 0;
1443 target_write_u32(target, comparator->dwt_comparator_address + 8,
1444 comparator->function);
1445
1446 watchpoint->set = false;
1447
1448 return ERROR_OK;
1449 }
1450
1451 static int
1452 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1453 {
1454 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1455
1456 if (cortex_m3->dwt_comp_available < 1)
1457 {
1458 LOG_DEBUG("no comparators?");
1459 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1460 }
1461
1462 /* hardware doesn't support data value masking */
1463 if (watchpoint->mask != ~(uint32_t)0) {
1464 LOG_DEBUG("watchpoint value masks not supported");
1465 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1466 }
1467
1468 /* hardware allows address masks of up to 32K */
1469 unsigned mask;
1470
1471 for (mask = 0; mask < 16; mask++) {
1472 if ((1u << mask) == watchpoint->length)
1473 break;
1474 }
1475 if (mask == 16) {
1476 LOG_DEBUG("unsupported watchpoint length");
1477 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1478 }
1479 if (watchpoint->address & ((1 << mask) - 1)) {
1480 LOG_DEBUG("watchpoint address is unaligned");
1481 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1482 }
1483
1484 /* Caller doesn't seem to be able to describe watching for data
1485 * values of zero; that flags "no value".
1486 *
1487 * REVISIT This DWT may well be able to watch for specific data
1488 * values. Requires comparator #1 to set DATAVMATCH and match
1489 * the data, and another comparator (DATAVADDR0) matching addr.
1490 */
1491 if (watchpoint->value) {
1492 LOG_DEBUG("data value watchpoint not YET supported");
1493 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1494 }
1495
1496 cortex_m3->dwt_comp_available--;
1497 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1498
1499 return ERROR_OK;
1500 }
1501
1502 static int
1503 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1504 {
1505 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1506
1507 /* REVISIT why check? DWT can be updated with core running ... */
1508 if (target->state != TARGET_HALTED)
1509 {
1510 LOG_WARNING("target not halted");
1511 return ERROR_TARGET_NOT_HALTED;
1512 }
1513
1514 if (watchpoint->set)
1515 {
1516 cortex_m3_unset_watchpoint(target, watchpoint);
1517 }
1518
1519 cortex_m3->dwt_comp_available++;
1520 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1521
1522 return ERROR_OK;
1523 }
1524
1525 static void cortex_m3_enable_watchpoints(struct target *target)
1526 {
1527 struct watchpoint *watchpoint = target->watchpoints;
1528
1529 /* set any pending watchpoints */
1530 while (watchpoint)
1531 {
1532 if (!watchpoint->set)
1533 cortex_m3_set_watchpoint(target, watchpoint);
1534 watchpoint = watchpoint->next;
1535 }
1536 }
1537
1538 static int cortex_m3_load_core_reg_u32(struct target *target,
1539 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1540 {
1541 int retval;
1542 struct armv7m_common *armv7m = target_to_armv7m(target);
1543 struct adiv5_dap *swjdp = &armv7m->dap;
1544
1545 /* NOTE: we "know" here that the register identifiers used
1546 * in the v7m header match the Cortex-M3 Debug Core Register
1547 * Selector values for R0..R15, xPSR, MSP, and PSP.
1548 */
1549 switch (num) {
1550 case 0 ... 18:
1551 /* read a normal core register */
1552 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1553
1554 if (retval != ERROR_OK)
1555 {
1556 LOG_ERROR("JTAG failure %i",retval);
1557 return ERROR_JTAG_DEVICE_ERROR;
1558 }
1559 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
1560 break;
1561
1562 case ARMV7M_PRIMASK:
1563 case ARMV7M_BASEPRI:
1564 case ARMV7M_FAULTMASK:
1565 case ARMV7M_CONTROL:
1566 /* Cortex-M3 packages these four registers as bitfields
1567 * in one Debug Core register. So say r0 and r2 docs;
1568 * it was removed from r1 docs, but still works.
1569 */
1570 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1571
1572 switch (num)
1573 {
1574 case ARMV7M_PRIMASK:
1575 *value = buf_get_u32((uint8_t*)value, 0, 1);
1576 break;
1577
1578 case ARMV7M_BASEPRI:
1579 *value = buf_get_u32((uint8_t*)value, 8, 8);
1580 break;
1581
1582 case ARMV7M_FAULTMASK:
1583 *value = buf_get_u32((uint8_t*)value, 16, 1);
1584 break;
1585
1586 case ARMV7M_CONTROL:
1587 *value = buf_get_u32((uint8_t*)value, 24, 2);
1588 break;
1589 }
1590
1591 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1592 break;
1593
1594 default:
1595 return ERROR_INVALID_ARGUMENTS;
1596 }
1597
1598 return ERROR_OK;
1599 }
1600
1601 static int cortex_m3_store_core_reg_u32(struct target *target,
1602 enum armv7m_regtype type, uint32_t num, uint32_t value)
1603 {
1604 int retval;
1605 uint32_t reg;
1606 struct armv7m_common *armv7m = target_to_armv7m(target);
1607 struct adiv5_dap *swjdp = &armv7m->dap;
1608
1609 #ifdef ARMV7_GDB_HACKS
1610 /* If the LR register is being modified, make sure it will put us
1611 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1612 * hack to deal with the fact that gdb will sometimes "forge"
1613 * return addresses, and doesn't set the LSB correctly (i.e., when
1614 * printing expressions containing function calls, it sets LR = 0.)
1615 * Valid exception return codes have bit 0 set too.
1616 */
1617 if (num == ARMV7M_R14)
1618 value |= 0x01;
1619 #endif
1620
1621 /* NOTE: we "know" here that the register identifiers used
1622 * in the v7m header match the Cortex-M3 Debug Core Register
1623 * Selector values for R0..R15, xPSR, MSP, and PSP.
1624 */
1625 switch (num) {
1626 case 0 ... 18:
1627 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1628 if (retval != ERROR_OK)
1629 {
1630 struct reg *r;
1631
1632 LOG_ERROR("JTAG failure");
1633 r = armv7m->core_cache->reg_list + num;
1634 r->dirty = r->valid;
1635 return ERROR_JTAG_DEVICE_ERROR;
1636 }
1637 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1638 break;
1639
1640 case ARMV7M_PRIMASK:
1641 case ARMV7M_BASEPRI:
1642 case ARMV7M_FAULTMASK:
1643 case ARMV7M_CONTROL:
1644 /* Cortex-M3 packages these four registers as bitfields
1645 * in one Debug Core register. So say r0 and r2 docs;
1646 * it was removed from r1 docs, but still works.
1647 */
1648 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1649
1650 switch (num)
1651 {
1652 case ARMV7M_PRIMASK:
1653 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1654 break;
1655
1656 case ARMV7M_BASEPRI:
1657 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1658 break;
1659
1660 case ARMV7M_FAULTMASK:
1661 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1662 break;
1663
1664 case ARMV7M_CONTROL:
1665 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1666 break;
1667 }
1668
1669 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1670
1671 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1672 break;
1673
1674 default:
1675 return ERROR_INVALID_ARGUMENTS;
1676 }
1677
1678 return ERROR_OK;
1679 }
1680
1681 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1682 uint32_t size, uint32_t count, uint8_t *buffer)
1683 {
1684 struct armv7m_common *armv7m = target_to_armv7m(target);
1685 struct adiv5_dap *swjdp = &armv7m->dap;
1686 int retval = ERROR_INVALID_ARGUMENTS;
1687
1688 /* cortex_m3 handles unaligned memory access */
1689 if (count && buffer) {
1690 switch (size) {
1691 case 4:
1692 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1693 break;
1694 case 2:
1695 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1696 break;
1697 case 1:
1698 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1699 break;
1700 }
1701 }
1702
1703 return retval;
1704 }
1705
1706 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1707 uint32_t size, uint32_t count, const uint8_t *buffer)
1708 {
1709 struct armv7m_common *armv7m = target_to_armv7m(target);
1710 struct adiv5_dap *swjdp = &armv7m->dap;
1711 int retval = ERROR_INVALID_ARGUMENTS;
1712
1713 if (count && buffer) {
1714 switch (size) {
1715 case 4:
1716 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1717 break;
1718 case 2:
1719 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1720 break;
1721 case 1:
1722 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1723 break;
1724 }
1725 }
1726
1727 return retval;
1728 }
1729
1730 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1731 uint32_t count, const uint8_t *buffer)
1732 {
1733 return cortex_m3_write_memory(target, address, 4, count, buffer);
1734 }
1735
1736 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1737 struct target *target)
1738 {
1739 armv7m_build_reg_cache(target);
1740 return ERROR_OK;
1741 }
1742
1743 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1744 * on r/w if the core is not running, and clear on resume or reset ... or
1745 * at least, in a post_restore_context() method.
1746 */
1747
1748 struct dwt_reg_state {
1749 struct target *target;
1750 uint32_t addr;
1751 uint32_t value; /* scratch/cache */
1752 };
1753
1754 static int cortex_m3_dwt_get_reg(struct reg *reg)
1755 {
1756 struct dwt_reg_state *state = reg->arch_info;
1757
1758 return target_read_u32(state->target, state->addr, &state->value);
1759 }
1760
1761 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1762 {
1763 struct dwt_reg_state *state = reg->arch_info;
1764
1765 return target_write_u32(state->target, state->addr,
1766 buf_get_u32(buf, 0, reg->size));
1767 }
1768
1769 struct dwt_reg {
1770 uint32_t addr;
1771 char *name;
1772 unsigned size;
1773 };
1774
1775 static struct dwt_reg dwt_base_regs[] = {
1776 { DWT_CTRL, "dwt_ctrl", 32, },
1777 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1778 * increments while the core is asleep.
1779 */
1780 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1781 /* plus some 8 bit counters, useful for profiling with TPIU */
1782 };
1783
1784 static struct dwt_reg dwt_comp[] = {
1785 #define DWT_COMPARATOR(i) \
1786 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1787 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1788 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1789 DWT_COMPARATOR(0),
1790 DWT_COMPARATOR(1),
1791 DWT_COMPARATOR(2),
1792 DWT_COMPARATOR(3),
1793 #undef DWT_COMPARATOR
1794 };
1795
1796 static const struct reg_arch_type dwt_reg_type = {
1797 .get = cortex_m3_dwt_get_reg,
1798 .set = cortex_m3_dwt_set_reg,
1799 };
1800
1801 static void
1802 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1803 {
1804 struct dwt_reg_state *state;
1805
1806 state = calloc(1, sizeof *state);
1807 if (!state)
1808 return;
1809 state->addr = d->addr;
1810 state->target = t;
1811
1812 r->name = d->name;
1813 r->size = d->size;
1814 r->value = &state->value;
1815 r->arch_info = state;
1816 r->type = &dwt_reg_type;
1817 }
1818
1819 static void
1820 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1821 {
1822 uint32_t dwtcr;
1823 struct reg_cache *cache;
1824 struct cortex_m3_dwt_comparator *comparator;
1825 int reg, i;
1826
1827 target_read_u32(target, DWT_CTRL, &dwtcr);
1828 if (!dwtcr) {
1829 LOG_DEBUG("no DWT");
1830 return;
1831 }
1832
1833 cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1834 cm3->dwt_comp_available = cm3->dwt_num_comp;
1835 cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1836 sizeof(struct cortex_m3_dwt_comparator));
1837 if (!cm3->dwt_comparator_list) {
1838 fail0:
1839 cm3->dwt_num_comp = 0;
1840 LOG_ERROR("out of mem");
1841 return;
1842 }
1843
1844 cache = calloc(1, sizeof *cache);
1845 if (!cache) {
1846 fail1:
1847 free(cm3->dwt_comparator_list);
1848 goto fail0;
1849 }
1850 cache->name = "cortex-m3 dwt registers";
1851 cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1852 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1853 if (!cache->reg_list) {
1854 free(cache);
1855 goto fail1;
1856 }
1857
1858 for (reg = 0; reg < 2; reg++)
1859 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1860 dwt_base_regs + reg);
1861
1862 comparator = cm3->dwt_comparator_list;
1863 for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1864 int j;
1865
1866 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1867 for (j = 0; j < 3; j++, reg++)
1868 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1869 dwt_comp + 3 * i + j);
1870 }
1871
1872 *register_get_last_cache_p(&target->reg_cache) = cache;
1873 cm3->dwt_cache = cache;
1874
1875 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1876 dwtcr, cm3->dwt_num_comp,
1877 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1878
1879 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1880 * implement single-address data value watchpoints ... so we
1881 * won't need to check it later, when asked to set one up.
1882 */
1883 }
1884
1885 static int cortex_m3_examine(struct target *target)
1886 {
1887 int retval;
1888 uint32_t cpuid, fpcr;
1889 int i;
1890 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1891 struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
1892
1893 if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1894 return retval;
1895
1896 if (!target_was_examined(target))
1897 {
1898 target_set_examined(target);
1899
1900 /* Read from Device Identification Registers */
1901 retval = target_read_u32(target, CPUID, &cpuid);
1902 if (retval != ERROR_OK)
1903 return retval;
1904
1905 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1906 LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
1907 (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1908 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1909
1910 /* NOTE: FPB and DWT are both optional. */
1911
1912 /* Setup FPB */
1913 target_read_u32(target, FP_CTRL, &fpcr);
1914 cortex_m3->auto_bp_type = 1;
1915 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1916 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1917 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1918 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1919 cortex_m3->fpb_enabled = fpcr & 1;
1920 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1921 {
1922 cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1923 cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1924 }
1925 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1926
1927 /* Setup DWT */
1928 cortex_m3_dwt_setup(cortex_m3, target);
1929
1930 /* These hardware breakpoints only work for code in flash! */
1931 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1932 target_name(target),
1933 cortex_m3->fp_num_code,
1934 cortex_m3->dwt_num_comp);
1935 }
1936
1937 return ERROR_OK;
1938 }
1939
1940 static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
1941 {
1942 uint16_t dcrdr;
1943 int retval;
1944
1945 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1946 *ctrl = (uint8_t)dcrdr;
1947 *value = (uint8_t)(dcrdr >> 8);
1948
1949 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1950
1951 /* write ack back to software dcc register
1952 * signify we have read data */
1953 if (dcrdr & (1 << 0))
1954 {
1955 dcrdr = 0;
1956 retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1957 if (retval != ERROR_OK)
1958 return retval;
1959 }
1960
1961 return ERROR_OK;
1962 }
1963
1964 static int cortex_m3_target_request_data(struct target *target,
1965 uint32_t size, uint8_t *buffer)
1966 {
1967 struct armv7m_common *armv7m = target_to_armv7m(target);
1968 struct adiv5_dap *swjdp = &armv7m->dap;
1969 uint8_t data;
1970 uint8_t ctrl;
1971 uint32_t i;
1972
1973 for (i = 0; i < (size * 4); i++)
1974 {
1975 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1976 buffer[i] = data;
1977 }
1978
1979 return ERROR_OK;
1980 }
1981
1982 static int cortex_m3_handle_target_request(void *priv)
1983 {
1984 struct target *target = priv;
1985 if (!target_was_examined(target))
1986 return ERROR_OK;
1987 struct armv7m_common *armv7m = target_to_armv7m(target);
1988 struct adiv5_dap *swjdp = &armv7m->dap;
1989
1990 if (!target->dbg_msg_enabled)
1991 return ERROR_OK;
1992
1993 if (target->state == TARGET_RUNNING)
1994 {
1995 uint8_t data;
1996 uint8_t ctrl;
1997
1998 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1999
2000 /* check if we have data */
2001 if (ctrl & (1 << 0))
2002 {
2003 uint32_t request;
2004
2005 /* we assume target is quick enough */
2006 request = data;
2007 cortex_m3_dcc_read(swjdp, &data, &ctrl);
2008 request |= (data << 8);
2009 cortex_m3_dcc_read(swjdp, &data, &ctrl);
2010 request |= (data << 16);
2011 cortex_m3_dcc_read(swjdp, &data, &ctrl);
2012 request |= (data << 24);
2013 target_request(target, request);
2014 }
2015 }
2016
2017 return ERROR_OK;
2018 }
2019
2020 static int cortex_m3_init_arch_info(struct target *target,
2021 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
2022 {
2023 int retval;
2024 struct armv7m_common *armv7m = &cortex_m3->armv7m;
2025
2026 armv7m_init_arch_info(target, armv7m);
2027
2028 /* prepare JTAG information for the new target */
2029 cortex_m3->jtag_info.tap = tap;
2030 cortex_m3->jtag_info.scann_size = 4;
2031
2032 /* default reset mode is to use srst if fitted
2033 * if not it will use CORTEX_M3_RESET_VECTRESET */
2034 cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
2035
2036 armv7m->arm.dap = &armv7m->dap;
2037
2038 /* Leave (only) generic DAP stuff for debugport_init(); */
2039 armv7m->dap.jtag_info = &cortex_m3->jtag_info;
2040 armv7m->dap.memaccess_tck = 8;
2041 /* Cortex-M3 has 4096 bytes autoincrement range */
2042 armv7m->dap.tar_autoincr_block = (1 << 12);
2043
2044 /* register arch-specific functions */
2045 armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
2046
2047 armv7m->post_debug_entry = NULL;
2048
2049 armv7m->pre_restore_context = NULL;
2050
2051 armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
2052 armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
2053
2054 target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
2055
2056 if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
2057 {
2058 return retval;
2059 }
2060
2061 return ERROR_OK;
2062 }
2063
2064 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
2065 {
2066 struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
2067
2068 cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
2069 cortex_m3_init_arch_info(target, cortex_m3, target->tap);
2070
2071 return ERROR_OK;
2072 }
2073
2074 /*--------------------------------------------------------------------------*/
2075
2076 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
2077 struct cortex_m3_common *cm3)
2078 {
2079 if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
2080 command_print(cmd_ctx, "target is not a Cortex-M3");
2081 return ERROR_TARGET_INVALID;
2082 }
2083 return ERROR_OK;
2084 }
2085
2086 /*
2087 * Only stuff below this line should need to verify that its target
2088 * is a Cortex-M3. Everything else should have indirected through the
2089 * cortexm3_target structure, which is only used with CM3 targets.
2090 */
2091
2092 static const struct {
2093 char name[10];
2094 unsigned mask;
2095 } vec_ids[] = {
2096 { "hard_err", VC_HARDERR, },
2097 { "int_err", VC_INTERR, },
2098 { "bus_err", VC_BUSERR, },
2099 { "state_err", VC_STATERR, },
2100 { "chk_err", VC_CHKERR, },
2101 { "nocp_err", VC_NOCPERR, },
2102 { "mm_err", VC_MMERR, },
2103 { "reset", VC_CORERESET, },
2104 };
2105
2106 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
2107 {
2108 struct target *target = get_current_target(CMD_CTX);
2109 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2110 struct armv7m_common *armv7m = &cortex_m3->armv7m;
2111 struct adiv5_dap *swjdp = &armv7m->dap;
2112 uint32_t demcr = 0;
2113 int retval;
2114
2115 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2116 if (retval != ERROR_OK)
2117 return retval;
2118
2119 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2120 if (retval != ERROR_OK)
2121 return retval;
2122
2123 if (CMD_ARGC > 0) {
2124 unsigned catch = 0;
2125
2126 if (CMD_ARGC == 1) {
2127 if (strcmp(CMD_ARGV[0], "all") == 0) {
2128 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2129 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2130 | VC_MMERR | VC_CORERESET;
2131 goto write;
2132 } else if (strcmp(CMD_ARGV[0], "none") == 0) {
2133 goto write;
2134 }
2135 }
2136 while (CMD_ARGC-- > 0) {
2137 unsigned i;
2138 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2139 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2140 continue;
2141 catch |= vec_ids[i].mask;
2142 break;
2143 }
2144 if (i == ARRAY_SIZE(vec_ids)) {
2145 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2146 return ERROR_INVALID_ARGUMENTS;
2147 }
2148 }
2149 write:
2150 /* For now, armv7m->demcr only stores vector catch flags. */
2151 armv7m->demcr = catch;
2152
2153 demcr &= ~0xffff;
2154 demcr |= catch;
2155
2156 /* write, but don't assume it stuck (why not??) */
2157 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2158 if (retval != ERROR_OK)
2159 return retval;
2160 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2161 if (retval != ERROR_OK)
2162 return retval;
2163
2164 /* FIXME be sure to clear DEMCR on clean server shutdown.
2165 * Otherwise the vector catch hardware could fire when there's
2166 * no debugger hooked up, causing much confusion...
2167 */
2168 }
2169
2170 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
2171 {
2172 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2173 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2174 }
2175
2176 return ERROR_OK;
2177 }
2178
2179 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
2180 {
2181 struct target *target = get_current_target(CMD_CTX);
2182 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2183 int retval;
2184
2185 static const Jim_Nvp nvp_maskisr_modes[] = {
2186 { .name = "auto", .value = CORTEX_M3_ISRMASK_AUTO },
2187 { .name = "off" , .value = CORTEX_M3_ISRMASK_OFF },
2188 { .name = "on" , .value = CORTEX_M3_ISRMASK_ON },
2189 { .name = NULL , .value = -1 },
2190 };
2191 const Jim_Nvp *n;
2192
2193
2194 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2195 if (retval != ERROR_OK)
2196 return retval;
2197
2198 if (target->state != TARGET_HALTED)
2199 {
2200 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2201 return ERROR_OK;
2202 }
2203
2204 if (CMD_ARGC > 0)
2205 {
2206 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2207 if (n->name == NULL)
2208 {
2209 return ERROR_COMMAND_SYNTAX_ERROR;
2210 }
2211 cortex_m3->isrmasking_mode = n->value;
2212
2213
2214 if(cortex_m3->isrmasking_mode == CORTEX_M3_ISRMASK_ON)
2215 {
2216 cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2217 }
2218 else
2219 {
2220 cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2221 }
2222 }
2223
2224 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode);
2225 command_print(CMD_CTX, "cortex_m3 interrupt mask %s", n->name);
2226
2227 return ERROR_OK;
2228 }
2229
2230 COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
2231 {
2232 struct target *target = get_current_target(CMD_CTX);
2233 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2234 int retval;
2235 char *reset_config;
2236
2237 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2238 if (retval != ERROR_OK)
2239 return retval;
2240
2241 if (CMD_ARGC > 0)
2242 {
2243 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2244 cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
2245 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2246 cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
2247 }
2248
2249 switch (cortex_m3->soft_reset_config)
2250 {
2251 case CORTEX_M3_RESET_SYSRESETREQ:
2252 reset_config = "sysresetreq";
2253 break;
2254
2255 case CORTEX_M3_RESET_VECTRESET:
2256 reset_config = "vectreset";
2257 break;
2258
2259 default:
2260 reset_config = "unknown";
2261 break;
2262 }
2263
2264 command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
2265
2266 return ERROR_OK;
2267 }
2268
2269 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2270 {
2271 .name = "maskisr",
2272 .handler = handle_cortex_m3_mask_interrupts_command,
2273 .mode = COMMAND_EXEC,
2274 .help = "mask cortex_m3 interrupts",
2275 .usage = "['auto'|'on'|'off']",
2276 },
2277 {
2278 .name = "vector_catch",
2279 .handler = handle_cortex_m3_vector_catch_command,
2280 .mode = COMMAND_EXEC,
2281 .help = "configure hardware vectors to trigger debug entry",
2282 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2283 },
2284 {
2285 .name = "reset_config",
2286 .handler = handle_cortex_m3_reset_config_command,
2287 .mode = COMMAND_ANY,
2288 .help = "configure software reset handling",
2289 .usage = "['srst'|'sysresetreq'|'vectreset']",
2290 },
2291 COMMAND_REGISTRATION_DONE
2292 };
2293 static const struct command_registration cortex_m3_command_handlers[] = {
2294 {
2295 .chain = armv7m_command_handlers,
2296 },
2297 {
2298 .name = "cortex_m3",
2299 .mode = COMMAND_EXEC,
2300 .help = "Cortex-M3 command group",
2301 .chain = cortex_m3_exec_command_handlers,
2302 },
2303 COMMAND_REGISTRATION_DONE
2304 };
2305
2306 struct target_type cortexm3_target =
2307 {
2308 .name = "cortex_m3",
2309
2310 .poll = cortex_m3_poll,
2311 .arch_state = armv7m_arch_state,
2312
2313 .target_request_data = cortex_m3_target_request_data,
2314
2315 .halt = cortex_m3_halt,
2316 .resume = cortex_m3_resume,
2317 .step = cortex_m3_step,
2318
2319 .assert_reset = cortex_m3_assert_reset,
2320 .deassert_reset = cortex_m3_deassert_reset,
2321 .soft_reset_halt = cortex_m3_soft_reset_halt,
2322
2323 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2324
2325 .read_memory = cortex_m3_read_memory,
2326 .write_memory = cortex_m3_write_memory,
2327 .bulk_write_memory = cortex_m3_bulk_write_memory,
2328 .checksum_memory = armv7m_checksum_memory,
2329 .blank_check_memory = armv7m_blank_check_memory,
2330
2331 .run_algorithm = armv7m_run_algorithm,
2332
2333 .add_breakpoint = cortex_m3_add_breakpoint,
2334 .remove_breakpoint = cortex_m3_remove_breakpoint,
2335 .add_watchpoint = cortex_m3_add_watchpoint,
2336 .remove_watchpoint = cortex_m3_remove_watchpoint,
2337
2338 .commands = cortex_m3_command_handlers,
2339 .target_create = cortex_m3_target_create,
2340 .init_target = cortex_m3_init_target,
2341 .examine = cortex_m3_examine,
2342 };
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