1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
40 #include "arm_opcodes.h"
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
48 /* forward declarations */
49 static int cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
50 static int cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
51 static void cortex_m3_enable_watchpoints(struct target
*target
);
52 static int cortex_m3_store_core_reg_u32(struct target
*target
,
53 enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
55 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common
*swjdp
,
56 uint32_t *value
, int regnum
)
61 /* because the DCB_DCRDR is used for the emulated dcc channel
62 * we have to save/restore the DCB_DCRDR when used */
64 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
66 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
68 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
69 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
70 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
72 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
73 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
74 dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
76 retval
= swjdp_transaction_endcheck(swjdp
);
78 /* restore DCB_DCRDR - this needs to be in a seperate
79 * transaction otherwise the emulated DCC channel breaks */
80 if (retval
== ERROR_OK
)
81 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
86 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common
*swjdp
,
87 uint32_t value
, int regnum
)
92 /* because the DCB_DCRDR is used for the emulated dcc channel
93 * we have to save/restore the DCB_DCRDR when used */
95 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
97 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
99 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
100 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
101 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
103 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
104 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
105 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
107 retval
= swjdp_transaction_endcheck(swjdp
);
109 /* restore DCB_DCRDR - this needs to be in a seperate
110 * transaction otherwise the emulated DCC channel breaks */
111 if (retval
== ERROR_OK
)
112 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
117 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
118 uint32_t mask_on
, uint32_t mask_off
)
120 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
121 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
123 /* mask off status bits */
124 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
125 /* create new register mask */
126 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
128 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
131 static int cortex_m3_clear_halt(struct target
*target
)
133 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
134 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
136 /* clear step if any */
137 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
139 /* Read Debug Fault Status Register */
140 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
141 /* Clear Debug Fault Status */
142 mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
143 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
148 static int cortex_m3_single_step_core(struct target
*target
)
150 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
151 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
154 /* backup dhcsr reg */
155 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
157 /* mask interrupts if not done already */
158 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
))
159 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
160 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
163 /* restore dhcsr reg */
164 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
165 cortex_m3_clear_halt(target
);
170 static int cortex_m3_endreset_event(struct target
*target
)
174 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
175 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
176 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
177 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
179 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
180 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"",dcb_demcr
);
182 /* this regsiter is used for emulated dcc channel */
183 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
185 /* Enable debug requests */
186 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
187 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
188 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
190 /* clear any interrupt masking */
191 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
193 /* Enable trace and dwt */
194 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
);
195 /* Monitor bus faults */
196 mem_ap_write_u32(swjdp
, NVIC_SHCSR
, SHCSR_BUSFAULTENA
);
199 target_write_u32(target
, FP_CTRL
, 3);
200 cortex_m3
->fpb_enabled
= 1;
202 /* Restore FPB registers */
203 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
205 target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
208 /* Restore DWT registers */
209 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++)
211 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
213 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
215 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
216 dwt_list
[i
].function
);
218 swjdp_transaction_endcheck(swjdp
);
220 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
222 /* make sure we have latest dhcsr flags */
223 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
228 static int cortex_m3_examine_debug_reason(struct target
*target
)
230 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
232 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
233 /* only check the debug reason if we don't know it already */
235 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
236 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
238 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
)
240 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
241 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
242 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
244 else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
245 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
246 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
247 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
248 else /* EXTERNAL, HALTED */
249 target
->debug_reason
= DBG_REASON_UNDEFINED
;
255 static int cortex_m3_examine_exception_reason(struct target
*target
)
257 uint32_t shcsr
, except_sr
, cfsr
= -1, except_ar
= -1;
258 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
259 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
261 mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
262 switch (armv7m
->exception_number
)
266 case 3: /* Hard Fault */
267 mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
268 if (except_sr
& 0x40000000)
270 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
273 case 4: /* Memory Management */
274 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
275 mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
277 case 5: /* Bus Fault */
278 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
279 mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
281 case 6: /* Usage Fault */
282 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
284 case 11: /* SVCall */
286 case 12: /* Debug Monitor */
287 mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
289 case 14: /* PendSV */
291 case 15: /* SysTick */
297 swjdp_transaction_endcheck(swjdp
);
298 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
"", armv7m_exception_string(armv7m
->exception_number
), \
299 shcsr
, except_sr
, cfsr
, except_ar
);
303 static int cortex_m3_debug_entry(struct target
*target
)
308 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
309 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
310 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
314 cortex_m3_clear_halt(target
);
315 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
317 if ((retval
= armv7m
->examine_debug_reason(target
)) != ERROR_OK
)
320 /* Examine target state and mode */
321 /* First load register acessible through core debug port*/
322 int num_regs
= armv7m
->core_cache
->num_regs
;
324 for (i
= 0; i
< num_regs
; i
++)
326 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
327 armv7m
->read_core_reg(target
, i
);
330 xPSR
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32);
332 #ifdef ARMV7_GDB_HACKS
333 /* FIXME this breaks on scan chains with more than one Cortex-M3.
334 * Instead, each CM3 should have its own dummy value...
336 /* copy real xpsr reg for gdb, setting thumb bit */
337 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
338 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
339 armv7m_gdb_dummy_cpsr_reg
.valid
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
;
340 armv7m_gdb_dummy_cpsr_reg
.dirty
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
;
343 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
346 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
;
347 cortex_m3_store_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 16, xPSR
&~ 0xff);
350 /* Are we in an exception handler */
353 armv7m
->core_mode
= ARMV7M_MODE_HANDLER
;
354 armv7m
->exception_number
= (xPSR
& 0x1FF);
358 armv7m
->core_mode
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
, 0, 1);
359 armv7m
->exception_number
= 0;
362 if (armv7m
->exception_number
)
364 cortex_m3_examine_exception_reason(target
);
367 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
368 armv7m_mode_strings
[armv7m
->core_mode
],
369 *(uint32_t*)(armv7m
->core_cache
->reg_list
[15].value
),
370 target_state_name(target
));
372 if (armv7m
->post_debug_entry
)
373 armv7m
->post_debug_entry(target
);
378 static int cortex_m3_poll(struct target
*target
)
381 enum target_state prev_target_state
= target
->state
;
382 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
383 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
385 /* Read from Debug Halting Control and Status Register */
386 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
387 if (retval
!= ERROR_OK
)
389 target
->state
= TARGET_UNKNOWN
;
393 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
395 /* check if still in reset */
396 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
398 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
400 target
->state
= TARGET_RESET
;
405 if (target
->state
== TARGET_RESET
)
407 /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
408 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
);
409 cortex_m3_endreset_event(target
);
410 target
->state
= TARGET_RUNNING
;
411 prev_target_state
= TARGET_RUNNING
;
414 if (cortex_m3
->dcb_dhcsr
& S_HALT
)
416 target
->state
= TARGET_HALTED
;
418 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
))
420 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
423 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
425 if (prev_target_state
== TARGET_DEBUG_RUNNING
)
428 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
431 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
435 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
436 * How best to model low power modes?
439 if (target
->state
== TARGET_UNKNOWN
)
441 /* check if processor is retiring instructions */
442 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
)
444 target
->state
= TARGET_RUNNING
;
452 static int cortex_m3_halt(struct target
*target
)
454 LOG_DEBUG("target->state: %s",
455 target_state_name(target
));
457 if (target
->state
== TARGET_HALTED
)
459 LOG_DEBUG("target was already halted");
463 if (target
->state
== TARGET_UNKNOWN
)
465 LOG_WARNING("target was in unknown state when halt was requested");
468 if (target
->state
== TARGET_RESET
)
470 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
472 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
473 return ERROR_TARGET_FAILURE
;
477 /* we came here in a reset_halt or reset_init sequence
478 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
480 target
->debug_reason
= DBG_REASON_DBGRQ
;
486 /* Write to Debug Halting Control and Status Register */
487 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
489 target
->debug_reason
= DBG_REASON_DBGRQ
;
494 static int cortex_m3_soft_reset_halt(struct target
*target
)
496 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
497 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
498 uint32_t dcb_dhcsr
= 0;
499 int retval
, timeout
= 0;
501 /* Enter debug state on reset, cf. end_reset_event() */
502 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
504 /* Request a reset */
505 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
, AIRCR_VECTKEY
| AIRCR_VECTRESET
);
506 target
->state
= TARGET_RESET
;
508 /* registers are now invalid */
509 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
511 while (timeout
< 100)
513 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
514 if (retval
== ERROR_OK
)
516 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
517 if ((dcb_dhcsr
& S_HALT
) && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
))
519 LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32
", nvic_dfsr 0x%" PRIx32
"", dcb_dhcsr
, cortex_m3
->nvic_dfsr
);
520 cortex_m3_poll(target
);
524 LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32
", %i ms", dcb_dhcsr
, timeout
);
533 static void cortex_m3_enable_breakpoints(struct target
*target
)
535 struct breakpoint
*breakpoint
= target
->breakpoints
;
537 /* set any pending breakpoints */
540 if (breakpoint
->set
== 0)
541 cortex_m3_set_breakpoint(target
, breakpoint
);
542 breakpoint
= breakpoint
->next
;
546 static int cortex_m3_resume(struct target
*target
, int current
,
547 uint32_t address
, int handle_breakpoints
, int debug_execution
)
549 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
550 struct breakpoint
*breakpoint
= NULL
;
553 if (target
->state
!= TARGET_HALTED
)
555 LOG_WARNING("target not halted");
556 return ERROR_TARGET_NOT_HALTED
;
559 if (!debug_execution
)
561 target_free_all_working_areas(target
);
562 cortex_m3_enable_breakpoints(target
);
563 cortex_m3_enable_watchpoints(target
);
568 /* Disable interrupts */
569 /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
570 * This is probably the same issue as Cortex-M3 Errata 377493:
571 * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
572 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
573 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
574 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
576 /* Make sure we are in Thumb mode */
577 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
578 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32) | (1 << 24));
579 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
580 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
583 /* current = 1: continue on current pc, otherwise continue at <address> */
586 buf_set_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32, address
);
587 armv7m
->core_cache
->reg_list
[15].dirty
= 1;
588 armv7m
->core_cache
->reg_list
[15].valid
= 1;
591 resume_pc
= buf_get_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32);
593 armv7m_restore_context(target
);
595 /* the front-end may request us not to handle breakpoints */
596 if (handle_breakpoints
)
598 /* Single step past breakpoint at current address */
599 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
601 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
603 breakpoint
->unique_id
);
604 cortex_m3_unset_breakpoint(target
, breakpoint
);
605 cortex_m3_single_step_core(target
);
606 cortex_m3_set_breakpoint(target
, breakpoint
);
611 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
613 target
->debug_reason
= DBG_REASON_NOTHALTED
;
615 /* registers are now invalid */
616 register_cache_invalidate(armv7m
->core_cache
);
618 if (!debug_execution
)
620 target
->state
= TARGET_RUNNING
;
621 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
622 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
626 target
->state
= TARGET_DEBUG_RUNNING
;
627 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
628 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
634 /* int irqstepcount = 0; */
635 static int cortex_m3_step(struct target
*target
, int current
,
636 uint32_t address
, int handle_breakpoints
)
638 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
639 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
640 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
641 struct breakpoint
*breakpoint
= NULL
;
643 if (target
->state
!= TARGET_HALTED
)
645 LOG_WARNING("target not halted");
646 return ERROR_TARGET_NOT_HALTED
;
649 /* current = 1: continue on current pc, otherwise continue at <address> */
651 buf_set_u32(cortex_m3
->armv7m
.core_cache
->reg_list
[15].value
,
654 /* the front-end may request us not to handle breakpoints */
655 if (handle_breakpoints
) {
656 breakpoint
= breakpoint_find(target
, buf_get_u32(armv7m
657 ->core_cache
->reg_list
[15].value
, 0, 32));
659 cortex_m3_unset_breakpoint(target
, breakpoint
);
662 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
664 armv7m_restore_context(target
);
666 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
668 /* set step and clear halt */
669 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
670 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
672 /* registers are now invalid */
673 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
676 cortex_m3_set_breakpoint(target
, breakpoint
);
678 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
" nvic_icsr = 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
680 cortex_m3_debug_entry(target
);
681 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
683 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
" nvic_icsr = 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
687 static int cortex_m3_assert_reset(struct target
*target
)
689 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
690 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
693 LOG_DEBUG("target->state: %s",
694 target_state_name(target
));
696 enum reset_types jtag_reset_config
= jtag_get_reset_config();
699 * We can reset Cortex-M3 targets using just the NVIC without
700 * requiring SRST, getting a SoC reset (or a core-only reset)
701 * instead of a system reset.
703 if (!(jtag_reset_config
& RESET_HAS_SRST
))
706 /* Enable debug requests */
707 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
708 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
709 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
711 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
713 if (!target
->reset_halt
)
715 /* Set/Clear C_MASKINTS in a separate operation */
716 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
)
717 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
| C_HALT
);
719 /* clear any debug flags before resuming */
720 cortex_m3_clear_halt(target
);
722 /* clear C_HALT in dhcsr reg */
723 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
725 /* Enter debug state on reset, cf. end_reset_event() */
726 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
);
730 /* Enter debug state on reset, cf. end_reset_event() */
731 mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
735 * When nRST is asserted on most Stellaris devices, it clears some of
736 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
737 * and OpenOCD depends on those TRMs. So we won't use SRST on those
738 * chips. (Only power-on reset should affect debug state, beyond a
739 * few specified bits; not the chip's nRST input, wired to SRST.)
741 * REVISIT current errata specs don't seem to cover this issue.
742 * Do we have more details than this email?
743 * https://lists.berlios.de/pipermail
744 * /openocd-development/2008-August/003065.html
746 if (strcmp(target
->variant
, "lm3s") == 0)
748 /* Check for silicon revisions with the issue. */
751 if (target_read_u32(target
, 0x400fe000, &did0
) == ERROR_OK
)
753 switch ((did0
>> 16) & 0xff)
756 /* all Sandstorm suffer issue */
762 /* Fury and DustDevil rev A have
763 * this nRST problem. It should
764 * be fixed in rev B silicon.
766 if (((did0
>> 8) & 0xff) == 0)
770 /* Tempest should be fine. */
778 /* default to asserting srst */
779 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
781 jtag_add_reset(1, 1);
785 jtag_add_reset(0, 1);
790 /* Use a standard Cortex-M3 software reset mechanism.
791 * SYSRESETREQ will reset SoC peripherals outside the
792 * core, like watchdog timers, if the SoC wires it up
793 * correctly. Else VECRESET can reset just the core.
795 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
796 AIRCR_VECTKEY
| AIRCR_SYSRESETREQ
);
797 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
800 /* I do not know why this is necessary, but it
801 * fixes strange effects (step/resume cause NMI
802 * after reset) on LM3S6918 -- Michael Schwingen
805 mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
809 target
->state
= TARGET_RESET
;
810 jtag_add_sleep(50000);
812 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
814 if (target
->reset_halt
)
817 if ((retval
= target_halt(target
)) != ERROR_OK
)
824 static int cortex_m3_deassert_reset(struct target
*target
)
826 LOG_DEBUG("target->state: %s",
827 target_state_name(target
));
829 /* deassert reset lines */
830 jtag_add_reset(0, 0);
836 cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
841 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
842 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
846 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
850 if (cortex_m3
->auto_bp_type
)
852 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
855 if (breakpoint
->type
== BKPT_HARD
)
857 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
859 if (fp_num
>= cortex_m3
->fp_num_code
)
861 LOG_ERROR("Can not find free FPB Comparator!");
864 breakpoint
->set
= fp_num
+ 1;
865 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
866 comparator_list
[fp_num
].used
= 1;
867 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
868 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
869 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"", fp_num
, comparator_list
[fp_num
].fpcr_value
);
870 if (!cortex_m3
->fpb_enabled
)
872 LOG_DEBUG("FPB wasn't enabled, do it now");
873 target_write_u32(target
, FP_CTRL
, 3);
876 else if (breakpoint
->type
== BKPT_SOFT
)
879 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
880 if ((retval
= target_read_memory(target
, breakpoint
->address
& 0xFFFFFFFE, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
884 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, breakpoint
->length
, 1, code
)) != ERROR_OK
)
888 breakpoint
->set
= 0x11; /* Any nice value but 0 */
891 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
892 breakpoint
->unique_id
,
893 (int)(breakpoint
->type
),
902 cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
905 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
906 struct cortex_m3_fp_comparator
* comparator_list
= cortex_m3
->fp_comparator_list
;
908 if (!breakpoint
->set
)
910 LOG_WARNING("breakpoint not set");
914 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
915 breakpoint
->unique_id
,
916 (int)(breakpoint
->type
),
921 if (breakpoint
->type
== BKPT_HARD
)
923 int fp_num
= breakpoint
->set
- 1;
924 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
))
926 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
929 comparator_list
[fp_num
].used
= 0;
930 comparator_list
[fp_num
].fpcr_value
= 0;
931 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
935 /* restore original instruction (kept in target endianness) */
936 if (breakpoint
->length
== 4)
938 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
945 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
957 cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
959 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
961 if (cortex_m3
->auto_bp_type
)
963 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
964 #ifdef ARMV7_GDB_HACKS
965 if (breakpoint
->length
!= 2) {
966 /* XXX Hack: Replace all breakpoints with length != 2 with
967 * a hardware breakpoint. */
968 breakpoint
->type
= BKPT_HARD
;
969 breakpoint
->length
= 2;
974 if ((breakpoint
->type
== BKPT_HARD
) && (breakpoint
->address
>= 0x20000000))
976 LOG_INFO("flash patch comparator requested outside code memory region");
977 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
980 if ((breakpoint
->type
== BKPT_SOFT
) && (breakpoint
->address
< 0x20000000))
982 LOG_INFO("soft breakpoint requested in code (flash) memory region");
983 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
986 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1))
988 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
989 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
992 if ((breakpoint
->length
!= 2))
994 LOG_INFO("only breakpoints of two bytes length supported");
995 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
998 if (breakpoint
->type
== BKPT_HARD
)
999 cortex_m3
->fp_code_available
--;
1000 cortex_m3_set_breakpoint(target
, breakpoint
);
1006 cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1008 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1010 /* REVISIT why check? FBP can be updated with core running ... */
1011 if (target
->state
!= TARGET_HALTED
)
1013 LOG_WARNING("target not halted");
1014 return ERROR_TARGET_NOT_HALTED
;
1017 if (cortex_m3
->auto_bp_type
)
1019 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
1022 if (breakpoint
->set
)
1024 cortex_m3_unset_breakpoint(target
, breakpoint
);
1027 if (breakpoint
->type
== BKPT_HARD
)
1028 cortex_m3
->fp_code_available
++;
1034 cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1037 uint32_t mask
, temp
;
1038 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1040 /* watchpoint params were validated earlier */
1042 temp
= watchpoint
->length
;
1049 /* REVISIT Don't fully trust these "not used" records ... users
1050 * may set up breakpoints by hand, e.g. dual-address data value
1051 * watchpoint using comparator #1; comparator #0 matching cycle
1052 * count; send data trace info through ITM and TPIU; etc
1054 struct cortex_m3_dwt_comparator
*comparator
;
1056 for (comparator
= cortex_m3
->dwt_comparator_list
;
1057 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1058 comparator
++, dwt_num
++)
1060 if (dwt_num
>= cortex_m3
->dwt_num_comp
)
1062 LOG_ERROR("Can not find free DWT Comparator");
1065 comparator
->used
= 1;
1066 watchpoint
->set
= dwt_num
+ 1;
1068 comparator
->comp
= watchpoint
->address
;
1069 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1072 comparator
->mask
= mask
;
1073 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1076 switch (watchpoint
->rw
) {
1078 comparator
->function
= 5;
1081 comparator
->function
= 6;
1084 comparator
->function
= 7;
1087 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1088 comparator
->function
);
1090 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1091 watchpoint
->unique_id
, dwt_num
,
1092 (unsigned) comparator
->comp
,
1093 (unsigned) comparator
->mask
,
1094 (unsigned) comparator
->function
);
1099 cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1101 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1102 struct cortex_m3_dwt_comparator
*comparator
;
1105 if (!watchpoint
->set
)
1107 LOG_WARNING("watchpoint (wpid: %d) not set",
1108 watchpoint
->unique_id
);
1112 dwt_num
= watchpoint
->set
- 1;
1114 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1115 watchpoint
->unique_id
, dwt_num
,
1116 (unsigned) watchpoint
->address
);
1118 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
))
1120 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1124 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1125 comparator
->used
= 0;
1126 comparator
->function
= 0;
1127 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1128 comparator
->function
);
1130 watchpoint
->set
= 0;
1136 cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1138 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1140 if (cortex_m3
->dwt_comp_available
< 1)
1142 LOG_DEBUG("no comparators?");
1143 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1146 /* hardware doesn't support data value masking */
1147 if (watchpoint
->mask
!= ~(uint32_t)0) {
1148 LOG_DEBUG("watchpoint value masks not supported");
1149 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1152 /* hardware allows address masks of up to 32K */
1155 for (mask
= 0; mask
< 16; mask
++) {
1156 if ((1u << mask
) == watchpoint
->length
)
1160 LOG_DEBUG("unsupported watchpoint length");
1161 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1163 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1164 LOG_DEBUG("watchpoint address is unaligned");
1165 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1168 /* Caller doesn't seem to be able to describe watching for data
1169 * values of zero; that flags "no value".
1171 * REVISIT This DWT may well be able to watch for specific data
1172 * values. Requires comparator #1 to set DATAVMATCH and match
1173 * the data, and another comparator (DATAVADDR0) matching addr.
1175 if (watchpoint
->value
) {
1176 LOG_DEBUG("data value watchpoint not YET supported");
1177 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1180 cortex_m3
->dwt_comp_available
--;
1181 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1187 cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1189 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1191 /* REVISIT why check? DWT can be updated with core running ... */
1192 if (target
->state
!= TARGET_HALTED
)
1194 LOG_WARNING("target not halted");
1195 return ERROR_TARGET_NOT_HALTED
;
1198 if (watchpoint
->set
)
1200 cortex_m3_unset_watchpoint(target
, watchpoint
);
1203 cortex_m3
->dwt_comp_available
++;
1204 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1209 static void cortex_m3_enable_watchpoints(struct target
*target
)
1211 struct watchpoint
*watchpoint
= target
->watchpoints
;
1213 /* set any pending watchpoints */
1216 if (watchpoint
->set
== 0)
1217 cortex_m3_set_watchpoint(target
, watchpoint
);
1218 watchpoint
= watchpoint
->next
;
1222 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1223 enum armv7m_regtype type
, uint32_t num
, uint32_t * value
)
1226 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1227 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1229 /* NOTE: we "know" here that the register identifiers used
1230 * in the v7m header match the Cortex-M3 Debug Core Register
1231 * Selector values for R0..R15, xPSR, MSP, and PSP.
1235 /* read a normal core register */
1236 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1238 if (retval
!= ERROR_OK
)
1240 LOG_ERROR("JTAG failure %i",retval
);
1241 return ERROR_JTAG_DEVICE_ERROR
;
1243 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"",(int)num
,*value
);
1246 case ARMV7M_PRIMASK
:
1247 case ARMV7M_BASEPRI
:
1248 case ARMV7M_FAULTMASK
:
1249 case ARMV7M_CONTROL
:
1250 /* Cortex-M3 packages these four registers as bitfields
1251 * in one Debug Core register. So say r0 and r2 docs;
1252 * it was removed from r1 docs, but still works.
1254 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1258 case ARMV7M_PRIMASK
:
1259 *value
= buf_get_u32((uint8_t*)value
, 0, 1);
1262 case ARMV7M_BASEPRI
:
1263 *value
= buf_get_u32((uint8_t*)value
, 8, 8);
1266 case ARMV7M_FAULTMASK
:
1267 *value
= buf_get_u32((uint8_t*)value
, 16, 1);
1270 case ARMV7M_CONTROL
:
1271 *value
= buf_get_u32((uint8_t*)value
, 24, 2);
1275 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1279 return ERROR_INVALID_ARGUMENTS
;
1285 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1286 enum armv7m_regtype type
, uint32_t num
, uint32_t value
)
1290 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1291 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1293 #ifdef ARMV7_GDB_HACKS
1294 /* If the LR register is being modified, make sure it will put us
1295 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1296 * hack to deal with the fact that gdb will sometimes "forge"
1297 * return addresses, and doesn't set the LSB correctly (i.e., when
1298 * printing expressions containing function calls, it sets LR = 0.)
1299 * Valid exception return codes have bit 0 set too.
1301 if (num
== ARMV7M_R14
)
1305 /* NOTE: we "know" here that the register identifiers used
1306 * in the v7m header match the Cortex-M3 Debug Core Register
1307 * Selector values for R0..R15, xPSR, MSP, and PSP.
1311 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1312 if (retval
!= ERROR_OK
)
1314 LOG_ERROR("JTAG failure %i", retval
);
1315 armv7m
->core_cache
->reg_list
[num
].dirty
= armv7m
->core_cache
->reg_list
[num
].valid
;
1316 return ERROR_JTAG_DEVICE_ERROR
;
1318 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1321 case ARMV7M_PRIMASK
:
1322 case ARMV7M_BASEPRI
:
1323 case ARMV7M_FAULTMASK
:
1324 case ARMV7M_CONTROL
:
1325 /* Cortex-M3 packages these four registers as bitfields
1326 * in one Debug Core register. So say r0 and r2 docs;
1327 * it was removed from r1 docs, but still works.
1329 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1333 case ARMV7M_PRIMASK
:
1334 buf_set_u32((uint8_t*)®
, 0, 1, value
);
1337 case ARMV7M_BASEPRI
:
1338 buf_set_u32((uint8_t*)®
, 8, 8, value
);
1341 case ARMV7M_FAULTMASK
:
1342 buf_set_u32((uint8_t*)®
, 16, 1, value
);
1345 case ARMV7M_CONTROL
:
1346 buf_set_u32((uint8_t*)®
, 24, 2, value
);
1350 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1352 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1356 return ERROR_INVALID_ARGUMENTS
;
1362 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1363 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1365 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1366 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1367 int retval
= ERROR_INVALID_ARGUMENTS
;
1369 /* cortex_m3 handles unaligned memory access */
1370 if (count
&& buffer
) {
1373 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1376 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1379 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1387 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1388 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1390 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1391 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1392 int retval
= ERROR_INVALID_ARGUMENTS
;
1394 if (count
&& buffer
) {
1397 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1400 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1403 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1411 static int cortex_m3_bulk_write_memory(struct target
*target
, uint32_t address
,
1412 uint32_t count
, uint8_t *buffer
)
1414 return cortex_m3_write_memory(target
, address
, 4, count
, buffer
);
1417 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1418 struct target
*target
)
1420 armv7m_build_reg_cache(target
);
1424 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1425 * on r/w if the core is not running, and clear on resume or reset ... or
1426 * at least, in a post_restore_context() method.
1429 struct dwt_reg_state
{
1430 struct target
*target
;
1432 uint32_t value
; /* scratch/cache */
1435 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1437 struct dwt_reg_state
*state
= reg
->arch_info
;
1439 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1442 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1444 struct dwt_reg_state
*state
= reg
->arch_info
;
1446 return target_write_u32(state
->target
, state
->addr
,
1447 buf_get_u32(buf
, 0, reg
->size
));
1456 static struct dwt_reg dwt_base_regs
[] = {
1457 { DWT_CTRL
, "dwt_ctrl", 32, },
1458 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1459 /* plus some 8 bit counters, useful for profiling with TPIU */
1462 static struct dwt_reg dwt_comp
[] = {
1463 #define DWT_COMPARATOR(i) \
1464 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1465 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1466 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1471 #undef DWT_COMPARATOR
1474 static const struct reg_arch_type dwt_reg_type
= {
1475 .get
= cortex_m3_dwt_get_reg
,
1476 .set
= cortex_m3_dwt_set_reg
,
1480 cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1482 struct dwt_reg_state
*state
;
1484 state
= calloc(1, sizeof *state
);
1487 state
->addr
= d
->addr
;
1492 r
->value
= &state
->value
;
1493 r
->arch_info
= state
;
1494 r
->type
= &dwt_reg_type
;
1498 cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1501 struct reg_cache
*cache
;
1502 struct cortex_m3_dwt_comparator
*comparator
;
1505 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1507 LOG_DEBUG("no DWT");
1511 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1512 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1513 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1514 sizeof(struct cortex_m3_dwt_comparator
));
1515 if (!cm3
->dwt_comparator_list
) {
1517 cm3
->dwt_num_comp
= 0;
1518 LOG_ERROR("out of mem");
1522 cache
= calloc(1, sizeof *cache
);
1525 free(cm3
->dwt_comparator_list
);
1528 cache
->name
= "cortex-m3 dwt registers";
1529 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1530 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1531 if (!cache
->reg_list
) {
1536 for (reg
= 0; reg
< 2; reg
++)
1537 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1538 dwt_base_regs
+ reg
);
1540 comparator
= cm3
->dwt_comparator_list
;
1541 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1544 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1545 for (j
= 0; j
< 3; j
++, reg
++)
1546 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1547 dwt_comp
+ 3 * i
+ j
);
1550 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1551 cm3
->dwt_cache
= cache
;
1553 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1554 dwtcr
, cm3
->dwt_num_comp
,
1555 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1557 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1558 * implement single-address data value watchpoints ... so we
1559 * won't need to check it later, when asked to set one up.
1563 static int cortex_m3_examine(struct target
*target
)
1566 uint32_t cpuid
, fpcr
;
1568 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1569 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
1571 if ((retval
= ahbap_debugport_init(swjdp
)) != ERROR_OK
)
1574 if (!target_was_examined(target
))
1576 target_set_examined(target
);
1578 /* Read from Device Identification Registers */
1579 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1580 if (retval
!= ERROR_OK
)
1583 if (((cpuid
>> 4) & 0xc3f) == 0xc23)
1584 LOG_DEBUG("CORTEX-M3 processor detected");
1585 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1587 /* NOTE: FPB and DWT are both optional. */
1590 target_read_u32(target
, FP_CTRL
, &fpcr
);
1591 cortex_m3
->auto_bp_type
= 1;
1592 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits [14:12] and [7:4] */
1593 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1594 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1595 cortex_m3
->fp_comparator_list
= calloc(cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
, sizeof(struct cortex_m3_fp_comparator
));
1596 cortex_m3
->fpb_enabled
= fpcr
& 1;
1597 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
1599 cortex_m3
->fp_comparator_list
[i
].type
= (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1600 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1602 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i", fpcr
, cortex_m3
->fp_num_code
, cortex_m3
->fp_num_lit
);
1605 cortex_m3_dwt_setup(cortex_m3
, target
);
1607 /* These hardware breakpoints only work for code in flash! */
1608 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1609 target_name(target
),
1610 cortex_m3
->fp_num_code
,
1611 cortex_m3
->dwt_num_comp
);
1617 static int cortex_m3_dcc_read(struct swjdp_common
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1621 mem_ap_read_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1622 *ctrl
= (uint8_t)dcrdr
;
1623 *value
= (uint8_t)(dcrdr
>> 8);
1625 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1627 /* write ack back to software dcc register
1628 * signify we have read data */
1629 if (dcrdr
& (1 << 0))
1632 mem_ap_write_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1638 static int cortex_m3_target_request_data(struct target
*target
,
1639 uint32_t size
, uint8_t *buffer
)
1641 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1642 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1647 for (i
= 0; i
< (size
* 4); i
++)
1649 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1656 static int cortex_m3_handle_target_request(void *priv
)
1658 struct target
*target
= priv
;
1659 if (!target_was_examined(target
))
1661 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1662 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1664 if (!target
->dbg_msg_enabled
)
1667 if (target
->state
== TARGET_RUNNING
)
1672 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1674 /* check if we have data */
1675 if (ctrl
& (1 << 0))
1679 /* we assume target is quick enough */
1681 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1682 request
|= (data
<< 8);
1683 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1684 request
|= (data
<< 16);
1685 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1686 request
|= (data
<< 24);
1687 target_request(target
, request
);
1694 static int cortex_m3_init_arch_info(struct target
*target
,
1695 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
1698 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1700 armv7m_init_arch_info(target
, armv7m
);
1702 /* prepare JTAG information for the new target */
1703 cortex_m3
->jtag_info
.tap
= tap
;
1704 cortex_m3
->jtag_info
.scann_size
= 4;
1706 armv7m
->swjdp_info
.dp_select_value
= -1;
1707 armv7m
->swjdp_info
.ap_csw_value
= -1;
1708 armv7m
->swjdp_info
.ap_tar_value
= -1;
1709 armv7m
->swjdp_info
.jtag_info
= &cortex_m3
->jtag_info
;
1710 armv7m
->swjdp_info
.memaccess_tck
= 8;
1711 armv7m
->swjdp_info
.tar_autoincr_block
= (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
1713 /* register arch-specific functions */
1714 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
1716 armv7m
->post_debug_entry
= NULL
;
1718 armv7m
->pre_restore_context
= NULL
;
1719 armv7m
->post_restore_context
= NULL
;
1721 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
1722 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
1724 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
1726 if ((retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
)) != ERROR_OK
)
1734 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
1736 struct cortex_m3_common
*cortex_m3
= calloc(1,sizeof(struct cortex_m3_common
));
1738 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
1739 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
1744 /*--------------------------------------------------------------------------*/
1746 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
1747 struct cortex_m3_common
*cm3
)
1749 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
1750 command_print(cmd_ctx
, "target is not a Cortex-M3");
1751 return ERROR_TARGET_INVALID
;
1757 * Only stuff below this line should need to verify that its target
1758 * is a Cortex-M3. Everything else should have indirected through the
1759 * cortexm3_target structure, which is only used with CM3 targets.
1763 * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1764 * as at least ARM-1156T2. The interesting thing about Cortex-M is
1765 * that *only* Thumb2 disassembly matters. There are also some small
1766 * additions to Thumb2 that are specific to ARMv7-M.
1768 COMMAND_HANDLER(handle_cortex_m3_disassemble_command
)
1771 struct target
*target
= get_current_target(CMD_CTX
);
1772 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1774 unsigned long count
= 1;
1775 struct arm_instruction cur_instruction
;
1777 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
1778 if (retval
!= ERROR_OK
)
1784 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[1], count
);
1787 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1790 command_print(CMD_CTX
,
1791 "usage: cortex_m3 disassemble <address> [<count>]");
1796 retval
= thumb2_opcode(target
, address
, &cur_instruction
);
1797 if (retval
!= ERROR_OK
)
1799 command_print(CMD_CTX
, "%s", cur_instruction
.text
);
1800 address
+= cur_instruction
.instruction_size
;
1806 static const struct {
1810 { "hard_err", VC_HARDERR
, },
1811 { "int_err", VC_INTERR
, },
1812 { "bus_err", VC_BUSERR
, },
1813 { "state_err", VC_STATERR
, },
1814 { "chk_err", VC_CHKERR
, },
1815 { "nocp_err", VC_NOCPERR
, },
1816 { "mm_err", VC_MMERR
, },
1817 { "reset", VC_CORERESET
, },
1820 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
1822 struct target
*target
= get_current_target(CMD_CTX
);
1823 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1824 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1825 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1829 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
1830 if (retval
!= ERROR_OK
)
1833 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1838 if (CMD_ARGC
== 1) {
1839 if (strcmp(CMD_ARGV
[0], "all") == 0) {
1840 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
1841 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
1842 | VC_MMERR
| VC_CORERESET
;
1844 } else if (strcmp(CMD_ARGV
[0], "none") == 0) {
1848 while (CMD_ARGC
-- > 0) {
1850 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
1851 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
1853 catch |= vec_ids
[i
].mask
;
1856 if (i
== ARRAY_SIZE(vec_ids
)) {
1857 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
1858 return ERROR_INVALID_ARGUMENTS
;
1865 /* write, but don't assume it stuck */
1866 mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
1867 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1870 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++)
1872 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
1873 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
1879 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
1881 struct target
*target
= get_current_target(CMD_CTX
);
1882 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1885 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
1886 if (retval
!= ERROR_OK
)
1889 if (target
->state
!= TARGET_HALTED
)
1891 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
1898 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], enable
);
1899 uint32_t mask_on
= C_HALT
| (enable
? C_MASKINTS
: 0);
1900 uint32_t mask_off
= enable
? 0 : C_MASKINTS
;
1901 cortex_m3_write_debug_halt_mask(target
, mask_on
, mask_off
);
1904 command_print(CMD_CTX
, "cortex_m3 interrupt mask %s",
1905 (cortex_m3
->dcb_dhcsr
& C_MASKINTS
) ? "on" : "off");
1910 static const struct command_registration cortex_m3_exec_command_handlers
[] = {
1912 .name
= "disassemble",
1913 .handler
= &handle_cortex_m3_disassemble_command
,
1914 .mode
= COMMAND_EXEC
,
1915 .help
= "disassemble Thumb2 instructions",
1916 .usage
= "<address> [<count>]",
1920 .handler
= &handle_cortex_m3_mask_interrupts_command
,
1921 .mode
= COMMAND_EXEC
,
1922 .help
= "mask cortex_m3 interrupts",
1923 .usage
= "['on'|'off']",
1926 .name
= "vector_catch",
1927 .handler
= &handle_cortex_m3_vector_catch_command
,
1928 .mode
= COMMAND_EXEC
,
1929 .help
= "catch hardware vectors",
1930 .usage
= "['all'|'none'|<list>]",
1932 COMMAND_REGISTRATION_DONE
1934 static const struct command_registration cortex_m3_command_handlers
[] = {
1936 .chain
= armv7m_command_handlers
,
1939 .name
= "cortex_m3",
1940 .mode
= COMMAND_ANY
,
1941 .help
= "Cortex-M3 command group",
1942 .chain
= cortex_m3_exec_command_handlers
,
1944 COMMAND_REGISTRATION_DONE
1947 struct target_type cortexm3_target
=
1949 .name
= "cortex_m3",
1951 .poll
= cortex_m3_poll
,
1952 .arch_state
= armv7m_arch_state
,
1954 .target_request_data
= cortex_m3_target_request_data
,
1956 .halt
= cortex_m3_halt
,
1957 .resume
= cortex_m3_resume
,
1958 .step
= cortex_m3_step
,
1960 .assert_reset
= cortex_m3_assert_reset
,
1961 .deassert_reset
= cortex_m3_deassert_reset
,
1962 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
1964 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
1966 .read_memory
= cortex_m3_read_memory
,
1967 .write_memory
= cortex_m3_write_memory
,
1968 .bulk_write_memory
= cortex_m3_bulk_write_memory
,
1969 .checksum_memory
= armv7m_checksum_memory
,
1970 .blank_check_memory
= armv7m_blank_check_memory
,
1972 .run_algorithm
= armv7m_run_algorithm
,
1974 .add_breakpoint
= cortex_m3_add_breakpoint
,
1975 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
1976 .add_watchpoint
= cortex_m3_add_watchpoint
,
1977 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
1979 .commands
= cortex_m3_command_handlers
,
1980 .target_create
= cortex_m3_target_create
,
1981 .init_target
= cortex_m3_init_target
,
1982 .examine
= cortex_m3_examine
,
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