1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
25 #ifndef OPENOCD_TARGET_CORTEX_M_H
26 #define OPENOCD_TARGET_CORTEX_M_H
29 #include "helper/bits.h"
31 #define CORTEX_M_COMMON_MAGIC 0x1A451A45
33 #define SYSTEM_CONTROL_BASE 0x400FE000
35 #define ITM_TER0 0xE0000E00
36 #define ITM_TPR 0xE0000E40
37 #define ITM_TCR 0xE0000E80
38 #define ITM_LAR 0xE0000FB0
39 #define ITM_LAR_KEY 0xC5ACCE55
41 #define CPUID 0xE000ED00
43 #define ARM_CPUID_PARTNO_MASK 0xFFF0
45 #define CORTEX_M23_PARTNO 0xD200
46 #define CORTEX_M33_PARTNO 0xD210
48 /* Debug Control Block */
49 #define DCB_DHCSR 0xE000EDF0
50 #define DCB_DCRSR 0xE000EDF4
51 #define DCB_DCRDR 0xE000EDF8
52 #define DCB_DEMCR 0xE000EDFC
54 #define DCRSR_WnR BIT(16)
56 #define DWT_CTRL 0xE0001000
57 #define DWT_CYCCNT 0xE0001004
58 #define DWT_PCSR 0xE000101C
59 #define DWT_COMP0 0xE0001020
60 #define DWT_MASK0 0xE0001024
61 #define DWT_FUNCTION0 0xE0001028
62 #define DWT_DEVARCH 0xE0001FBC
64 #define DWT_DEVARCH_ARMV8M 0x101A02
66 #define FP_CTRL 0xE0002000
67 #define FP_REMAP 0xE0002004
68 #define FP_COMP0 0xE0002008
69 #define FP_COMP1 0xE000200C
70 #define FP_COMP2 0xE0002010
71 #define FP_COMP3 0xE0002014
72 #define FP_COMP4 0xE0002018
73 #define FP_COMP5 0xE000201C
74 #define FP_COMP6 0xE0002020
75 #define FP_COMP7 0xE0002024
77 #define FPU_CPACR 0xE000ED88
78 #define FPU_FPCCR 0xE000EF34
79 #define FPU_FPCAR 0xE000EF38
80 #define FPU_FPDSCR 0xE000EF3C
82 #define TPIU_SSPSR 0xE0040000
83 #define TPIU_CSPSR 0xE0040004
84 #define TPIU_ACPR 0xE0040010
85 #define TPIU_SPPR 0xE00400F0
86 #define TPIU_FFSR 0xE0040300
87 #define TPIU_FFCR 0xE0040304
88 #define TPIU_FSCR 0xE0040308
90 /* Maximum SWO prescaler value. */
91 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
93 /* DCB_DHCSR bit and field definitions */
94 #define DBGKEY (0xA05Ful << 16)
95 #define C_DEBUGEN BIT(0)
98 #define C_MASKINTS BIT(3)
99 #define S_REGRDY BIT(16)
100 #define S_HALT BIT(17)
101 #define S_SLEEP BIT(18)
102 #define S_LOCKUP BIT(19)
103 #define S_RETIRE_ST BIT(24)
104 #define S_RESET_ST BIT(25)
106 /* DCB_DEMCR bit and field definitions */
107 #define TRCENA BIT(24)
108 #define VC_HARDERR BIT(10)
109 #define VC_INTERR BIT(9)
110 #define VC_BUSERR BIT(8)
111 #define VC_STATERR BIT(7)
112 #define VC_CHKERR BIT(6)
113 #define VC_NOCPERR BIT(5)
114 #define VC_MMERR BIT(4)
115 #define VC_CORERESET BIT(0)
117 #define NVIC_ICTR 0xE000E004
118 #define NVIC_ISE0 0xE000E100
119 #define NVIC_ICSR 0xE000ED04
120 #define NVIC_AIRCR 0xE000ED0C
121 #define NVIC_SHCSR 0xE000ED24
122 #define NVIC_CFSR 0xE000ED28
123 #define NVIC_MMFSRb 0xE000ED28
124 #define NVIC_BFSRb 0xE000ED29
125 #define NVIC_USFSRh 0xE000ED2A
126 #define NVIC_HFSR 0xE000ED2C
127 #define NVIC_DFSR 0xE000ED30
128 #define NVIC_MMFAR 0xE000ED34
129 #define NVIC_BFAR 0xE000ED38
131 /* NVIC_AIRCR bits */
132 #define AIRCR_VECTKEY (0x5FAul << 16)
133 #define AIRCR_SYSRESETREQ BIT(2)
134 #define AIRCR_VECTCLRACTIVE BIT(1)
135 #define AIRCR_VECTRESET BIT(0)
136 /* NVIC_SHCSR bits */
137 #define SHCSR_BUSFAULTENA BIT(17)
139 #define DFSR_HALTED 1
141 #define DFSR_DWTTRAP 4
142 #define DFSR_VCATCH 8
143 #define DFSR_EXTERNAL 16
146 #define FPCR_LITERAL 1
147 #define FPCR_REPLACE_REMAP (0ul << 30)
148 #define FPCR_REPLACE_BKPT_LOW (1ul << 30)
149 #define FPCR_REPLACE_BKPT_HIGH (2ul << 30)
150 #define FPCR_REPLACE_BKPT_BOTH (3ul << 30)
152 struct cortex_m_fp_comparator
{
156 uint32_t fpcr_address
;
159 struct cortex_m_dwt_comparator
{
164 uint32_t dwt_comparator_address
;
167 enum cortex_m_soft_reset_config
{
168 CORTEX_M_RESET_SYSRESETREQ
,
169 CORTEX_M_RESET_VECTRESET
,
172 enum cortex_m_isrmasking_mode
{
173 CORTEX_M_ISRMASK_AUTO
,
174 CORTEX_M_ISRMASK_OFF
,
176 CORTEX_M_ISRMASK_STEPONLY
,
179 struct cortex_m_common
{
182 /* Context information */
184 uint32_t nvic_dfsr
; /* Debug Fault Status Register - shows reason for debug halt */
185 uint32_t nvic_icsr
; /* Interrupt Control State Register - shows active and pending IRQ */
187 /* Flash Patch and Breakpoint (FPB) */
192 struct cortex_m_fp_comparator
*fp_comparator_list
;
194 /* Data Watchpoint and Trace (DWT) */
196 int dwt_comp_available
;
197 uint32_t dwt_devarch
;
198 struct cortex_m_dwt_comparator
*dwt_comparator_list
;
199 struct reg_cache
*dwt_cache
;
201 enum cortex_m_soft_reset_config soft_reset_config
;
202 bool vectreset_supported
;
204 enum cortex_m_isrmasking_mode isrmasking_mode
;
206 struct armv7m_common armv7m
;
210 /* Whether this target has the erratum that makes C_MASKINTS not apply to
211 * already pending interrupts */
212 bool maskints_erratum
;
215 static inline struct cortex_m_common
*
216 target_to_cm(struct target
*target
)
218 return container_of(target
->arch_info
,
219 struct cortex_m_common
, armv7m
);
222 int cortex_m_examine(struct target
*target
);
223 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
224 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
225 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
226 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
227 int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
);
228 int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
);
229 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
);
230 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
);
231 void cortex_m_enable_breakpoints(struct target
*target
);
232 void cortex_m_enable_watchpoints(struct target
*target
);
233 void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
);
234 void cortex_m_deinit_target(struct target
*target
);
235 int cortex_m_profiling(struct target
*target
, uint32_t *samples
,
236 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
);
238 #endif /* OPENOCD_TARGET_CORTEX_M_H */
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