Support for debugging on ARMv8-M CPUs
[openocd.git] / src / target / cortex_m.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifndef OPENOCD_TARGET_CORTEX_M_H
26 #define OPENOCD_TARGET_CORTEX_M_H
27
28 #include "armv7m.h"
29
30 #define CORTEX_M_COMMON_MAGIC 0x1A451A45
31
32 #define SYSTEM_CONTROL_BASE 0x400FE000
33
34 #define ITM_TER0 0xE0000E00
35 #define ITM_TPR 0xE0000E40
36 #define ITM_TCR 0xE0000E80
37 #define ITM_LAR 0xE0000FB0
38 #define ITM_LAR_KEY 0xC5ACCE55
39
40 #define CPUID 0xE000ED00
41
42 #define ARM_CPUID_PARTNO_MASK 0xFFF0
43
44 #define CORTEX_M23_PARTNO 0xD200
45 #define CORTEX_M33_PARTNO 0xD210
46
47 /* Debug Control Block */
48 #define DCB_DHCSR 0xE000EDF0
49 #define DCB_DCRSR 0xE000EDF4
50 #define DCB_DCRDR 0xE000EDF8
51 #define DCB_DEMCR 0xE000EDFC
52
53 #define DCRSR_WnR (1 << 16)
54
55 #define DWT_CTRL 0xE0001000
56 #define DWT_CYCCNT 0xE0001004
57 #define DWT_PCSR 0xE000101C
58 #define DWT_COMP0 0xE0001020
59 #define DWT_MASK0 0xE0001024
60 #define DWT_FUNCTION0 0xE0001028
61 #define DWT_DEVARCH 0xE0001FBC
62
63 #define DWT_DEVARCH_ARMV8M 0x101A02
64
65 #define FP_CTRL 0xE0002000
66 #define FP_REMAP 0xE0002004
67 #define FP_COMP0 0xE0002008
68 #define FP_COMP1 0xE000200C
69 #define FP_COMP2 0xE0002010
70 #define FP_COMP3 0xE0002014
71 #define FP_COMP4 0xE0002018
72 #define FP_COMP5 0xE000201C
73 #define FP_COMP6 0xE0002020
74 #define FP_COMP7 0xE0002024
75
76 #define FPU_CPACR 0xE000ED88
77 #define FPU_FPCCR 0xE000EF34
78 #define FPU_FPCAR 0xE000EF38
79 #define FPU_FPDSCR 0xE000EF3C
80
81 #define TPIU_SSPSR 0xE0040000
82 #define TPIU_CSPSR 0xE0040004
83 #define TPIU_ACPR 0xE0040010
84 #define TPIU_SPPR 0xE00400F0
85 #define TPIU_FFSR 0xE0040300
86 #define TPIU_FFCR 0xE0040304
87 #define TPIU_FSCR 0xE0040308
88
89 /* DCB_DHCSR bit and field definitions */
90 #define DBGKEY (0xA05F << 16)
91 #define C_DEBUGEN (1 << 0)
92 #define C_HALT (1 << 1)
93 #define C_STEP (1 << 2)
94 #define C_MASKINTS (1 << 3)
95 #define S_REGRDY (1 << 16)
96 #define S_HALT (1 << 17)
97 #define S_SLEEP (1 << 18)
98 #define S_LOCKUP (1 << 19)
99 #define S_RETIRE_ST (1 << 24)
100 #define S_RESET_ST (1 << 25)
101
102 /* DCB_DEMCR bit and field definitions */
103 #define TRCENA (1 << 24)
104 #define VC_HARDERR (1 << 10)
105 #define VC_INTERR (1 << 9)
106 #define VC_BUSERR (1 << 8)
107 #define VC_STATERR (1 << 7)
108 #define VC_CHKERR (1 << 6)
109 #define VC_NOCPERR (1 << 5)
110 #define VC_MMERR (1 << 4)
111 #define VC_CORERESET (1 << 0)
112
113 #define NVIC_ICTR 0xE000E004
114 #define NVIC_ISE0 0xE000E100
115 #define NVIC_ICSR 0xE000ED04
116 #define NVIC_AIRCR 0xE000ED0C
117 #define NVIC_SHCSR 0xE000ED24
118 #define NVIC_CFSR 0xE000ED28
119 #define NVIC_MMFSRb 0xE000ED28
120 #define NVIC_BFSRb 0xE000ED29
121 #define NVIC_USFSRh 0xE000ED2A
122 #define NVIC_HFSR 0xE000ED2C
123 #define NVIC_DFSR 0xE000ED30
124 #define NVIC_MMFAR 0xE000ED34
125 #define NVIC_BFAR 0xE000ED38
126
127 /* NVIC_AIRCR bits */
128 #define AIRCR_VECTKEY (0x5FA << 16)
129 #define AIRCR_SYSRESETREQ (1 << 2)
130 #define AIRCR_VECTCLRACTIVE (1 << 1)
131 #define AIRCR_VECTRESET (1 << 0)
132 /* NVIC_SHCSR bits */
133 #define SHCSR_BUSFAULTENA (1 << 17)
134 /* NVIC_DFSR bits */
135 #define DFSR_HALTED 1
136 #define DFSR_BKPT 2
137 #define DFSR_DWTTRAP 4
138 #define DFSR_VCATCH 8
139 #define DFSR_EXTERNAL 16
140
141 #define FPCR_CODE 0
142 #define FPCR_LITERAL 1
143 #define FPCR_REPLACE_REMAP (0 << 30)
144 #define FPCR_REPLACE_BKPT_LOW (1 << 30)
145 #define FPCR_REPLACE_BKPT_HIGH (2 << 30)
146 #define FPCR_REPLACE_BKPT_BOTH (3 << 30)
147
148 struct cortex_m_fp_comparator {
149 bool used;
150 int type;
151 uint32_t fpcr_value;
152 uint32_t fpcr_address;
153 };
154
155 struct cortex_m_dwt_comparator {
156 bool used;
157 uint32_t comp;
158 uint32_t mask;
159 uint32_t function;
160 uint32_t dwt_comparator_address;
161 };
162
163 enum cortex_m_soft_reset_config {
164 CORTEX_M_RESET_SYSRESETREQ,
165 CORTEX_M_RESET_VECTRESET,
166 };
167
168 enum cortex_m_isrmasking_mode {
169 CORTEX_M_ISRMASK_AUTO,
170 CORTEX_M_ISRMASK_OFF,
171 CORTEX_M_ISRMASK_ON,
172 CORTEX_M_ISRMASK_STEPONLY,
173 };
174
175 struct cortex_m_common {
176 int common_magic;
177
178 /* Context information */
179 uint32_t dcb_dhcsr;
180 uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
181 uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
182
183 /* Flash Patch and Breakpoint (FPB) */
184 int fp_num_lit;
185 int fp_num_code;
186 int fp_rev;
187 bool fpb_enabled;
188 struct cortex_m_fp_comparator *fp_comparator_list;
189
190 /* Data Watchpoint and Trace (DWT) */
191 int dwt_num_comp;
192 int dwt_comp_available;
193 uint32_t dwt_devarch;
194 struct cortex_m_dwt_comparator *dwt_comparator_list;
195 struct reg_cache *dwt_cache;
196
197 enum cortex_m_soft_reset_config soft_reset_config;
198 bool vectreset_supported;
199
200 enum cortex_m_isrmasking_mode isrmasking_mode;
201
202 struct armv7m_common armv7m;
203
204 int apsel;
205
206 /* Whether this target has the erratum that makes C_MASKINTS not apply to
207 * already pending interrupts */
208 bool maskints_erratum;
209 };
210
211 static inline struct cortex_m_common *
212 target_to_cm(struct target *target)
213 {
214 return container_of(target->arch_info,
215 struct cortex_m_common, armv7m);
216 }
217
218 int cortex_m_examine(struct target *target);
219 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
220 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
221 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
222 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
223 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint);
224 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint);
225 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
226 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
227 void cortex_m_enable_breakpoints(struct target *target);
228 void cortex_m_enable_watchpoints(struct target *target);
229 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target);
230 void cortex_m_deinit_target(struct target *target);
231 int cortex_m_profiling(struct target *target, uint32_t *samples,
232 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
233
234 #endif /* OPENOCD_TARGET_CORTEX_M_H */