354532823d2404a85d3e45682fc7cafc77a3e371
[openocd.git] / src / target / cortex_m.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifndef OPENOCD_TARGET_CORTEX_M_H
26 #define OPENOCD_TARGET_CORTEX_M_H
27
28 #include "armv7m.h"
29 #include "helper/bits.h"
30
31 #define CORTEX_M_COMMON_MAGIC 0x1A451A45
32
33 #define SYSTEM_CONTROL_BASE 0x400FE000
34
35 #define ITM_TER0 0xE0000E00
36 #define ITM_TPR 0xE0000E40
37 #define ITM_TCR 0xE0000E80
38 #define ITM_LAR 0xE0000FB0
39 #define ITM_LAR_KEY 0xC5ACCE55
40
41 #define CPUID 0xE000ED00
42
43 #define ARM_CPUID_PARTNO_MASK 0xFFF0
44
45 #define CORTEX_M23_PARTNO 0xD200
46 #define CORTEX_M33_PARTNO 0xD210
47
48 /* Debug Control Block */
49 #define DCB_DHCSR 0xE000EDF0
50 #define DCB_DCRSR 0xE000EDF4
51 #define DCB_DCRDR 0xE000EDF8
52 #define DCB_DEMCR 0xE000EDFC
53 #define DCB_DSCSR 0xE000EE08
54
55 #define DCRSR_WnR BIT(16)
56
57 #define DWT_CTRL 0xE0001000
58 #define DWT_CYCCNT 0xE0001004
59 #define DWT_PCSR 0xE000101C
60 #define DWT_COMP0 0xE0001020
61 #define DWT_MASK0 0xE0001024
62 #define DWT_FUNCTION0 0xE0001028
63 #define DWT_DEVARCH 0xE0001FBC
64
65 #define DWT_DEVARCH_ARMV8M 0x101A02
66
67 #define FP_CTRL 0xE0002000
68 #define FP_REMAP 0xE0002004
69 #define FP_COMP0 0xE0002008
70 #define FP_COMP1 0xE000200C
71 #define FP_COMP2 0xE0002010
72 #define FP_COMP3 0xE0002014
73 #define FP_COMP4 0xE0002018
74 #define FP_COMP5 0xE000201C
75 #define FP_COMP6 0xE0002020
76 #define FP_COMP7 0xE0002024
77
78 #define FPU_CPACR 0xE000ED88
79 #define FPU_FPCCR 0xE000EF34
80 #define FPU_FPCAR 0xE000EF38
81 #define FPU_FPDSCR 0xE000EF3C
82
83 #define TPIU_SSPSR 0xE0040000
84 #define TPIU_CSPSR 0xE0040004
85 #define TPIU_ACPR 0xE0040010
86 #define TPIU_SPPR 0xE00400F0
87 #define TPIU_FFSR 0xE0040300
88 #define TPIU_FFCR 0xE0040304
89 #define TPIU_FSCR 0xE0040308
90
91 /* Maximum SWO prescaler value. */
92 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
93
94 /* DCB_DHCSR bit and field definitions */
95 #define DBGKEY (0xA05Ful << 16)
96 #define C_DEBUGEN BIT(0)
97 #define C_HALT BIT(1)
98 #define C_STEP BIT(2)
99 #define C_MASKINTS BIT(3)
100 #define S_REGRDY BIT(16)
101 #define S_HALT BIT(17)
102 #define S_SLEEP BIT(18)
103 #define S_LOCKUP BIT(19)
104 #define S_RETIRE_ST BIT(24)
105 #define S_RESET_ST BIT(25)
106
107 /* DCB_DEMCR bit and field definitions */
108 #define TRCENA BIT(24)
109 #define VC_HARDERR BIT(10)
110 #define VC_INTERR BIT(9)
111 #define VC_BUSERR BIT(8)
112 #define VC_STATERR BIT(7)
113 #define VC_CHKERR BIT(6)
114 #define VC_NOCPERR BIT(5)
115 #define VC_MMERR BIT(4)
116 #define VC_CORERESET BIT(0)
117
118 /* DCB_DSCSR bit and field definitions */
119 #define DSCSR_CDS BIT(16)
120
121 /* NVIC registers */
122 #define NVIC_ICTR 0xE000E004
123 #define NVIC_ISE0 0xE000E100
124 #define NVIC_ICSR 0xE000ED04
125 #define NVIC_AIRCR 0xE000ED0C
126 #define NVIC_SHCSR 0xE000ED24
127 #define NVIC_CFSR 0xE000ED28
128 #define NVIC_MMFSRb 0xE000ED28
129 #define NVIC_BFSRb 0xE000ED29
130 #define NVIC_USFSRh 0xE000ED2A
131 #define NVIC_HFSR 0xE000ED2C
132 #define NVIC_DFSR 0xE000ED30
133 #define NVIC_MMFAR 0xE000ED34
134 #define NVIC_BFAR 0xE000ED38
135 #define NVIC_SFSR 0xE000EDE4
136 #define NVIC_SFAR 0xE000EDE8
137
138 /* NVIC_AIRCR bits */
139 #define AIRCR_VECTKEY (0x5FAul << 16)
140 #define AIRCR_SYSRESETREQ BIT(2)
141 #define AIRCR_VECTCLRACTIVE BIT(1)
142 #define AIRCR_VECTRESET BIT(0)
143 /* NVIC_SHCSR bits */
144 #define SHCSR_BUSFAULTENA BIT(17)
145 /* NVIC_DFSR bits */
146 #define DFSR_HALTED 1
147 #define DFSR_BKPT 2
148 #define DFSR_DWTTRAP 4
149 #define DFSR_VCATCH 8
150 #define DFSR_EXTERNAL 16
151
152 #define FPCR_CODE 0
153 #define FPCR_LITERAL 1
154 #define FPCR_REPLACE_REMAP (0ul << 30)
155 #define FPCR_REPLACE_BKPT_LOW (1ul << 30)
156 #define FPCR_REPLACE_BKPT_HIGH (2ul << 30)
157 #define FPCR_REPLACE_BKPT_BOTH (3ul << 30)
158
159 struct cortex_m_fp_comparator {
160 bool used;
161 int type;
162 uint32_t fpcr_value;
163 uint32_t fpcr_address;
164 };
165
166 struct cortex_m_dwt_comparator {
167 bool used;
168 uint32_t comp;
169 uint32_t mask;
170 uint32_t function;
171 uint32_t dwt_comparator_address;
172 };
173
174 enum cortex_m_soft_reset_config {
175 CORTEX_M_RESET_SYSRESETREQ,
176 CORTEX_M_RESET_VECTRESET,
177 };
178
179 enum cortex_m_isrmasking_mode {
180 CORTEX_M_ISRMASK_AUTO,
181 CORTEX_M_ISRMASK_OFF,
182 CORTEX_M_ISRMASK_ON,
183 CORTEX_M_ISRMASK_STEPONLY,
184 };
185
186 struct cortex_m_common {
187 int common_magic;
188
189 /* Context information */
190 uint32_t dcb_dhcsr;
191 uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
192 uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
193
194 /* Flash Patch and Breakpoint (FPB) */
195 int fp_num_lit;
196 int fp_num_code;
197 int fp_rev;
198 bool fpb_enabled;
199 struct cortex_m_fp_comparator *fp_comparator_list;
200
201 /* Data Watchpoint and Trace (DWT) */
202 int dwt_num_comp;
203 int dwt_comp_available;
204 uint32_t dwt_devarch;
205 struct cortex_m_dwt_comparator *dwt_comparator_list;
206 struct reg_cache *dwt_cache;
207
208 enum cortex_m_soft_reset_config soft_reset_config;
209 bool vectreset_supported;
210
211 enum cortex_m_isrmasking_mode isrmasking_mode;
212
213 struct armv7m_common armv7m;
214
215 int apsel;
216
217 /* Whether this target has the erratum that makes C_MASKINTS not apply to
218 * already pending interrupts */
219 bool maskints_erratum;
220 };
221
222 static inline struct cortex_m_common *
223 target_to_cm(struct target *target)
224 {
225 return container_of(target->arch_info,
226 struct cortex_m_common, armv7m);
227 }
228
229 int cortex_m_examine(struct target *target);
230 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
231 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
232 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
233 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
234 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint);
235 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint);
236 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
237 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
238 void cortex_m_enable_breakpoints(struct target *target);
239 void cortex_m_enable_watchpoints(struct target *target);
240 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target);
241 void cortex_m_deinit_target(struct target *target);
242 int cortex_m_profiling(struct target *target, uint32_t *samples,
243 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
244
245 #endif /* OPENOCD_TARGET_CORTEX_M_H */