Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
target/cortex_m: constify some variables
[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FBP remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortexm_dap_read_coreregister_u32(struct target *target,
60 uint32_t *value, int regnum)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortexm_dap_write_coreregister_u32(struct target *target,
93 uint32_t value, int regnum)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_clear_halt(struct target *target)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 struct armv7m_common *armv7m = &cortex_m->armv7m;
143 int retval;
144
145 /* clear step if any */
146 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
147
148 /* Read Debug Fault Status Register */
149 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
150 if (retval != ERROR_OK)
151 return retval;
152
153 /* Clear Debug Fault Status */
154 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
155 if (retval != ERROR_OK)
156 return retval;
157 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
158
159 return ERROR_OK;
160 }
161
162 static int cortex_m_single_step_core(struct target *target)
163 {
164 struct cortex_m_common *cortex_m = target_to_cm(target);
165 struct armv7m_common *armv7m = &cortex_m->armv7m;
166 int retval;
167
168 /* Mask interrupts before clearing halt, if done already. This avoids
169 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
170 * HALT can put the core into an unknown state.
171 */
172 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
173 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
174 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
175 if (retval != ERROR_OK)
176 return retval;
177 }
178 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
179 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
180 if (retval != ERROR_OK)
181 return retval;
182 LOG_DEBUG(" ");
183
184 /* restore dhcsr reg */
185 cortex_m_clear_halt(target);
186
187 return ERROR_OK;
188 }
189
190 static int cortex_m_enable_fpb(struct target *target)
191 {
192 int retval = target_write_u32(target, FP_CTRL, 3);
193 if (retval != ERROR_OK)
194 return retval;
195
196 /* check the fpb is actually enabled */
197 uint32_t fpctrl;
198 retval = target_read_u32(target, FP_CTRL, &fpctrl);
199 if (retval != ERROR_OK)
200 return retval;
201
202 if (fpctrl & 1)
203 return ERROR_OK;
204
205 return ERROR_FAIL;
206 }
207
208 static int cortex_m_endreset_event(struct target *target)
209 {
210 int i;
211 int retval;
212 uint32_t dcb_demcr;
213 struct cortex_m_common *cortex_m = target_to_cm(target);
214 struct armv7m_common *armv7m = &cortex_m->armv7m;
215 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
216 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
217 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
218
219 /* REVISIT The four debug monitor bits are currently ignored... */
220 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
221 if (retval != ERROR_OK)
222 return retval;
223 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
224
225 /* this register is used for emulated dcc channel */
226 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Enable debug requests */
231 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
232 if (retval != ERROR_OK)
233 return retval;
234 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
235 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
236 if (retval != ERROR_OK)
237 return retval;
238 }
239
240 /* clear any interrupt masking */
241 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
242
243 /* Enable features controlled by ITM and DWT blocks, and catch only
244 * the vectors we were told to pay attention to.
245 *
246 * Target firmware is responsible for all fault handling policy
247 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
248 * or manual updates to the NVIC SHCSR and CCR registers.
249 */
250 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
251 if (retval != ERROR_OK)
252 return retval;
253
254 /* Paranoia: evidently some (early?) chips don't preserve all the
255 * debug state (including FBP, DWT, etc) across reset...
256 */
257
258 /* Enable FPB */
259 retval = cortex_m_enable_fpb(target);
260 if (retval != ERROR_OK) {
261 LOG_ERROR("Failed to enable the FPB");
262 return retval;
263 }
264
265 cortex_m->fpb_enabled = 1;
266
267 /* Restore FPB registers */
268 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
269 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
270 if (retval != ERROR_OK)
271 return retval;
272 }
273
274 /* Restore DWT registers */
275 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
276 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
277 dwt_list[i].comp);
278 if (retval != ERROR_OK)
279 return retval;
280 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
281 dwt_list[i].mask);
282 if (retval != ERROR_OK)
283 return retval;
284 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
285 dwt_list[i].function);
286 if (retval != ERROR_OK)
287 return retval;
288 }
289 retval = dap_run(swjdp);
290 if (retval != ERROR_OK)
291 return retval;
292
293 register_cache_invalidate(armv7m->arm.core_cache);
294
295 /* make sure we have latest dhcsr flags */
296 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
297
298 return retval;
299 }
300
301 static int cortex_m_examine_debug_reason(struct target *target)
302 {
303 struct cortex_m_common *cortex_m = target_to_cm(target);
304
305 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
306 * only check the debug reason if we don't know it already */
307
308 if ((target->debug_reason != DBG_REASON_DBGRQ)
309 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
310 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
311 target->debug_reason = DBG_REASON_BREAKPOINT;
312 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
313 target->debug_reason = DBG_REASON_WPTANDBKPT;
314 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
315 target->debug_reason = DBG_REASON_WATCHPOINT;
316 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
317 target->debug_reason = DBG_REASON_BREAKPOINT;
318 else /* EXTERNAL, HALTED */
319 target->debug_reason = DBG_REASON_UNDEFINED;
320 }
321
322 return ERROR_OK;
323 }
324
325 static int cortex_m_examine_exception_reason(struct target *target)
326 {
327 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
328 struct armv7m_common *armv7m = target_to_armv7m(target);
329 struct adiv5_dap *swjdp = armv7m->arm.dap;
330 int retval;
331
332 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
333 if (retval != ERROR_OK)
334 return retval;
335 switch (armv7m->exception_number) {
336 case 2: /* NMI */
337 break;
338 case 3: /* Hard Fault */
339 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
340 if (retval != ERROR_OK)
341 return retval;
342 if (except_sr & 0x40000000) {
343 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
344 if (retval != ERROR_OK)
345 return retval;
346 }
347 break;
348 case 4: /* Memory Management */
349 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
350 if (retval != ERROR_OK)
351 return retval;
352 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
353 if (retval != ERROR_OK)
354 return retval;
355 break;
356 case 5: /* Bus Fault */
357 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
358 if (retval != ERROR_OK)
359 return retval;
360 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
361 if (retval != ERROR_OK)
362 return retval;
363 break;
364 case 6: /* Usage Fault */
365 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
366 if (retval != ERROR_OK)
367 return retval;
368 break;
369 case 11: /* SVCall */
370 break;
371 case 12: /* Debug Monitor */
372 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
373 if (retval != ERROR_OK)
374 return retval;
375 break;
376 case 14: /* PendSV */
377 break;
378 case 15: /* SysTick */
379 break;
380 default:
381 except_sr = 0;
382 break;
383 }
384 retval = dap_run(swjdp);
385 if (retval == ERROR_OK)
386 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
387 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
388 armv7m_exception_string(armv7m->exception_number),
389 shcsr, except_sr, cfsr, except_ar);
390 return retval;
391 }
392
393 static int cortex_m_debug_entry(struct target *target)
394 {
395 int i;
396 uint32_t xPSR;
397 int retval;
398 struct cortex_m_common *cortex_m = target_to_cm(target);
399 struct armv7m_common *armv7m = &cortex_m->armv7m;
400 struct arm *arm = &armv7m->arm;
401 struct reg *r;
402
403 LOG_DEBUG(" ");
404
405 cortex_m_clear_halt(target);
406 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
407 if (retval != ERROR_OK)
408 return retval;
409
410 retval = armv7m->examine_debug_reason(target);
411 if (retval != ERROR_OK)
412 return retval;
413
414 /* Examine target state and mode
415 * First load register accessible through core debug port */
416 int num_regs = arm->core_cache->num_regs;
417
418 for (i = 0; i < num_regs; i++) {
419 r = &armv7m->arm.core_cache->reg_list[i];
420 if (!r->valid)
421 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
422 }
423
424 r = arm->cpsr;
425 xPSR = buf_get_u32(r->value, 0, 32);
426
427 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
428 if (xPSR & 0xf00) {
429 r->dirty = r->valid;
430 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
431 }
432
433 /* Are we in an exception handler */
434 if (xPSR & 0x1FF) {
435 armv7m->exception_number = (xPSR & 0x1FF);
436
437 arm->core_mode = ARM_MODE_HANDLER;
438 arm->map = armv7m_msp_reg_map;
439 } else {
440 unsigned control = buf_get_u32(arm->core_cache
441 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
442
443 /* is this thread privileged? */
444 arm->core_mode = control & 1
445 ? ARM_MODE_USER_THREAD
446 : ARM_MODE_THREAD;
447
448 /* which stack is it using? */
449 if (control & 2)
450 arm->map = armv7m_psp_reg_map;
451 else
452 arm->map = armv7m_msp_reg_map;
453
454 armv7m->exception_number = 0;
455 }
456
457 if (armv7m->exception_number)
458 cortex_m_examine_exception_reason(target);
459
460 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
461 arm_mode_name(arm->core_mode),
462 buf_get_u32(arm->pc->value, 0, 32),
463 target_state_name(target));
464
465 if (armv7m->post_debug_entry) {
466 retval = armv7m->post_debug_entry(target);
467 if (retval != ERROR_OK)
468 return retval;
469 }
470
471 return ERROR_OK;
472 }
473
474 static int cortex_m_poll(struct target *target)
475 {
476 int detected_failure = ERROR_OK;
477 int retval = ERROR_OK;
478 enum target_state prev_target_state = target->state;
479 struct cortex_m_common *cortex_m = target_to_cm(target);
480 struct armv7m_common *armv7m = &cortex_m->armv7m;
481
482 /* Read from Debug Halting Control and Status Register */
483 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
484 if (retval != ERROR_OK) {
485 target->state = TARGET_UNKNOWN;
486 return retval;
487 }
488
489 /* Recover from lockup. See ARMv7-M architecture spec,
490 * section B1.5.15 "Unrecoverable exception cases".
491 */
492 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
493 LOG_ERROR("%s -- clearing lockup after double fault",
494 target_name(target));
495 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
496 target->debug_reason = DBG_REASON_DBGRQ;
497
498 /* We have to execute the rest (the "finally" equivalent, but
499 * still throw this exception again).
500 */
501 detected_failure = ERROR_FAIL;
502
503 /* refresh status bits */
504 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
505 if (retval != ERROR_OK)
506 return retval;
507 }
508
509 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
510 target->state = TARGET_RESET;
511 return ERROR_OK;
512 }
513
514 if (target->state == TARGET_RESET) {
515 /* Cannot switch context while running so endreset is
516 * called with target->state == TARGET_RESET
517 */
518 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
519 cortex_m->dcb_dhcsr);
520 retval = cortex_m_endreset_event(target);
521 if (retval != ERROR_OK) {
522 target->state = TARGET_UNKNOWN;
523 return retval;
524 }
525 target->state = TARGET_RUNNING;
526 prev_target_state = TARGET_RUNNING;
527 }
528
529 if (cortex_m->dcb_dhcsr & S_HALT) {
530 target->state = TARGET_HALTED;
531
532 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
533 retval = cortex_m_debug_entry(target);
534 if (retval != ERROR_OK)
535 return retval;
536
537 if (arm_semihosting(target, &retval) != 0)
538 return retval;
539
540 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
541 }
542 if (prev_target_state == TARGET_DEBUG_RUNNING) {
543 LOG_DEBUG(" ");
544 retval = cortex_m_debug_entry(target);
545 if (retval != ERROR_OK)
546 return retval;
547
548 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
549 }
550 }
551
552 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
553 * How best to model low power modes?
554 */
555
556 if (target->state == TARGET_UNKNOWN) {
557 /* check if processor is retiring instructions */
558 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
559 target->state = TARGET_RUNNING;
560 retval = ERROR_OK;
561 }
562 }
563
564 /* Did we detect a failure condition that we cleared? */
565 if (detected_failure != ERROR_OK)
566 retval = detected_failure;
567 return retval;
568 }
569
570 static int cortex_m_halt(struct target *target)
571 {
572 LOG_DEBUG("target->state: %s",
573 target_state_name(target));
574
575 if (target->state == TARGET_HALTED) {
576 LOG_DEBUG("target was already halted");
577 return ERROR_OK;
578 }
579
580 if (target->state == TARGET_UNKNOWN)
581 LOG_WARNING("target was in unknown state when halt was requested");
582
583 if (target->state == TARGET_RESET) {
584 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
585 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
586 return ERROR_TARGET_FAILURE;
587 } else {
588 /* we came here in a reset_halt or reset_init sequence
589 * debug entry was already prepared in cortex_m3_assert_reset()
590 */
591 target->debug_reason = DBG_REASON_DBGRQ;
592
593 return ERROR_OK;
594 }
595 }
596
597 /* Write to Debug Halting Control and Status Register */
598 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
599
600 target->debug_reason = DBG_REASON_DBGRQ;
601
602 return ERROR_OK;
603 }
604
605 static int cortex_m_soft_reset_halt(struct target *target)
606 {
607 struct cortex_m_common *cortex_m = target_to_cm(target);
608 struct armv7m_common *armv7m = &cortex_m->armv7m;
609 uint32_t dcb_dhcsr = 0;
610 int retval, timeout = 0;
611
612 /* soft_reset_halt is deprecated on cortex_m as the same functionality
613 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
614 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
615 * core, not the peripherals */
616 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
617
618 /* Enter debug state on reset; restore DEMCR in endreset_event() */
619 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
620 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
621 if (retval != ERROR_OK)
622 return retval;
623
624 /* Request a core-only reset */
625 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
626 AIRCR_VECTKEY | AIRCR_VECTRESET);
627 if (retval != ERROR_OK)
628 return retval;
629 target->state = TARGET_RESET;
630
631 /* registers are now invalid */
632 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
633
634 while (timeout < 100) {
635 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
636 if (retval == ERROR_OK) {
637 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
638 &cortex_m->nvic_dfsr);
639 if (retval != ERROR_OK)
640 return retval;
641 if ((dcb_dhcsr & S_HALT)
642 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
643 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
644 "DFSR 0x%08x",
645 (unsigned) dcb_dhcsr,
646 (unsigned) cortex_m->nvic_dfsr);
647 cortex_m_poll(target);
648 /* FIXME restore user's vector catch config */
649 return ERROR_OK;
650 } else
651 LOG_DEBUG("waiting for system reset-halt, "
652 "DHCSR 0x%08x, %d ms",
653 (unsigned) dcb_dhcsr, timeout);
654 }
655 timeout++;
656 alive_sleep(1);
657 }
658
659 return ERROR_OK;
660 }
661
662 void cortex_m_enable_breakpoints(struct target *target)
663 {
664 struct breakpoint *breakpoint = target->breakpoints;
665
666 /* set any pending breakpoints */
667 while (breakpoint) {
668 if (!breakpoint->set)
669 cortex_m_set_breakpoint(target, breakpoint);
670 breakpoint = breakpoint->next;
671 }
672 }
673
674 static int cortex_m_resume(struct target *target, int current,
675 target_addr_t address, int handle_breakpoints, int debug_execution)
676 {
677 struct armv7m_common *armv7m = target_to_armv7m(target);
678 struct breakpoint *breakpoint = NULL;
679 uint32_t resume_pc;
680 struct reg *r;
681
682 if (target->state != TARGET_HALTED) {
683 LOG_WARNING("target not halted");
684 return ERROR_TARGET_NOT_HALTED;
685 }
686
687 if (!debug_execution) {
688 target_free_all_working_areas(target);
689 cortex_m_enable_breakpoints(target);
690 cortex_m_enable_watchpoints(target);
691 }
692
693 if (debug_execution) {
694 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
695
696 /* Disable interrupts */
697 /* We disable interrupts in the PRIMASK register instead of
698 * masking with C_MASKINTS. This is probably the same issue
699 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
700 * in parallel with disabled interrupts can cause local faults
701 * to not be taken.
702 *
703 * REVISIT this clearly breaks non-debug execution, since the
704 * PRIMASK register state isn't saved/restored... workaround
705 * by never resuming app code after debug execution.
706 */
707 buf_set_u32(r->value, 0, 1, 1);
708 r->dirty = true;
709 r->valid = true;
710
711 /* Make sure we are in Thumb mode */
712 r = armv7m->arm.cpsr;
713 buf_set_u32(r->value, 24, 1, 1);
714 r->dirty = true;
715 r->valid = true;
716 }
717
718 /* current = 1: continue on current pc, otherwise continue at <address> */
719 r = armv7m->arm.pc;
720 if (!current) {
721 buf_set_u32(r->value, 0, 32, address);
722 r->dirty = true;
723 r->valid = true;
724 }
725
726 /* if we halted last time due to a bkpt instruction
727 * then we have to manually step over it, otherwise
728 * the core will break again */
729
730 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
731 && !debug_execution)
732 armv7m_maybe_skip_bkpt_inst(target, NULL);
733
734 resume_pc = buf_get_u32(r->value, 0, 32);
735
736 armv7m_restore_context(target);
737
738 /* the front-end may request us not to handle breakpoints */
739 if (handle_breakpoints) {
740 /* Single step past breakpoint at current address */
741 breakpoint = breakpoint_find(target, resume_pc);
742 if (breakpoint) {
743 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
744 breakpoint->address,
745 breakpoint->unique_id);
746 cortex_m_unset_breakpoint(target, breakpoint);
747 cortex_m_single_step_core(target);
748 cortex_m_set_breakpoint(target, breakpoint);
749 }
750 }
751
752 /* Restart core */
753 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
754
755 target->debug_reason = DBG_REASON_NOTHALTED;
756
757 /* registers are now invalid */
758 register_cache_invalidate(armv7m->arm.core_cache);
759
760 if (!debug_execution) {
761 target->state = TARGET_RUNNING;
762 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
763 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
764 } else {
765 target->state = TARGET_DEBUG_RUNNING;
766 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
767 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
768 }
769
770 return ERROR_OK;
771 }
772
773 /* int irqstepcount = 0; */
774 static int cortex_m_step(struct target *target, int current,
775 target_addr_t address, int handle_breakpoints)
776 {
777 struct cortex_m_common *cortex_m = target_to_cm(target);
778 struct armv7m_common *armv7m = &cortex_m->armv7m;
779 struct breakpoint *breakpoint = NULL;
780 struct reg *pc = armv7m->arm.pc;
781 bool bkpt_inst_found = false;
782 int retval;
783 bool isr_timed_out = false;
784
785 if (target->state != TARGET_HALTED) {
786 LOG_WARNING("target not halted");
787 return ERROR_TARGET_NOT_HALTED;
788 }
789
790 /* current = 1: continue on current pc, otherwise continue at <address> */
791 if (!current)
792 buf_set_u32(pc->value, 0, 32, address);
793
794 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
795
796 /* the front-end may request us not to handle breakpoints */
797 if (handle_breakpoints) {
798 breakpoint = breakpoint_find(target, pc_value);
799 if (breakpoint)
800 cortex_m_unset_breakpoint(target, breakpoint);
801 }
802
803 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
804
805 target->debug_reason = DBG_REASON_SINGLESTEP;
806
807 armv7m_restore_context(target);
808
809 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
810
811 /* if no bkpt instruction is found at pc then we can perform
812 * a normal step, otherwise we have to manually step over the bkpt
813 * instruction - as such simulate a step */
814 if (bkpt_inst_found == false) {
815 /* Automatic ISR masking mode off: Just step over the next instruction */
816 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
817 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
818 else {
819 /* Process interrupts during stepping in a way they don't interfere
820 * debugging.
821 *
822 * Principle:
823 *
824 * Set a temporary break point at the current pc and let the core run
825 * with interrupts enabled. Pending interrupts get served and we run
826 * into the breakpoint again afterwards. Then we step over the next
827 * instruction with interrupts disabled.
828 *
829 * If the pending interrupts don't complete within time, we leave the
830 * core running. This may happen if the interrupts trigger faster
831 * than the core can process them or the handler doesn't return.
832 *
833 * If no more breakpoints are available we simply do a step with
834 * interrupts enabled.
835 *
836 */
837
838 /* 2012-09-29 ph
839 *
840 * If a break point is already set on the lower half word then a break point on
841 * the upper half word will not break again when the core is restarted. So we
842 * just step over the instruction with interrupts disabled.
843 *
844 * The documentation has no information about this, it was found by observation
845 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
846 * suffer from this problem.
847 *
848 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
849 * address has it always cleared. The former is done to indicate thumb mode
850 * to gdb.
851 *
852 */
853 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
854 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
855 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
856 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
857 /* Re-enable interrupts */
858 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
859 }
860 else {
861
862 /* Set a temporary break point */
863 if (breakpoint)
864 retval = cortex_m_set_breakpoint(target, breakpoint);
865 else
866 retval = breakpoint_add(target, pc_value, 2, BKPT_HARD);
867 bool tmp_bp_set = (retval == ERROR_OK);
868
869 /* No more breakpoints left, just do a step */
870 if (!tmp_bp_set)
871 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
872 else {
873 /* Start the core */
874 LOG_DEBUG("Starting core to serve pending interrupts");
875 int64_t t_start = timeval_ms();
876 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
877
878 /* Wait for pending handlers to complete or timeout */
879 do {
880 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
881 DCB_DHCSR,
882 &cortex_m->dcb_dhcsr);
883 if (retval != ERROR_OK) {
884 target->state = TARGET_UNKNOWN;
885 return retval;
886 }
887 isr_timed_out = ((timeval_ms() - t_start) > 500);
888 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
889
890 /* only remove breakpoint if we created it */
891 if (breakpoint)
892 cortex_m_unset_breakpoint(target, breakpoint);
893 else {
894 /* Remove the temporary breakpoint */
895 breakpoint_remove(target, pc_value);
896 }
897
898 if (isr_timed_out) {
899 LOG_DEBUG("Interrupt handlers didn't complete within time, "
900 "leaving target running");
901 } else {
902 /* Step over next instruction with interrupts disabled */
903 cortex_m_write_debug_halt_mask(target,
904 C_HALT | C_MASKINTS,
905 0);
906 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
907 /* Re-enable interrupts */
908 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
909 }
910 }
911 }
912 }
913 }
914
915 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
916 if (retval != ERROR_OK)
917 return retval;
918
919 /* registers are now invalid */
920 register_cache_invalidate(armv7m->arm.core_cache);
921
922 if (breakpoint)
923 cortex_m_set_breakpoint(target, breakpoint);
924
925 if (isr_timed_out) {
926 /* Leave the core running. The user has to stop execution manually. */
927 target->debug_reason = DBG_REASON_NOTHALTED;
928 target->state = TARGET_RUNNING;
929 return ERROR_OK;
930 }
931
932 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
933 " nvic_icsr = 0x%" PRIx32,
934 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
935
936 retval = cortex_m_debug_entry(target);
937 if (retval != ERROR_OK)
938 return retval;
939 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
940
941 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
942 " nvic_icsr = 0x%" PRIx32,
943 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
944
945 return ERROR_OK;
946 }
947
948 static int cortex_m_assert_reset(struct target *target)
949 {
950 struct cortex_m_common *cortex_m = target_to_cm(target);
951 struct armv7m_common *armv7m = &cortex_m->armv7m;
952 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
953
954 LOG_DEBUG("target->state: %s",
955 target_state_name(target));
956
957 enum reset_types jtag_reset_config = jtag_get_reset_config();
958
959 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
960 /* allow scripts to override the reset event */
961
962 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
963 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
964 target->state = TARGET_RESET;
965
966 return ERROR_OK;
967 }
968
969 /* some cores support connecting while srst is asserted
970 * use that mode is it has been configured */
971
972 bool srst_asserted = false;
973
974 if (!target_was_examined(target)) {
975 if (jtag_reset_config & RESET_HAS_SRST) {
976 adapter_assert_reset();
977 if (target->reset_halt)
978 LOG_ERROR("Target not examined, will not halt after reset!");
979 return ERROR_OK;
980 } else {
981 LOG_ERROR("Target not examined, reset NOT asserted!");
982 return ERROR_FAIL;
983 }
984 }
985
986 if ((jtag_reset_config & RESET_HAS_SRST) &&
987 (jtag_reset_config & RESET_SRST_NO_GATING)) {
988 adapter_assert_reset();
989 srst_asserted = true;
990 }
991
992 /* Enable debug requests */
993 int retval;
994 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
995 /* Store important errors instead of failing and proceed to reset assert */
996
997 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
998 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
999
1000 /* If the processor is sleeping in a WFI or WFE instruction, the
1001 * C_HALT bit must be asserted to regain control */
1002 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1003 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1004
1005 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1006 /* Ignore less important errors */
1007
1008 if (!target->reset_halt) {
1009 /* Set/Clear C_MASKINTS in a separate operation */
1010 if (cortex_m->dcb_dhcsr & C_MASKINTS)
1011 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
1012
1013 /* clear any debug flags before resuming */
1014 cortex_m_clear_halt(target);
1015
1016 /* clear C_HALT in dhcsr reg */
1017 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1018 } else {
1019 /* Halt in debug on reset; endreset_event() restores DEMCR.
1020 *
1021 * REVISIT catching BUSERR presumably helps to defend against
1022 * bad vector table entries. Should this include MMERR or
1023 * other flags too?
1024 */
1025 int retval2;
1026 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1027 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1028 if (retval != ERROR_OK || retval2 != ERROR_OK)
1029 LOG_INFO("AP write error, reset will not halt");
1030 }
1031
1032 if (jtag_reset_config & RESET_HAS_SRST) {
1033 /* default to asserting srst */
1034 if (!srst_asserted)
1035 adapter_assert_reset();
1036
1037 /* srst is asserted, ignore AP access errors */
1038 retval = ERROR_OK;
1039 } else {
1040 /* Use a standard Cortex-M3 software reset mechanism.
1041 * We default to using VECRESET as it is supported on all current cores.
1042 * This has the disadvantage of not resetting the peripherals, so a
1043 * reset-init event handler is needed to perform any peripheral resets.
1044 */
1045 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1046 ? "SYSRESETREQ" : "VECTRESET");
1047
1048 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1049 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1050 "handler to reset any peripherals or configure hardware srst support.");
1051 }
1052
1053 int retval3;
1054 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1055 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1056 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1057 if (retval3 != ERROR_OK)
1058 LOG_DEBUG("Ignoring AP write error right after reset");
1059
1060 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1061 if (retval3 != ERROR_OK)
1062 LOG_ERROR("DP initialisation failed");
1063
1064 else {
1065 /* I do not know why this is necessary, but it
1066 * fixes strange effects (step/resume cause NMI
1067 * after reset) on LM3S6918 -- Michael Schwingen
1068 */
1069 uint32_t tmp;
1070 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1071 }
1072 }
1073
1074 target->state = TARGET_RESET;
1075 jtag_add_sleep(50000);
1076
1077 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1078
1079 /* now return stored error code if any */
1080 if (retval != ERROR_OK)
1081 return retval;
1082
1083 if (target->reset_halt) {
1084 retval = target_halt(target);
1085 if (retval != ERROR_OK)
1086 return retval;
1087 }
1088
1089 return ERROR_OK;
1090 }
1091
1092 static int cortex_m_deassert_reset(struct target *target)
1093 {
1094 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1095
1096 LOG_DEBUG("target->state: %s",
1097 target_state_name(target));
1098
1099 /* deassert reset lines */
1100 adapter_deassert_reset();
1101
1102 enum reset_types jtag_reset_config = jtag_get_reset_config();
1103
1104 if ((jtag_reset_config & RESET_HAS_SRST) &&
1105 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1106 target_was_examined(target)) {
1107 int retval = dap_dp_init(armv7m->debug_ap->dap);
1108 if (retval != ERROR_OK) {
1109 LOG_ERROR("DP initialisation failed");
1110 return retval;
1111 }
1112 }
1113
1114 return ERROR_OK;
1115 }
1116
1117 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1118 {
1119 int retval;
1120 int fp_num = 0;
1121 struct cortex_m_common *cortex_m = target_to_cm(target);
1122 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1123
1124 if (breakpoint->set) {
1125 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1126 return ERROR_OK;
1127 }
1128
1129 if (breakpoint->type == BKPT_HARD) {
1130 uint32_t fpcr_value;
1131 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1132 fp_num++;
1133 if (fp_num >= cortex_m->fp_num_code) {
1134 LOG_ERROR("Can not find free FPB Comparator!");
1135 return ERROR_FAIL;
1136 }
1137 breakpoint->set = fp_num + 1;
1138 fpcr_value = breakpoint->address | 1;
1139 if (cortex_m->fp_rev == 0) {
1140 uint32_t hilo;
1141 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1142 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1143 } else if (cortex_m->fp_rev > 1) {
1144 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1145 return ERROR_FAIL;
1146 }
1147 comparator_list[fp_num].used = 1;
1148 comparator_list[fp_num].fpcr_value = fpcr_value;
1149 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1150 comparator_list[fp_num].fpcr_value);
1151 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1152 fp_num,
1153 comparator_list[fp_num].fpcr_value);
1154 if (!cortex_m->fpb_enabled) {
1155 LOG_DEBUG("FPB wasn't enabled, do it now");
1156 retval = cortex_m_enable_fpb(target);
1157 if (retval != ERROR_OK) {
1158 LOG_ERROR("Failed to enable the FPB");
1159 return retval;
1160 }
1161
1162 cortex_m->fpb_enabled = 1;
1163 }
1164 } else if (breakpoint->type == BKPT_SOFT) {
1165 uint8_t code[4];
1166
1167 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1168 * semihosting; don't use that. Otherwise the BKPT
1169 * parameter is arbitrary.
1170 */
1171 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1172 retval = target_read_memory(target,
1173 breakpoint->address & 0xFFFFFFFE,
1174 breakpoint->length, 1,
1175 breakpoint->orig_instr);
1176 if (retval != ERROR_OK)
1177 return retval;
1178 retval = target_write_memory(target,
1179 breakpoint->address & 0xFFFFFFFE,
1180 breakpoint->length, 1,
1181 code);
1182 if (retval != ERROR_OK)
1183 return retval;
1184 breakpoint->set = true;
1185 }
1186
1187 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1188 breakpoint->unique_id,
1189 (int)(breakpoint->type),
1190 breakpoint->address,
1191 breakpoint->length,
1192 breakpoint->set);
1193
1194 return ERROR_OK;
1195 }
1196
1197 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1198 {
1199 int retval;
1200 struct cortex_m_common *cortex_m = target_to_cm(target);
1201 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1202
1203 if (!breakpoint->set) {
1204 LOG_WARNING("breakpoint not set");
1205 return ERROR_OK;
1206 }
1207
1208 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1209 breakpoint->unique_id,
1210 (int)(breakpoint->type),
1211 breakpoint->address,
1212 breakpoint->length,
1213 breakpoint->set);
1214
1215 if (breakpoint->type == BKPT_HARD) {
1216 int fp_num = breakpoint->set - 1;
1217 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1218 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1219 return ERROR_OK;
1220 }
1221 comparator_list[fp_num].used = 0;
1222 comparator_list[fp_num].fpcr_value = 0;
1223 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1224 comparator_list[fp_num].fpcr_value);
1225 } else {
1226 /* restore original instruction (kept in target endianness) */
1227 if (breakpoint->length == 4) {
1228 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1229 breakpoint->orig_instr);
1230 if (retval != ERROR_OK)
1231 return retval;
1232 } else {
1233 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1234 breakpoint->orig_instr);
1235 if (retval != ERROR_OK)
1236 return retval;
1237 }
1238 }
1239 breakpoint->set = false;
1240
1241 return ERROR_OK;
1242 }
1243
1244 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1245 {
1246 struct cortex_m_common *cortex_m = target_to_cm(target);
1247
1248 if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
1249 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1250 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1251 }
1252
1253 if (breakpoint->length == 3) {
1254 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1255 breakpoint->length = 2;
1256 }
1257
1258 if ((breakpoint->length != 2)) {
1259 LOG_INFO("only breakpoints of two bytes length supported");
1260 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1261 }
1262
1263 if (breakpoint->type == BKPT_HARD)
1264 cortex_m->fp_code_available--;
1265
1266 return cortex_m_set_breakpoint(target, breakpoint);
1267 }
1268
1269 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1270 {
1271 struct cortex_m_common *cortex_m = target_to_cm(target);
1272
1273 /* REVISIT why check? FBP can be updated with core running ... */
1274 if (target->state != TARGET_HALTED) {
1275 LOG_WARNING("target not halted");
1276 return ERROR_TARGET_NOT_HALTED;
1277 }
1278
1279 if (breakpoint->set)
1280 cortex_m_unset_breakpoint(target, breakpoint);
1281
1282 if (breakpoint->type == BKPT_HARD)
1283 cortex_m->fp_code_available++;
1284
1285 return ERROR_OK;
1286 }
1287
1288 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1289 {
1290 int dwt_num = 0;
1291 uint32_t mask, temp;
1292 struct cortex_m_common *cortex_m = target_to_cm(target);
1293
1294 /* watchpoint params were validated earlier */
1295 mask = 0;
1296 temp = watchpoint->length;
1297 while (temp) {
1298 temp >>= 1;
1299 mask++;
1300 }
1301 mask--;
1302
1303 /* REVISIT Don't fully trust these "not used" records ... users
1304 * may set up breakpoints by hand, e.g. dual-address data value
1305 * watchpoint using comparator #1; comparator #0 matching cycle
1306 * count; send data trace info through ITM and TPIU; etc
1307 */
1308 struct cortex_m_dwt_comparator *comparator;
1309
1310 for (comparator = cortex_m->dwt_comparator_list;
1311 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1312 comparator++, dwt_num++)
1313 continue;
1314 if (dwt_num >= cortex_m->dwt_num_comp) {
1315 LOG_ERROR("Can not find free DWT Comparator");
1316 return ERROR_FAIL;
1317 }
1318 comparator->used = 1;
1319 watchpoint->set = dwt_num + 1;
1320
1321 comparator->comp = watchpoint->address;
1322 target_write_u32(target, comparator->dwt_comparator_address + 0,
1323 comparator->comp);
1324
1325 comparator->mask = mask;
1326 target_write_u32(target, comparator->dwt_comparator_address + 4,
1327 comparator->mask);
1328
1329 switch (watchpoint->rw) {
1330 case WPT_READ:
1331 comparator->function = 5;
1332 break;
1333 case WPT_WRITE:
1334 comparator->function = 6;
1335 break;
1336 case WPT_ACCESS:
1337 comparator->function = 7;
1338 break;
1339 }
1340 target_write_u32(target, comparator->dwt_comparator_address + 8,
1341 comparator->function);
1342
1343 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1344 watchpoint->unique_id, dwt_num,
1345 (unsigned) comparator->comp,
1346 (unsigned) comparator->mask,
1347 (unsigned) comparator->function);
1348 return ERROR_OK;
1349 }
1350
1351 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1352 {
1353 struct cortex_m_common *cortex_m = target_to_cm(target);
1354 struct cortex_m_dwt_comparator *comparator;
1355 int dwt_num;
1356
1357 if (!watchpoint->set) {
1358 LOG_WARNING("watchpoint (wpid: %d) not set",
1359 watchpoint->unique_id);
1360 return ERROR_OK;
1361 }
1362
1363 dwt_num = watchpoint->set - 1;
1364
1365 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1366 watchpoint->unique_id, dwt_num,
1367 (unsigned) watchpoint->address);
1368
1369 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1370 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1371 return ERROR_OK;
1372 }
1373
1374 comparator = cortex_m->dwt_comparator_list + dwt_num;
1375 comparator->used = 0;
1376 comparator->function = 0;
1377 target_write_u32(target, comparator->dwt_comparator_address + 8,
1378 comparator->function);
1379
1380 watchpoint->set = false;
1381
1382 return ERROR_OK;
1383 }
1384
1385 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1386 {
1387 struct cortex_m_common *cortex_m = target_to_cm(target);
1388
1389 if (cortex_m->dwt_comp_available < 1) {
1390 LOG_DEBUG("no comparators?");
1391 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1392 }
1393
1394 /* hardware doesn't support data value masking */
1395 if (watchpoint->mask != ~(uint32_t)0) {
1396 LOG_DEBUG("watchpoint value masks not supported");
1397 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1398 }
1399
1400 /* hardware allows address masks of up to 32K */
1401 unsigned mask;
1402
1403 for (mask = 0; mask < 16; mask++) {
1404 if ((1u << mask) == watchpoint->length)
1405 break;
1406 }
1407 if (mask == 16) {
1408 LOG_DEBUG("unsupported watchpoint length");
1409 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1410 }
1411 if (watchpoint->address & ((1 << mask) - 1)) {
1412 LOG_DEBUG("watchpoint address is unaligned");
1413 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1414 }
1415
1416 /* Caller doesn't seem to be able to describe watching for data
1417 * values of zero; that flags "no value".
1418 *
1419 * REVISIT This DWT may well be able to watch for specific data
1420 * values. Requires comparator #1 to set DATAVMATCH and match
1421 * the data, and another comparator (DATAVADDR0) matching addr.
1422 */
1423 if (watchpoint->value) {
1424 LOG_DEBUG("data value watchpoint not YET supported");
1425 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1426 }
1427
1428 cortex_m->dwt_comp_available--;
1429 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1430
1431 return ERROR_OK;
1432 }
1433
1434 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1435 {
1436 struct cortex_m_common *cortex_m = target_to_cm(target);
1437
1438 /* REVISIT why check? DWT can be updated with core running ... */
1439 if (target->state != TARGET_HALTED) {
1440 LOG_WARNING("target not halted");
1441 return ERROR_TARGET_NOT_HALTED;
1442 }
1443
1444 if (watchpoint->set)
1445 cortex_m_unset_watchpoint(target, watchpoint);
1446
1447 cortex_m->dwt_comp_available++;
1448 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1449
1450 return ERROR_OK;
1451 }
1452
1453 void cortex_m_enable_watchpoints(struct target *target)
1454 {
1455 struct watchpoint *watchpoint = target->watchpoints;
1456
1457 /* set any pending watchpoints */
1458 while (watchpoint) {
1459 if (!watchpoint->set)
1460 cortex_m_set_watchpoint(target, watchpoint);
1461 watchpoint = watchpoint->next;
1462 }
1463 }
1464
1465 static int cortex_m_load_core_reg_u32(struct target *target,
1466 uint32_t num, uint32_t *value)
1467 {
1468 int retval;
1469
1470 /* NOTE: we "know" here that the register identifiers used
1471 * in the v7m header match the Cortex-M3 Debug Core Register
1472 * Selector values for R0..R15, xPSR, MSP, and PSP.
1473 */
1474 switch (num) {
1475 case 0 ... 18:
1476 /* read a normal core register */
1477 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1478
1479 if (retval != ERROR_OK) {
1480 LOG_ERROR("JTAG failure %i", retval);
1481 return ERROR_JTAG_DEVICE_ERROR;
1482 }
1483 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1484 break;
1485
1486 case ARMV7M_FPSCR:
1487 /* Floating-point Status and Registers */
1488 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1489 if (retval != ERROR_OK)
1490 return retval;
1491 retval = target_read_u32(target, DCB_DCRDR, value);
1492 if (retval != ERROR_OK)
1493 return retval;
1494 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1495 break;
1496
1497 case ARMV7M_S0 ... ARMV7M_S31:
1498 /* Floating-point Status and Registers */
1499 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1500 if (retval != ERROR_OK)
1501 return retval;
1502 retval = target_read_u32(target, DCB_DCRDR, value);
1503 if (retval != ERROR_OK)
1504 return retval;
1505 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1506 (int)(num - ARMV7M_S0), *value);
1507 break;
1508
1509 case ARMV7M_PRIMASK:
1510 case ARMV7M_BASEPRI:
1511 case ARMV7M_FAULTMASK:
1512 case ARMV7M_CONTROL:
1513 /* Cortex-M3 packages these four registers as bitfields
1514 * in one Debug Core register. So say r0 and r2 docs;
1515 * it was removed from r1 docs, but still works.
1516 */
1517 cortexm_dap_read_coreregister_u32(target, value, 20);
1518
1519 switch (num) {
1520 case ARMV7M_PRIMASK:
1521 *value = buf_get_u32((uint8_t *)value, 0, 1);
1522 break;
1523
1524 case ARMV7M_BASEPRI:
1525 *value = buf_get_u32((uint8_t *)value, 8, 8);
1526 break;
1527
1528 case ARMV7M_FAULTMASK:
1529 *value = buf_get_u32((uint8_t *)value, 16, 1);
1530 break;
1531
1532 case ARMV7M_CONTROL:
1533 *value = buf_get_u32((uint8_t *)value, 24, 2);
1534 break;
1535 }
1536
1537 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1538 break;
1539
1540 default:
1541 return ERROR_COMMAND_SYNTAX_ERROR;
1542 }
1543
1544 return ERROR_OK;
1545 }
1546
1547 static int cortex_m_store_core_reg_u32(struct target *target,
1548 uint32_t num, uint32_t value)
1549 {
1550 int retval;
1551 uint32_t reg;
1552 struct armv7m_common *armv7m = target_to_armv7m(target);
1553
1554 /* NOTE: we "know" here that the register identifiers used
1555 * in the v7m header match the Cortex-M3 Debug Core Register
1556 * Selector values for R0..R15, xPSR, MSP, and PSP.
1557 */
1558 switch (num) {
1559 case 0 ... 18:
1560 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1561 if (retval != ERROR_OK) {
1562 struct reg *r;
1563
1564 LOG_ERROR("JTAG failure");
1565 r = armv7m->arm.core_cache->reg_list + num;
1566 r->dirty = r->valid;
1567 return ERROR_JTAG_DEVICE_ERROR;
1568 }
1569 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1570 break;
1571
1572 case ARMV7M_FPSCR:
1573 /* Floating-point Status and Registers */
1574 retval = target_write_u32(target, DCB_DCRDR, value);
1575 if (retval != ERROR_OK)
1576 return retval;
1577 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1578 if (retval != ERROR_OK)
1579 return retval;
1580 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1581 break;
1582
1583 case ARMV7M_S0 ... ARMV7M_S31:
1584 /* Floating-point Status and Registers */
1585 retval = target_write_u32(target, DCB_DCRDR, value);
1586 if (retval != ERROR_OK)
1587 return retval;
1588 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1589 if (retval != ERROR_OK)
1590 return retval;
1591 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1592 (int)(num - ARMV7M_S0), value);
1593 break;
1594
1595 case ARMV7M_PRIMASK:
1596 case ARMV7M_BASEPRI:
1597 case ARMV7M_FAULTMASK:
1598 case ARMV7M_CONTROL:
1599 /* Cortex-M3 packages these four registers as bitfields
1600 * in one Debug Core register. So say r0 and r2 docs;
1601 * it was removed from r1 docs, but still works.
1602 */
1603 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1604
1605 switch (num) {
1606 case ARMV7M_PRIMASK:
1607 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1608 break;
1609
1610 case ARMV7M_BASEPRI:
1611 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1612 break;
1613
1614 case ARMV7M_FAULTMASK:
1615 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1616 break;
1617
1618 case ARMV7M_CONTROL:
1619 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1620 break;
1621 }
1622
1623 cortexm_dap_write_coreregister_u32(target, reg, 20);
1624
1625 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1626 break;
1627
1628 default:
1629 return ERROR_COMMAND_SYNTAX_ERROR;
1630 }
1631
1632 return ERROR_OK;
1633 }
1634
1635 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1636 uint32_t size, uint32_t count, uint8_t *buffer)
1637 {
1638 struct armv7m_common *armv7m = target_to_armv7m(target);
1639
1640 if (armv7m->arm.is_armv6m) {
1641 /* armv6m does not handle unaligned memory access */
1642 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1643 return ERROR_TARGET_UNALIGNED_ACCESS;
1644 }
1645
1646 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1647 }
1648
1649 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1650 uint32_t size, uint32_t count, const uint8_t *buffer)
1651 {
1652 struct armv7m_common *armv7m = target_to_armv7m(target);
1653
1654 if (armv7m->arm.is_armv6m) {
1655 /* armv6m does not handle unaligned memory access */
1656 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1657 return ERROR_TARGET_UNALIGNED_ACCESS;
1658 }
1659
1660 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1661 }
1662
1663 static int cortex_m_init_target(struct command_context *cmd_ctx,
1664 struct target *target)
1665 {
1666 armv7m_build_reg_cache(target);
1667 arm_semihosting_init(target);
1668 return ERROR_OK;
1669 }
1670
1671 void cortex_m_deinit_target(struct target *target)
1672 {
1673 struct cortex_m_common *cortex_m = target_to_cm(target);
1674
1675 free(cortex_m->fp_comparator_list);
1676
1677 cortex_m_dwt_free(target);
1678 armv7m_free_reg_cache(target);
1679
1680 free(target->private_config);
1681 free(cortex_m);
1682 }
1683
1684 int cortex_m_profiling(struct target *target, uint32_t *samples,
1685 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1686 {
1687 struct timeval timeout, now;
1688 struct armv7m_common *armv7m = target_to_armv7m(target);
1689 uint32_t reg_value;
1690 bool use_pcsr = false;
1691 int retval = ERROR_OK;
1692 struct reg *reg;
1693
1694 gettimeofday(&timeout, NULL);
1695 timeval_add_time(&timeout, seconds, 0);
1696
1697 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1698 if (retval != ERROR_OK) {
1699 LOG_ERROR("Error while reading PCSR");
1700 return retval;
1701 }
1702
1703 if (reg_value != 0) {
1704 use_pcsr = true;
1705 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1706 } else {
1707 LOG_INFO("Starting profiling. Halting and resuming the"
1708 " target as often as we can...");
1709 reg = register_get_by_name(target->reg_cache, "pc", 1);
1710 }
1711
1712 /* Make sure the target is running */
1713 target_poll(target);
1714 if (target->state == TARGET_HALTED)
1715 retval = target_resume(target, 1, 0, 0, 0);
1716
1717 if (retval != ERROR_OK) {
1718 LOG_ERROR("Error while resuming target");
1719 return retval;
1720 }
1721
1722 uint32_t sample_count = 0;
1723
1724 for (;;) {
1725 if (use_pcsr) {
1726 if (armv7m && armv7m->debug_ap) {
1727 uint32_t read_count = max_num_samples - sample_count;
1728 if (read_count > 1024)
1729 read_count = 1024;
1730
1731 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1732 (void *)&samples[sample_count],
1733 4, read_count, DWT_PCSR);
1734 sample_count += read_count;
1735 } else {
1736 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1737 }
1738 } else {
1739 target_poll(target);
1740 if (target->state == TARGET_HALTED) {
1741 reg_value = buf_get_u32(reg->value, 0, 32);
1742 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1743 retval = target_resume(target, 1, 0, 0, 0);
1744 samples[sample_count++] = reg_value;
1745 target_poll(target);
1746 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1747 } else if (target->state == TARGET_RUNNING) {
1748 /* We want to quickly sample the PC. */
1749 retval = target_halt(target);
1750 } else {
1751 LOG_INFO("Target not halted or running");
1752 retval = ERROR_OK;
1753 break;
1754 }
1755 }
1756
1757 if (retval != ERROR_OK) {
1758 LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1759 return retval;
1760 }
1761
1762
1763 gettimeofday(&now, NULL);
1764 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1765 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1766 break;
1767 }
1768 }
1769
1770 *num_samples = sample_count;
1771 return retval;
1772 }
1773
1774
1775 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1776 * on r/w if the core is not running, and clear on resume or reset ... or
1777 * at least, in a post_restore_context() method.
1778 */
1779
1780 struct dwt_reg_state {
1781 struct target *target;
1782 uint32_t addr;
1783 uint8_t value[4]; /* scratch/cache */
1784 };
1785
1786 static int cortex_m_dwt_get_reg(struct reg *reg)
1787 {
1788 struct dwt_reg_state *state = reg->arch_info;
1789
1790 uint32_t tmp;
1791 int retval = target_read_u32(state->target, state->addr, &tmp);
1792 if (retval != ERROR_OK)
1793 return retval;
1794
1795 buf_set_u32(state->value, 0, 32, tmp);
1796 return ERROR_OK;
1797 }
1798
1799 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1800 {
1801 struct dwt_reg_state *state = reg->arch_info;
1802
1803 return target_write_u32(state->target, state->addr,
1804 buf_get_u32(buf, 0, reg->size));
1805 }
1806
1807 struct dwt_reg {
1808 uint32_t addr;
1809 const char *name;
1810 unsigned size;
1811 };
1812
1813 static const struct dwt_reg dwt_base_regs[] = {
1814 { DWT_CTRL, "dwt_ctrl", 32, },
1815 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1816 * increments while the core is asleep.
1817 */
1818 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1819 /* plus some 8 bit counters, useful for profiling with TPIU */
1820 };
1821
1822 static const struct dwt_reg dwt_comp[] = {
1823 #define DWT_COMPARATOR(i) \
1824 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1825 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1826 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1827 DWT_COMPARATOR(0),
1828 DWT_COMPARATOR(1),
1829 DWT_COMPARATOR(2),
1830 DWT_COMPARATOR(3),
1831 DWT_COMPARATOR(4),
1832 DWT_COMPARATOR(5),
1833 DWT_COMPARATOR(6),
1834 DWT_COMPARATOR(7),
1835 DWT_COMPARATOR(8),
1836 DWT_COMPARATOR(9),
1837 DWT_COMPARATOR(10),
1838 DWT_COMPARATOR(11),
1839 DWT_COMPARATOR(12),
1840 DWT_COMPARATOR(13),
1841 DWT_COMPARATOR(14),
1842 DWT_COMPARATOR(15),
1843 #undef DWT_COMPARATOR
1844 };
1845
1846 static const struct reg_arch_type dwt_reg_type = {
1847 .get = cortex_m_dwt_get_reg,
1848 .set = cortex_m_dwt_set_reg,
1849 };
1850
1851 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1852 {
1853 struct dwt_reg_state *state;
1854
1855 state = calloc(1, sizeof *state);
1856 if (!state)
1857 return;
1858 state->addr = d->addr;
1859 state->target = t;
1860
1861 r->name = d->name;
1862 r->size = d->size;
1863 r->value = state->value;
1864 r->arch_info = state;
1865 r->type = &dwt_reg_type;
1866 }
1867
1868 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1869 {
1870 uint32_t dwtcr;
1871 struct reg_cache *cache;
1872 struct cortex_m_dwt_comparator *comparator;
1873 int reg, i;
1874
1875 target_read_u32(target, DWT_CTRL, &dwtcr);
1876 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1877 if (!dwtcr) {
1878 LOG_DEBUG("no DWT");
1879 return;
1880 }
1881
1882 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1883 cm->dwt_comp_available = cm->dwt_num_comp;
1884 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1885 sizeof(struct cortex_m_dwt_comparator));
1886 if (!cm->dwt_comparator_list) {
1887 fail0:
1888 cm->dwt_num_comp = 0;
1889 LOG_ERROR("out of mem");
1890 return;
1891 }
1892
1893 cache = calloc(1, sizeof *cache);
1894 if (!cache) {
1895 fail1:
1896 free(cm->dwt_comparator_list);
1897 goto fail0;
1898 }
1899 cache->name = "Cortex-M DWT registers";
1900 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1901 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1902 if (!cache->reg_list) {
1903 free(cache);
1904 goto fail1;
1905 }
1906
1907 for (reg = 0; reg < 2; reg++)
1908 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1909 dwt_base_regs + reg);
1910
1911 comparator = cm->dwt_comparator_list;
1912 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1913 int j;
1914
1915 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1916 for (j = 0; j < 3; j++, reg++)
1917 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1918 dwt_comp + 3 * i + j);
1919
1920 /* make sure we clear any watchpoints enabled on the target */
1921 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1922 }
1923
1924 *register_get_last_cache_p(&target->reg_cache) = cache;
1925 cm->dwt_cache = cache;
1926
1927 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1928 dwtcr, cm->dwt_num_comp,
1929 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1930
1931 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1932 * implement single-address data value watchpoints ... so we
1933 * won't need to check it later, when asked to set one up.
1934 */
1935 }
1936
1937 static void cortex_m_dwt_free(struct target *target)
1938 {
1939 struct cortex_m_common *cm = target_to_cm(target);
1940 struct reg_cache *cache = cm->dwt_cache;
1941
1942 free(cm->dwt_comparator_list);
1943 cm->dwt_comparator_list = NULL;
1944 cm->dwt_num_comp = 0;
1945
1946 if (cache) {
1947 register_unlink_cache(&target->reg_cache, cache);
1948
1949 if (cache->reg_list) {
1950 for (size_t i = 0; i < cache->num_regs; i++)
1951 free(cache->reg_list[i].arch_info);
1952 free(cache->reg_list);
1953 }
1954 free(cache);
1955 }
1956 cm->dwt_cache = NULL;
1957 }
1958
1959 #define MVFR0 0xe000ef40
1960 #define MVFR1 0xe000ef44
1961
1962 #define MVFR0_DEFAULT_M4 0x10110021
1963 #define MVFR1_DEFAULT_M4 0x11000011
1964
1965 #define MVFR0_DEFAULT_M7_SP 0x10110021
1966 #define MVFR0_DEFAULT_M7_DP 0x10110221
1967 #define MVFR1_DEFAULT_M7_SP 0x11000011
1968 #define MVFR1_DEFAULT_M7_DP 0x12000011
1969
1970 int cortex_m_examine(struct target *target)
1971 {
1972 int retval;
1973 uint32_t cpuid, fpcr, mvfr0, mvfr1;
1974 int i;
1975 struct cortex_m_common *cortex_m = target_to_cm(target);
1976 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1977 struct armv7m_common *armv7m = target_to_armv7m(target);
1978
1979 /* stlink shares the examine handler but does not support
1980 * all its calls */
1981 if (!armv7m->stlink) {
1982 if (cortex_m->apsel < 0) {
1983 /* Search for the MEM-AP */
1984 retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
1985 if (retval != ERROR_OK) {
1986 LOG_ERROR("Could not find MEM-AP to control the core");
1987 return retval;
1988 }
1989 } else {
1990 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
1991 }
1992
1993 /* Leave (only) generic DAP stuff for debugport_init(); */
1994 armv7m->debug_ap->memaccess_tck = 8;
1995
1996 retval = mem_ap_init(armv7m->debug_ap);
1997 if (retval != ERROR_OK)
1998 return retval;
1999 }
2000
2001 if (!target_was_examined(target)) {
2002 target_set_examined(target);
2003
2004 /* Read from Device Identification Registers */
2005 retval = target_read_u32(target, CPUID, &cpuid);
2006 if (retval != ERROR_OK)
2007 return retval;
2008
2009 /* Get CPU Type */
2010 i = (cpuid >> 4) & 0xf;
2011
2012 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2013 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2014 if (i == 7) {
2015 uint8_t rev, patch;
2016 rev = (cpuid >> 20) & 0xf;
2017 patch = (cpuid >> 0) & 0xf;
2018 if ((rev == 0) && (patch < 2))
2019 LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
2020 }
2021 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2022
2023 if (i == 4) {
2024 target_read_u32(target, MVFR0, &mvfr0);
2025 target_read_u32(target, MVFR1, &mvfr1);
2026
2027 /* test for floating point feature on Cortex-M4 */
2028 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2029 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2030 armv7m->fp_feature = FPv4_SP;
2031 }
2032 } else if (i == 7) {
2033 target_read_u32(target, MVFR0, &mvfr0);
2034 target_read_u32(target, MVFR1, &mvfr1);
2035
2036 /* test for floating point features on Cortex-M7 */
2037 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2038 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2039 armv7m->fp_feature = FPv5_SP;
2040 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2041 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2042 armv7m->fp_feature = FPv5_DP;
2043 }
2044 } else if (i == 0) {
2045 /* Cortex-M0 does not support unaligned memory access */
2046 armv7m->arm.is_armv6m = true;
2047 }
2048
2049 if (armv7m->fp_feature == FP_NONE &&
2050 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2051 /* free unavailable FPU registers */
2052 size_t idx;
2053
2054 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2055 idx < armv7m->arm.core_cache->num_regs;
2056 idx++) {
2057 free(armv7m->arm.core_cache->reg_list[idx].value);
2058 free(armv7m->arm.core_cache->reg_list[idx].feature);
2059 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2060 }
2061 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2062 }
2063
2064 if (!armv7m->stlink) {
2065 if (i == 3 || i == 4)
2066 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2067 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2068 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2069 else if (i == 7)
2070 /* Cortex-M7 has only 1024 bytes autoincrement range */
2071 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2072 }
2073
2074 /* Configure trace modules */
2075 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2076 if (retval != ERROR_OK)
2077 return retval;
2078
2079 if (armv7m->trace_config.config_type != DISABLED) {
2080 armv7m_trace_tpiu_config(target);
2081 armv7m_trace_itm_config(target);
2082 }
2083
2084 /* NOTE: FPB and DWT are both optional. */
2085
2086 /* Setup FPB */
2087 target_read_u32(target, FP_CTRL, &fpcr);
2088 /* bits [14:12] and [7:4] */
2089 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2090 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2091 cortex_m->fp_code_available = cortex_m->fp_num_code;
2092 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2093 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2094 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2095 free(cortex_m->fp_comparator_list);
2096 cortex_m->fp_comparator_list = calloc(
2097 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2098 sizeof(struct cortex_m_fp_comparator));
2099 cortex_m->fpb_enabled = fpcr & 1;
2100 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2101 cortex_m->fp_comparator_list[i].type =
2102 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2103 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2104
2105 /* make sure we clear any breakpoints enabled on the target */
2106 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2107 }
2108 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2109 fpcr,
2110 cortex_m->fp_num_code,
2111 cortex_m->fp_num_lit);
2112
2113 /* Setup DWT */
2114 cortex_m_dwt_free(target);
2115 cortex_m_dwt_setup(cortex_m, target);
2116
2117 /* These hardware breakpoints only work for code in flash! */
2118 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2119 target_name(target),
2120 cortex_m->fp_num_code,
2121 cortex_m->dwt_num_comp);
2122 }
2123
2124 return ERROR_OK;
2125 }
2126
2127 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2128 {
2129 struct armv7m_common *armv7m = target_to_armv7m(target);
2130 uint16_t dcrdr;
2131 uint8_t buf[2];
2132 int retval;
2133
2134 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2135 if (retval != ERROR_OK)
2136 return retval;
2137
2138 dcrdr = target_buffer_get_u16(target, buf);
2139 *ctrl = (uint8_t)dcrdr;
2140 *value = (uint8_t)(dcrdr >> 8);
2141
2142 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2143
2144 /* write ack back to software dcc register
2145 * signify we have read data */
2146 if (dcrdr & (1 << 0)) {
2147 target_buffer_set_u16(target, buf, 0);
2148 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2149 if (retval != ERROR_OK)
2150 return retval;
2151 }
2152
2153 return ERROR_OK;
2154 }
2155
2156 static int cortex_m_target_request_data(struct target *target,
2157 uint32_t size, uint8_t *buffer)
2158 {
2159 uint8_t data;
2160 uint8_t ctrl;
2161 uint32_t i;
2162
2163 for (i = 0; i < (size * 4); i++) {
2164 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2165 if (retval != ERROR_OK)
2166 return retval;
2167 buffer[i] = data;
2168 }
2169
2170 return ERROR_OK;
2171 }
2172
2173 static int cortex_m_handle_target_request(void *priv)
2174 {
2175 struct target *target = priv;
2176 if (!target_was_examined(target))
2177 return ERROR_OK;
2178
2179 if (!target->dbg_msg_enabled)
2180 return ERROR_OK;
2181
2182 if (target->state == TARGET_RUNNING) {
2183 uint8_t data;
2184 uint8_t ctrl;
2185 int retval;
2186
2187 retval = cortex_m_dcc_read(target, &data, &ctrl);
2188 if (retval != ERROR_OK)
2189 return retval;
2190
2191 /* check if we have data */
2192 if (ctrl & (1 << 0)) {
2193 uint32_t request;
2194
2195 /* we assume target is quick enough */
2196 request = data;
2197 for (int i = 1; i <= 3; i++) {
2198 retval = cortex_m_dcc_read(target, &data, &ctrl);
2199 if (retval != ERROR_OK)
2200 return retval;
2201 request |= ((uint32_t)data << (i * 8));
2202 }
2203 target_request(target, request);
2204 }
2205 }
2206
2207 return ERROR_OK;
2208 }
2209
2210 static int cortex_m_init_arch_info(struct target *target,
2211 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2212 {
2213 struct armv7m_common *armv7m = &cortex_m->armv7m;
2214
2215 armv7m_init_arch_info(target, armv7m);
2216
2217 /* default reset mode is to use srst if fitted
2218 * if not it will use CORTEX_M3_RESET_VECTRESET */
2219 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2220
2221 armv7m->arm.dap = dap;
2222
2223 /* register arch-specific functions */
2224 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2225
2226 armv7m->post_debug_entry = NULL;
2227
2228 armv7m->pre_restore_context = NULL;
2229
2230 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2231 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2232
2233 target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
2234
2235 return ERROR_OK;
2236 }
2237
2238 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2239 {
2240 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2241 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2242 struct adiv5_private_config *pc;
2243
2244 pc = (struct adiv5_private_config *)target->private_config;
2245 if (adiv5_verify_config(pc) != ERROR_OK)
2246 return ERROR_FAIL;
2247
2248 cortex_m->apsel = pc->ap_num;
2249
2250 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2251
2252 return ERROR_OK;
2253 }
2254
2255 /*--------------------------------------------------------------------------*/
2256
2257 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2258 struct cortex_m_common *cm)
2259 {
2260 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2261 command_print(cmd_ctx, "target is not a Cortex-M");
2262 return ERROR_TARGET_INVALID;
2263 }
2264 return ERROR_OK;
2265 }
2266
2267 /*
2268 * Only stuff below this line should need to verify that its target
2269 * is a Cortex-M3. Everything else should have indirected through the
2270 * cortexm3_target structure, which is only used with CM3 targets.
2271 */
2272
2273 static const struct {
2274 char name[10];
2275 unsigned mask;
2276 } vec_ids[] = {
2277 { "hard_err", VC_HARDERR, },
2278 { "int_err", VC_INTERR, },
2279 { "bus_err", VC_BUSERR, },
2280 { "state_err", VC_STATERR, },
2281 { "chk_err", VC_CHKERR, },
2282 { "nocp_err", VC_NOCPERR, },
2283 { "mm_err", VC_MMERR, },
2284 { "reset", VC_CORERESET, },
2285 };
2286
2287 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2288 {
2289 struct target *target = get_current_target(CMD_CTX);
2290 struct cortex_m_common *cortex_m = target_to_cm(target);
2291 struct armv7m_common *armv7m = &cortex_m->armv7m;
2292 uint32_t demcr = 0;
2293 int retval;
2294
2295 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2296 if (retval != ERROR_OK)
2297 return retval;
2298
2299 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2300 if (retval != ERROR_OK)
2301 return retval;
2302
2303 if (CMD_ARGC > 0) {
2304 unsigned catch = 0;
2305
2306 if (CMD_ARGC == 1) {
2307 if (strcmp(CMD_ARGV[0], "all") == 0) {
2308 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2309 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2310 | VC_MMERR | VC_CORERESET;
2311 goto write;
2312 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2313 goto write;
2314 }
2315 while (CMD_ARGC-- > 0) {
2316 unsigned i;
2317 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2318 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2319 continue;
2320 catch |= vec_ids[i].mask;
2321 break;
2322 }
2323 if (i == ARRAY_SIZE(vec_ids)) {
2324 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2325 return ERROR_COMMAND_SYNTAX_ERROR;
2326 }
2327 }
2328 write:
2329 /* For now, armv7m->demcr only stores vector catch flags. */
2330 armv7m->demcr = catch;
2331
2332 demcr &= ~0xffff;
2333 demcr |= catch;
2334
2335 /* write, but don't assume it stuck (why not??) */
2336 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2337 if (retval != ERROR_OK)
2338 return retval;
2339 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2340 if (retval != ERROR_OK)
2341 return retval;
2342
2343 /* FIXME be sure to clear DEMCR on clean server shutdown.
2344 * Otherwise the vector catch hardware could fire when there's
2345 * no debugger hooked up, causing much confusion...
2346 */
2347 }
2348
2349 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2350 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2351 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2352 }
2353
2354 return ERROR_OK;
2355 }
2356
2357 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2358 {
2359 struct target *target = get_current_target(CMD_CTX);
2360 struct cortex_m_common *cortex_m = target_to_cm(target);
2361 int retval;
2362
2363 static const Jim_Nvp nvp_maskisr_modes[] = {
2364 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2365 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2366 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2367 { .name = NULL, .value = -1 },
2368 };
2369 const Jim_Nvp *n;
2370
2371
2372 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2373 if (retval != ERROR_OK)
2374 return retval;
2375
2376 if (target->state != TARGET_HALTED) {
2377 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2378 return ERROR_OK;
2379 }
2380
2381 if (CMD_ARGC > 0) {
2382 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2383 if (n->name == NULL)
2384 return ERROR_COMMAND_SYNTAX_ERROR;
2385 cortex_m->isrmasking_mode = n->value;
2386
2387
2388 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2389 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2390 else
2391 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2392 }
2393
2394 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2395 command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2396
2397 return ERROR_OK;
2398 }
2399
2400 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2401 {
2402 struct target *target = get_current_target(CMD_CTX);
2403 struct cortex_m_common *cortex_m = target_to_cm(target);
2404 int retval;
2405 char *reset_config;
2406
2407 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2408 if (retval != ERROR_OK)
2409 return retval;
2410
2411 if (CMD_ARGC > 0) {
2412 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2413 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2414 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2415 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2416 }
2417
2418 switch (cortex_m->soft_reset_config) {
2419 case CORTEX_M_RESET_SYSRESETREQ:
2420 reset_config = "sysresetreq";
2421 break;
2422
2423 case CORTEX_M_RESET_VECTRESET:
2424 reset_config = "vectreset";
2425 break;
2426
2427 default:
2428 reset_config = "unknown";
2429 break;
2430 }
2431
2432 command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2433
2434 return ERROR_OK;
2435 }
2436
2437 static const struct command_registration cortex_m_exec_command_handlers[] = {
2438 {
2439 .name = "maskisr",
2440 .handler = handle_cortex_m_mask_interrupts_command,
2441 .mode = COMMAND_EXEC,
2442 .help = "mask cortex_m interrupts",
2443 .usage = "['auto'|'on'|'off']",
2444 },
2445 {
2446 .name = "vector_catch",
2447 .handler = handle_cortex_m_vector_catch_command,
2448 .mode = COMMAND_EXEC,
2449 .help = "configure hardware vectors to trigger debug entry",
2450 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2451 },
2452 {
2453 .name = "reset_config",
2454 .handler = handle_cortex_m_reset_config_command,
2455 .mode = COMMAND_ANY,
2456 .help = "configure software reset handling",
2457 .usage = "['srst'|'sysresetreq'|'vectreset']",
2458 },
2459 COMMAND_REGISTRATION_DONE
2460 };
2461 static const struct command_registration cortex_m_command_handlers[] = {
2462 {
2463 .chain = armv7m_command_handlers,
2464 },
2465 {
2466 .chain = armv7m_trace_command_handlers,
2467 },
2468 {
2469 .name = "cortex_m",
2470 .mode = COMMAND_EXEC,
2471 .help = "Cortex-M command group",
2472 .usage = "",
2473 .chain = cortex_m_exec_command_handlers,
2474 },
2475 COMMAND_REGISTRATION_DONE
2476 };
2477
2478 struct target_type cortexm_target = {
2479 .name = "cortex_m",
2480 .deprecated_name = "cortex_m3",
2481
2482 .poll = cortex_m_poll,
2483 .arch_state = armv7m_arch_state,
2484
2485 .target_request_data = cortex_m_target_request_data,
2486
2487 .halt = cortex_m_halt,
2488 .resume = cortex_m_resume,
2489 .step = cortex_m_step,
2490
2491 .assert_reset = cortex_m_assert_reset,
2492 .deassert_reset = cortex_m_deassert_reset,
2493 .soft_reset_halt = cortex_m_soft_reset_halt,
2494
2495 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2496
2497 .read_memory = cortex_m_read_memory,
2498 .write_memory = cortex_m_write_memory,
2499 .checksum_memory = armv7m_checksum_memory,
2500 .blank_check_memory = armv7m_blank_check_memory,
2501
2502 .run_algorithm = armv7m_run_algorithm,
2503 .start_algorithm = armv7m_start_algorithm,
2504 .wait_algorithm = armv7m_wait_algorithm,
2505
2506 .add_breakpoint = cortex_m_add_breakpoint,
2507 .remove_breakpoint = cortex_m_remove_breakpoint,
2508 .add_watchpoint = cortex_m_add_watchpoint,
2509 .remove_watchpoint = cortex_m_remove_watchpoint,
2510
2511 .commands = cortex_m_command_handlers,
2512 .target_create = cortex_m_target_create,
2513 .target_jim_configure = adiv5_jim_configure,
2514 .init_target = cortex_m_init_target,
2515 .examine = cortex_m_examine,
2516 .deinit_target = cortex_m_deinit_target,
2517
2518 .profiling = cortex_m_profiling,
2519 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)