cortex_m: add detection of Cortex M35P and M55
[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortexm_dap_read_coreregister_u32(struct target *target,
60 uint32_t *value, int regnum)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortexm_dap_write_coreregister_u32(struct target *target,
93 uint32_t value, int regnum)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a separate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_set_maskints(struct target *target, bool mask)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
143 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
144 else
145 return ERROR_OK;
146 }
147
148 static int cortex_m_set_maskints_for_halt(struct target *target)
149 {
150 struct cortex_m_common *cortex_m = target_to_cm(target);
151 switch (cortex_m->isrmasking_mode) {
152 case CORTEX_M_ISRMASK_AUTO:
153 /* interrupts taken at resume, whether for step or run -> no mask */
154 return cortex_m_set_maskints(target, false);
155
156 case CORTEX_M_ISRMASK_OFF:
157 /* interrupts never masked */
158 return cortex_m_set_maskints(target, false);
159
160 case CORTEX_M_ISRMASK_ON:
161 /* interrupts always masked */
162 return cortex_m_set_maskints(target, true);
163
164 case CORTEX_M_ISRMASK_STEPONLY:
165 /* interrupts masked for single step only -> mask now if MASKINTS
166 * erratum, otherwise only mask before stepping */
167 return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
168 }
169 return ERROR_OK;
170 }
171
172 static int cortex_m_set_maskints_for_run(struct target *target)
173 {
174 switch (target_to_cm(target)->isrmasking_mode) {
175 case CORTEX_M_ISRMASK_AUTO:
176 /* interrupts taken at resume, whether for step or run -> no mask */
177 return cortex_m_set_maskints(target, false);
178
179 case CORTEX_M_ISRMASK_OFF:
180 /* interrupts never masked */
181 return cortex_m_set_maskints(target, false);
182
183 case CORTEX_M_ISRMASK_ON:
184 /* interrupts always masked */
185 return cortex_m_set_maskints(target, true);
186
187 case CORTEX_M_ISRMASK_STEPONLY:
188 /* interrupts masked for single step only -> no mask */
189 return cortex_m_set_maskints(target, false);
190 }
191 return ERROR_OK;
192 }
193
194 static int cortex_m_set_maskints_for_step(struct target *target)
195 {
196 switch (target_to_cm(target)->isrmasking_mode) {
197 case CORTEX_M_ISRMASK_AUTO:
198 /* the auto-interrupt should already be done -> mask */
199 return cortex_m_set_maskints(target, true);
200
201 case CORTEX_M_ISRMASK_OFF:
202 /* interrupts never masked */
203 return cortex_m_set_maskints(target, false);
204
205 case CORTEX_M_ISRMASK_ON:
206 /* interrupts always masked */
207 return cortex_m_set_maskints(target, true);
208
209 case CORTEX_M_ISRMASK_STEPONLY:
210 /* interrupts masked for single step only -> mask */
211 return cortex_m_set_maskints(target, true);
212 }
213 return ERROR_OK;
214 }
215
216 static int cortex_m_clear_halt(struct target *target)
217 {
218 struct cortex_m_common *cortex_m = target_to_cm(target);
219 struct armv7m_common *armv7m = &cortex_m->armv7m;
220 int retval;
221
222 /* clear step if any */
223 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
224
225 /* Read Debug Fault Status Register */
226 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Clear Debug Fault Status */
231 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
232 if (retval != ERROR_OK)
233 return retval;
234 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
235
236 return ERROR_OK;
237 }
238
239 static int cortex_m_single_step_core(struct target *target)
240 {
241 struct cortex_m_common *cortex_m = target_to_cm(target);
242 struct armv7m_common *armv7m = &cortex_m->armv7m;
243 int retval;
244
245 /* Mask interrupts before clearing halt, if not done already. This avoids
246 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
247 * HALT can put the core into an unknown state.
248 */
249 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
250 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
251 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
252 if (retval != ERROR_OK)
253 return retval;
254 }
255 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
256 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
257 if (retval != ERROR_OK)
258 return retval;
259 LOG_DEBUG(" ");
260
261 /* restore dhcsr reg */
262 cortex_m_clear_halt(target);
263
264 return ERROR_OK;
265 }
266
267 static int cortex_m_enable_fpb(struct target *target)
268 {
269 int retval = target_write_u32(target, FP_CTRL, 3);
270 if (retval != ERROR_OK)
271 return retval;
272
273 /* check the fpb is actually enabled */
274 uint32_t fpctrl;
275 retval = target_read_u32(target, FP_CTRL, &fpctrl);
276 if (retval != ERROR_OK)
277 return retval;
278
279 if (fpctrl & 1)
280 return ERROR_OK;
281
282 return ERROR_FAIL;
283 }
284
285 static int cortex_m_endreset_event(struct target *target)
286 {
287 int i;
288 int retval;
289 uint32_t dcb_demcr;
290 struct cortex_m_common *cortex_m = target_to_cm(target);
291 struct armv7m_common *armv7m = &cortex_m->armv7m;
292 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
293 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
294 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
295
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
298 if (retval != ERROR_OK)
299 return retval;
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
301
302 /* this register is used for emulated dcc channel */
303 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
304 if (retval != ERROR_OK)
305 return retval;
306
307 /* Enable debug requests */
308 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
309 if (retval != ERROR_OK)
310 return retval;
311 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
312 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
313 if (retval != ERROR_OK)
314 return retval;
315 }
316
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target);
319
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
322 *
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
326 */
327 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
328 if (retval != ERROR_OK)
329 return retval;
330
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
333 */
334
335 /* Enable FPB */
336 retval = cortex_m_enable_fpb(target);
337 if (retval != ERROR_OK) {
338 LOG_ERROR("Failed to enable the FPB");
339 return retval;
340 }
341
342 cortex_m->fpb_enabled = true;
343
344 /* Restore FPB registers */
345 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
346 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350
351 /* Restore DWT registers */
352 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
353 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
354 dwt_list[i].comp);
355 if (retval != ERROR_OK)
356 return retval;
357 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
358 dwt_list[i].mask);
359 if (retval != ERROR_OK)
360 return retval;
361 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
362 dwt_list[i].function);
363 if (retval != ERROR_OK)
364 return retval;
365 }
366 retval = dap_run(swjdp);
367 if (retval != ERROR_OK)
368 return retval;
369
370 register_cache_invalidate(armv7m->arm.core_cache);
371
372 /* make sure we have latest dhcsr flags */
373 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
374
375 return retval;
376 }
377
378 static int cortex_m_examine_debug_reason(struct target *target)
379 {
380 struct cortex_m_common *cortex_m = target_to_cm(target);
381
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
384
385 if ((target->debug_reason != DBG_REASON_DBGRQ)
386 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
387 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
388 target->debug_reason = DBG_REASON_BREAKPOINT;
389 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
390 target->debug_reason = DBG_REASON_WPTANDBKPT;
391 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
392 target->debug_reason = DBG_REASON_WATCHPOINT;
393 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
394 target->debug_reason = DBG_REASON_BREAKPOINT;
395 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
396 target->debug_reason = DBG_REASON_DBGRQ;
397 else /* HALTED */
398 target->debug_reason = DBG_REASON_UNDEFINED;
399 }
400
401 return ERROR_OK;
402 }
403
404 static int cortex_m_examine_exception_reason(struct target *target)
405 {
406 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
407 struct armv7m_common *armv7m = target_to_armv7m(target);
408 struct adiv5_dap *swjdp = armv7m->arm.dap;
409 int retval;
410
411 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
412 if (retval != ERROR_OK)
413 return retval;
414 switch (armv7m->exception_number) {
415 case 2: /* NMI */
416 break;
417 case 3: /* Hard Fault */
418 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
419 if (retval != ERROR_OK)
420 return retval;
421 if (except_sr & 0x40000000) {
422 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
423 if (retval != ERROR_OK)
424 return retval;
425 }
426 break;
427 case 4: /* Memory Management */
428 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
429 if (retval != ERROR_OK)
430 return retval;
431 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
432 if (retval != ERROR_OK)
433 return retval;
434 break;
435 case 5: /* Bus Fault */
436 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
437 if (retval != ERROR_OK)
438 return retval;
439 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
440 if (retval != ERROR_OK)
441 return retval;
442 break;
443 case 6: /* Usage Fault */
444 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
445 if (retval != ERROR_OK)
446 return retval;
447 break;
448 case 7: /* Secure Fault */
449 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
450 if (retval != ERROR_OK)
451 return retval;
452 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
453 if (retval != ERROR_OK)
454 return retval;
455 break;
456 case 11: /* SVCall */
457 break;
458 case 12: /* Debug Monitor */
459 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
460 if (retval != ERROR_OK)
461 return retval;
462 break;
463 case 14: /* PendSV */
464 break;
465 case 15: /* SysTick */
466 break;
467 default:
468 except_sr = 0;
469 break;
470 }
471 retval = dap_run(swjdp);
472 if (retval == ERROR_OK)
473 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
474 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
475 armv7m_exception_string(armv7m->exception_number),
476 shcsr, except_sr, cfsr, except_ar);
477 return retval;
478 }
479
480 static int cortex_m_debug_entry(struct target *target)
481 {
482 int i;
483 uint32_t xPSR;
484 int retval;
485 struct cortex_m_common *cortex_m = target_to_cm(target);
486 struct armv7m_common *armv7m = &cortex_m->armv7m;
487 struct arm *arm = &armv7m->arm;
488 struct reg *r;
489
490 LOG_DEBUG(" ");
491
492 /* Do this really early to minimize the window where the MASKINTS erratum
493 * can pile up pending interrupts. */
494 cortex_m_set_maskints_for_halt(target);
495
496 cortex_m_clear_halt(target);
497 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
498 if (retval != ERROR_OK)
499 return retval;
500
501 retval = armv7m->examine_debug_reason(target);
502 if (retval != ERROR_OK)
503 return retval;
504
505 /* examine PE security state */
506 bool secure_state = false;
507 if (armv7m->arm.is_armv8m) {
508 uint32_t dscsr;
509
510 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
511 if (retval != ERROR_OK)
512 return retval;
513
514 secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
515 }
516
517 /* Examine target state and mode
518 * First load register accessible through core debug port */
519 int num_regs = arm->core_cache->num_regs;
520
521 for (i = 0; i < num_regs; i++) {
522 r = &armv7m->arm.core_cache->reg_list[i];
523 if (!r->valid)
524 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
525 }
526
527 r = arm->cpsr;
528 xPSR = buf_get_u32(r->value, 0, 32);
529
530 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
531 if (xPSR & 0xf00) {
532 r->dirty = r->valid;
533 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
534 }
535
536 /* Are we in an exception handler */
537 if (xPSR & 0x1FF) {
538 armv7m->exception_number = (xPSR & 0x1FF);
539
540 arm->core_mode = ARM_MODE_HANDLER;
541 arm->map = armv7m_msp_reg_map;
542 } else {
543 unsigned control = buf_get_u32(arm->core_cache
544 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
545
546 /* is this thread privileged? */
547 arm->core_mode = control & 1
548 ? ARM_MODE_USER_THREAD
549 : ARM_MODE_THREAD;
550
551 /* which stack is it using? */
552 if (control & 2)
553 arm->map = armv7m_psp_reg_map;
554 else
555 arm->map = armv7m_msp_reg_map;
556
557 armv7m->exception_number = 0;
558 }
559
560 if (armv7m->exception_number)
561 cortex_m_examine_exception_reason(target);
562
563 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
564 arm_mode_name(arm->core_mode),
565 buf_get_u32(arm->pc->value, 0, 32),
566 secure_state ? "Secure" : "Non-Secure",
567 target_state_name(target));
568
569 if (armv7m->post_debug_entry) {
570 retval = armv7m->post_debug_entry(target);
571 if (retval != ERROR_OK)
572 return retval;
573 }
574
575 return ERROR_OK;
576 }
577
578 static int cortex_m_poll(struct target *target)
579 {
580 int detected_failure = ERROR_OK;
581 int retval = ERROR_OK;
582 enum target_state prev_target_state = target->state;
583 struct cortex_m_common *cortex_m = target_to_cm(target);
584 struct armv7m_common *armv7m = &cortex_m->armv7m;
585
586 /* Read from Debug Halting Control and Status Register */
587 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
588 if (retval != ERROR_OK) {
589 target->state = TARGET_UNKNOWN;
590 return retval;
591 }
592
593 /* Recover from lockup. See ARMv7-M architecture spec,
594 * section B1.5.15 "Unrecoverable exception cases".
595 */
596 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
597 LOG_ERROR("%s -- clearing lockup after double fault",
598 target_name(target));
599 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
600 target->debug_reason = DBG_REASON_DBGRQ;
601
602 /* We have to execute the rest (the "finally" equivalent, but
603 * still throw this exception again).
604 */
605 detected_failure = ERROR_FAIL;
606
607 /* refresh status bits */
608 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
609 if (retval != ERROR_OK)
610 return retval;
611 }
612
613 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
614 if (target->state != TARGET_RESET) {
615 target->state = TARGET_RESET;
616 LOG_INFO("%s: external reset detected", target_name(target));
617 }
618 return ERROR_OK;
619 }
620
621 if (target->state == TARGET_RESET) {
622 /* Cannot switch context while running so endreset is
623 * called with target->state == TARGET_RESET
624 */
625 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
626 cortex_m->dcb_dhcsr);
627 retval = cortex_m_endreset_event(target);
628 if (retval != ERROR_OK) {
629 target->state = TARGET_UNKNOWN;
630 return retval;
631 }
632 target->state = TARGET_RUNNING;
633 prev_target_state = TARGET_RUNNING;
634 }
635
636 if (cortex_m->dcb_dhcsr & S_HALT) {
637 target->state = TARGET_HALTED;
638
639 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
640 retval = cortex_m_debug_entry(target);
641 if (retval != ERROR_OK)
642 return retval;
643
644 if (arm_semihosting(target, &retval) != 0)
645 return retval;
646
647 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
648 }
649 if (prev_target_state == TARGET_DEBUG_RUNNING) {
650 LOG_DEBUG(" ");
651 retval = cortex_m_debug_entry(target);
652 if (retval != ERROR_OK)
653 return retval;
654
655 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
656 }
657 }
658
659 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
660 * How best to model low power modes?
661 */
662
663 if (target->state == TARGET_UNKNOWN) {
664 /* check if processor is retiring instructions */
665 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
666 target->state = TARGET_RUNNING;
667 retval = ERROR_OK;
668 }
669 }
670
671 /* Check that target is truly halted, since the target could be resumed externally */
672 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
673 /* registers are now invalid */
674 register_cache_invalidate(armv7m->arm.core_cache);
675
676 target->state = TARGET_RUNNING;
677 LOG_WARNING("%s: external resume detected", target_name(target));
678 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
679 retval = ERROR_OK;
680 }
681
682 /* Did we detect a failure condition that we cleared? */
683 if (detected_failure != ERROR_OK)
684 retval = detected_failure;
685 return retval;
686 }
687
688 static int cortex_m_halt(struct target *target)
689 {
690 LOG_DEBUG("target->state: %s",
691 target_state_name(target));
692
693 if (target->state == TARGET_HALTED) {
694 LOG_DEBUG("target was already halted");
695 return ERROR_OK;
696 }
697
698 if (target->state == TARGET_UNKNOWN)
699 LOG_WARNING("target was in unknown state when halt was requested");
700
701 if (target->state == TARGET_RESET) {
702 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
703 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
704 return ERROR_TARGET_FAILURE;
705 } else {
706 /* we came here in a reset_halt or reset_init sequence
707 * debug entry was already prepared in cortex_m3_assert_reset()
708 */
709 target->debug_reason = DBG_REASON_DBGRQ;
710
711 return ERROR_OK;
712 }
713 }
714
715 /* Write to Debug Halting Control and Status Register */
716 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
717
718 /* Do this really early to minimize the window where the MASKINTS erratum
719 * can pile up pending interrupts. */
720 cortex_m_set_maskints_for_halt(target);
721
722 target->debug_reason = DBG_REASON_DBGRQ;
723
724 return ERROR_OK;
725 }
726
727 static int cortex_m_soft_reset_halt(struct target *target)
728 {
729 struct cortex_m_common *cortex_m = target_to_cm(target);
730 struct armv7m_common *armv7m = &cortex_m->armv7m;
731 uint32_t dcb_dhcsr = 0;
732 int retval, timeout = 0;
733
734 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
735 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
736 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
737 * core, not the peripherals */
738 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
739
740 /* Set C_DEBUGEN */
741 retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
742 if (retval != ERROR_OK)
743 return retval;
744
745 /* Enter debug state on reset; restore DEMCR in endreset_event() */
746 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
747 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
748 if (retval != ERROR_OK)
749 return retval;
750
751 /* Request a core-only reset */
752 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
753 AIRCR_VECTKEY | AIRCR_VECTRESET);
754 if (retval != ERROR_OK)
755 return retval;
756 target->state = TARGET_RESET;
757
758 /* registers are now invalid */
759 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
760
761 while (timeout < 100) {
762 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
763 if (retval == ERROR_OK) {
764 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
765 &cortex_m->nvic_dfsr);
766 if (retval != ERROR_OK)
767 return retval;
768 if ((dcb_dhcsr & S_HALT)
769 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
770 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
771 "DFSR 0x%08x",
772 (unsigned) dcb_dhcsr,
773 (unsigned) cortex_m->nvic_dfsr);
774 cortex_m_poll(target);
775 /* FIXME restore user's vector catch config */
776 return ERROR_OK;
777 } else
778 LOG_DEBUG("waiting for system reset-halt, "
779 "DHCSR 0x%08x, %d ms",
780 (unsigned) dcb_dhcsr, timeout);
781 }
782 timeout++;
783 alive_sleep(1);
784 }
785
786 return ERROR_OK;
787 }
788
789 void cortex_m_enable_breakpoints(struct target *target)
790 {
791 struct breakpoint *breakpoint = target->breakpoints;
792
793 /* set any pending breakpoints */
794 while (breakpoint) {
795 if (!breakpoint->set)
796 cortex_m_set_breakpoint(target, breakpoint);
797 breakpoint = breakpoint->next;
798 }
799 }
800
801 static int cortex_m_resume(struct target *target, int current,
802 target_addr_t address, int handle_breakpoints, int debug_execution)
803 {
804 struct armv7m_common *armv7m = target_to_armv7m(target);
805 struct breakpoint *breakpoint = NULL;
806 uint32_t resume_pc;
807 struct reg *r;
808
809 if (target->state != TARGET_HALTED) {
810 LOG_WARNING("target not halted");
811 return ERROR_TARGET_NOT_HALTED;
812 }
813
814 if (!debug_execution) {
815 target_free_all_working_areas(target);
816 cortex_m_enable_breakpoints(target);
817 cortex_m_enable_watchpoints(target);
818 }
819
820 if (debug_execution) {
821 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
822
823 /* Disable interrupts */
824 /* We disable interrupts in the PRIMASK register instead of
825 * masking with C_MASKINTS. This is probably the same issue
826 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
827 * in parallel with disabled interrupts can cause local faults
828 * to not be taken.
829 *
830 * REVISIT this clearly breaks non-debug execution, since the
831 * PRIMASK register state isn't saved/restored... workaround
832 * by never resuming app code after debug execution.
833 */
834 buf_set_u32(r->value, 0, 1, 1);
835 r->dirty = true;
836 r->valid = true;
837
838 /* Make sure we are in Thumb mode */
839 r = armv7m->arm.cpsr;
840 buf_set_u32(r->value, 24, 1, 1);
841 r->dirty = true;
842 r->valid = true;
843 }
844
845 /* current = 1: continue on current pc, otherwise continue at <address> */
846 r = armv7m->arm.pc;
847 if (!current) {
848 buf_set_u32(r->value, 0, 32, address);
849 r->dirty = true;
850 r->valid = true;
851 }
852
853 /* if we halted last time due to a bkpt instruction
854 * then we have to manually step over it, otherwise
855 * the core will break again */
856
857 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
858 && !debug_execution)
859 armv7m_maybe_skip_bkpt_inst(target, NULL);
860
861 resume_pc = buf_get_u32(r->value, 0, 32);
862
863 armv7m_restore_context(target);
864
865 /* the front-end may request us not to handle breakpoints */
866 if (handle_breakpoints) {
867 /* Single step past breakpoint at current address */
868 breakpoint = breakpoint_find(target, resume_pc);
869 if (breakpoint) {
870 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
871 breakpoint->address,
872 breakpoint->unique_id);
873 cortex_m_unset_breakpoint(target, breakpoint);
874 cortex_m_single_step_core(target);
875 cortex_m_set_breakpoint(target, breakpoint);
876 }
877 }
878
879 /* Restart core */
880 cortex_m_set_maskints_for_run(target);
881 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
882
883 target->debug_reason = DBG_REASON_NOTHALTED;
884
885 /* registers are now invalid */
886 register_cache_invalidate(armv7m->arm.core_cache);
887
888 if (!debug_execution) {
889 target->state = TARGET_RUNNING;
890 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
891 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
892 } else {
893 target->state = TARGET_DEBUG_RUNNING;
894 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
895 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
896 }
897
898 return ERROR_OK;
899 }
900
901 /* int irqstepcount = 0; */
902 static int cortex_m_step(struct target *target, int current,
903 target_addr_t address, int handle_breakpoints)
904 {
905 struct cortex_m_common *cortex_m = target_to_cm(target);
906 struct armv7m_common *armv7m = &cortex_m->armv7m;
907 struct breakpoint *breakpoint = NULL;
908 struct reg *pc = armv7m->arm.pc;
909 bool bkpt_inst_found = false;
910 int retval;
911 bool isr_timed_out = false;
912
913 if (target->state != TARGET_HALTED) {
914 LOG_WARNING("target not halted");
915 return ERROR_TARGET_NOT_HALTED;
916 }
917
918 /* current = 1: continue on current pc, otherwise continue at <address> */
919 if (!current)
920 buf_set_u32(pc->value, 0, 32, address);
921
922 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
923
924 /* the front-end may request us not to handle breakpoints */
925 if (handle_breakpoints) {
926 breakpoint = breakpoint_find(target, pc_value);
927 if (breakpoint)
928 cortex_m_unset_breakpoint(target, breakpoint);
929 }
930
931 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
932
933 target->debug_reason = DBG_REASON_SINGLESTEP;
934
935 armv7m_restore_context(target);
936
937 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
938
939 /* if no bkpt instruction is found at pc then we can perform
940 * a normal step, otherwise we have to manually step over the bkpt
941 * instruction - as such simulate a step */
942 if (bkpt_inst_found == false) {
943 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
944 /* Automatic ISR masking mode off: Just step over the next
945 * instruction, with interrupts on or off as appropriate. */
946 cortex_m_set_maskints_for_step(target);
947 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
948 } else {
949 /* Process interrupts during stepping in a way they don't interfere
950 * debugging.
951 *
952 * Principle:
953 *
954 * Set a temporary break point at the current pc and let the core run
955 * with interrupts enabled. Pending interrupts get served and we run
956 * into the breakpoint again afterwards. Then we step over the next
957 * instruction with interrupts disabled.
958 *
959 * If the pending interrupts don't complete within time, we leave the
960 * core running. This may happen if the interrupts trigger faster
961 * than the core can process them or the handler doesn't return.
962 *
963 * If no more breakpoints are available we simply do a step with
964 * interrupts enabled.
965 *
966 */
967
968 /* 2012-09-29 ph
969 *
970 * If a break point is already set on the lower half word then a break point on
971 * the upper half word will not break again when the core is restarted. So we
972 * just step over the instruction with interrupts disabled.
973 *
974 * The documentation has no information about this, it was found by observation
975 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
976 * suffer from this problem.
977 *
978 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
979 * address has it always cleared. The former is done to indicate thumb mode
980 * to gdb.
981 *
982 */
983 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
984 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
985 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
986 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
987 /* Re-enable interrupts if appropriate */
988 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
989 cortex_m_set_maskints_for_halt(target);
990 } else {
991
992 /* Set a temporary break point */
993 if (breakpoint) {
994 retval = cortex_m_set_breakpoint(target, breakpoint);
995 } else {
996 enum breakpoint_type type = BKPT_HARD;
997 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
998 /* FPB rev.1 cannot handle such addr, try BKPT instr */
999 type = BKPT_SOFT;
1000 }
1001 retval = breakpoint_add(target, pc_value, 2, type);
1002 }
1003
1004 bool tmp_bp_set = (retval == ERROR_OK);
1005
1006 /* No more breakpoints left, just do a step */
1007 if (!tmp_bp_set) {
1008 cortex_m_set_maskints_for_step(target);
1009 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1010 /* Re-enable interrupts if appropriate */
1011 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1012 cortex_m_set_maskints_for_halt(target);
1013 } else {
1014 /* Start the core */
1015 LOG_DEBUG("Starting core to serve pending interrupts");
1016 int64_t t_start = timeval_ms();
1017 cortex_m_set_maskints_for_run(target);
1018 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
1019
1020 /* Wait for pending handlers to complete or timeout */
1021 do {
1022 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
1023 DCB_DHCSR,
1024 &cortex_m->dcb_dhcsr);
1025 if (retval != ERROR_OK) {
1026 target->state = TARGET_UNKNOWN;
1027 return retval;
1028 }
1029 isr_timed_out = ((timeval_ms() - t_start) > 500);
1030 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1031
1032 /* only remove breakpoint if we created it */
1033 if (breakpoint)
1034 cortex_m_unset_breakpoint(target, breakpoint);
1035 else {
1036 /* Remove the temporary breakpoint */
1037 breakpoint_remove(target, pc_value);
1038 }
1039
1040 if (isr_timed_out) {
1041 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1042 "leaving target running");
1043 } else {
1044 /* Step over next instruction with interrupts disabled */
1045 cortex_m_set_maskints_for_step(target);
1046 cortex_m_write_debug_halt_mask(target,
1047 C_HALT | C_MASKINTS,
1048 0);
1049 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1050 /* Re-enable interrupts if appropriate */
1051 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1052 cortex_m_set_maskints_for_halt(target);
1053 }
1054 }
1055 }
1056 }
1057 }
1058
1059 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1060 if (retval != ERROR_OK)
1061 return retval;
1062
1063 /* registers are now invalid */
1064 register_cache_invalidate(armv7m->arm.core_cache);
1065
1066 if (breakpoint)
1067 cortex_m_set_breakpoint(target, breakpoint);
1068
1069 if (isr_timed_out) {
1070 /* Leave the core running. The user has to stop execution manually. */
1071 target->debug_reason = DBG_REASON_NOTHALTED;
1072 target->state = TARGET_RUNNING;
1073 return ERROR_OK;
1074 }
1075
1076 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1077 " nvic_icsr = 0x%" PRIx32,
1078 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1079
1080 retval = cortex_m_debug_entry(target);
1081 if (retval != ERROR_OK)
1082 return retval;
1083 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1084
1085 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1086 " nvic_icsr = 0x%" PRIx32,
1087 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1088
1089 return ERROR_OK;
1090 }
1091
1092 static int cortex_m_assert_reset(struct target *target)
1093 {
1094 struct cortex_m_common *cortex_m = target_to_cm(target);
1095 struct armv7m_common *armv7m = &cortex_m->armv7m;
1096 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1097
1098 LOG_DEBUG("target->state: %s",
1099 target_state_name(target));
1100
1101 enum reset_types jtag_reset_config = jtag_get_reset_config();
1102
1103 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1104 /* allow scripts to override the reset event */
1105
1106 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1107 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1108 target->state = TARGET_RESET;
1109
1110 return ERROR_OK;
1111 }
1112
1113 /* some cores support connecting while srst is asserted
1114 * use that mode is it has been configured */
1115
1116 bool srst_asserted = false;
1117
1118 if (!target_was_examined(target)) {
1119 if (jtag_reset_config & RESET_HAS_SRST) {
1120 adapter_assert_reset();
1121 if (target->reset_halt)
1122 LOG_ERROR("Target not examined, will not halt after reset!");
1123 return ERROR_OK;
1124 } else {
1125 LOG_ERROR("Target not examined, reset NOT asserted!");
1126 return ERROR_FAIL;
1127 }
1128 }
1129
1130 if ((jtag_reset_config & RESET_HAS_SRST) &&
1131 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1132 adapter_assert_reset();
1133 srst_asserted = true;
1134 }
1135
1136 /* Enable debug requests */
1137 int retval;
1138 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1139 /* Store important errors instead of failing and proceed to reset assert */
1140
1141 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1142 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1143
1144 /* If the processor is sleeping in a WFI or WFE instruction, the
1145 * C_HALT bit must be asserted to regain control */
1146 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1147 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1148
1149 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1150 /* Ignore less important errors */
1151
1152 if (!target->reset_halt) {
1153 /* Set/Clear C_MASKINTS in a separate operation */
1154 cortex_m_set_maskints_for_run(target);
1155
1156 /* clear any debug flags before resuming */
1157 cortex_m_clear_halt(target);
1158
1159 /* clear C_HALT in dhcsr reg */
1160 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1161 } else {
1162 /* Halt in debug on reset; endreset_event() restores DEMCR.
1163 *
1164 * REVISIT catching BUSERR presumably helps to defend against
1165 * bad vector table entries. Should this include MMERR or
1166 * other flags too?
1167 */
1168 int retval2;
1169 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1170 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1171 if (retval != ERROR_OK || retval2 != ERROR_OK)
1172 LOG_INFO("AP write error, reset will not halt");
1173 }
1174
1175 if (jtag_reset_config & RESET_HAS_SRST) {
1176 /* default to asserting srst */
1177 if (!srst_asserted)
1178 adapter_assert_reset();
1179
1180 /* srst is asserted, ignore AP access errors */
1181 retval = ERROR_OK;
1182 } else {
1183 /* Use a standard Cortex-M3 software reset mechanism.
1184 * We default to using VECRESET as it is supported on all current cores
1185 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1186 * This has the disadvantage of not resetting the peripherals, so a
1187 * reset-init event handler is needed to perform any peripheral resets.
1188 */
1189 if (!cortex_m->vectreset_supported
1190 && reset_config == CORTEX_M_RESET_VECTRESET) {
1191 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1192 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1193 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1194 }
1195
1196 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1197 ? "SYSRESETREQ" : "VECTRESET");
1198
1199 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1200 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1201 "handler to reset any peripherals or configure hardware srst support.");
1202 }
1203
1204 int retval3;
1205 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1206 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1207 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1208 if (retval3 != ERROR_OK)
1209 LOG_DEBUG("Ignoring AP write error right after reset");
1210
1211 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1212 if (retval3 != ERROR_OK)
1213 LOG_ERROR("DP initialisation failed");
1214
1215 else {
1216 /* I do not know why this is necessary, but it
1217 * fixes strange effects (step/resume cause NMI
1218 * after reset) on LM3S6918 -- Michael Schwingen
1219 */
1220 uint32_t tmp;
1221 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1222 }
1223 }
1224
1225 target->state = TARGET_RESET;
1226 jtag_sleep(50000);
1227
1228 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1229
1230 /* now return stored error code if any */
1231 if (retval != ERROR_OK)
1232 return retval;
1233
1234 if (target->reset_halt) {
1235 retval = target_halt(target);
1236 if (retval != ERROR_OK)
1237 return retval;
1238 }
1239
1240 return ERROR_OK;
1241 }
1242
1243 static int cortex_m_deassert_reset(struct target *target)
1244 {
1245 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1246
1247 LOG_DEBUG("target->state: %s",
1248 target_state_name(target));
1249
1250 /* deassert reset lines */
1251 adapter_deassert_reset();
1252
1253 enum reset_types jtag_reset_config = jtag_get_reset_config();
1254
1255 if ((jtag_reset_config & RESET_HAS_SRST) &&
1256 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1257 target_was_examined(target)) {
1258 int retval = dap_dp_init(armv7m->debug_ap->dap);
1259 if (retval != ERROR_OK) {
1260 LOG_ERROR("DP initialisation failed");
1261 return retval;
1262 }
1263 }
1264
1265 return ERROR_OK;
1266 }
1267
1268 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1269 {
1270 int retval;
1271 int fp_num = 0;
1272 struct cortex_m_common *cortex_m = target_to_cm(target);
1273 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1274
1275 if (breakpoint->set) {
1276 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1277 return ERROR_OK;
1278 }
1279
1280 if (breakpoint->type == BKPT_HARD) {
1281 uint32_t fpcr_value;
1282 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1283 fp_num++;
1284 if (fp_num >= cortex_m->fp_num_code) {
1285 LOG_ERROR("Can not find free FPB Comparator!");
1286 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1287 }
1288 breakpoint->set = fp_num + 1;
1289 fpcr_value = breakpoint->address | 1;
1290 if (cortex_m->fp_rev == 0) {
1291 if (breakpoint->address > 0x1FFFFFFF) {
1292 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1293 return ERROR_FAIL;
1294 }
1295 uint32_t hilo;
1296 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1297 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1298 } else if (cortex_m->fp_rev > 1) {
1299 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1300 return ERROR_FAIL;
1301 }
1302 comparator_list[fp_num].used = true;
1303 comparator_list[fp_num].fpcr_value = fpcr_value;
1304 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1305 comparator_list[fp_num].fpcr_value);
1306 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1307 fp_num,
1308 comparator_list[fp_num].fpcr_value);
1309 if (!cortex_m->fpb_enabled) {
1310 LOG_DEBUG("FPB wasn't enabled, do it now");
1311 retval = cortex_m_enable_fpb(target);
1312 if (retval != ERROR_OK) {
1313 LOG_ERROR("Failed to enable the FPB");
1314 return retval;
1315 }
1316
1317 cortex_m->fpb_enabled = true;
1318 }
1319 } else if (breakpoint->type == BKPT_SOFT) {
1320 uint8_t code[4];
1321
1322 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1323 * semihosting; don't use that. Otherwise the BKPT
1324 * parameter is arbitrary.
1325 */
1326 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1327 retval = target_read_memory(target,
1328 breakpoint->address & 0xFFFFFFFE,
1329 breakpoint->length, 1,
1330 breakpoint->orig_instr);
1331 if (retval != ERROR_OK)
1332 return retval;
1333 retval = target_write_memory(target,
1334 breakpoint->address & 0xFFFFFFFE,
1335 breakpoint->length, 1,
1336 code);
1337 if (retval != ERROR_OK)
1338 return retval;
1339 breakpoint->set = true;
1340 }
1341
1342 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1343 breakpoint->unique_id,
1344 (int)(breakpoint->type),
1345 breakpoint->address,
1346 breakpoint->length,
1347 breakpoint->set);
1348
1349 return ERROR_OK;
1350 }
1351
1352 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1353 {
1354 int retval;
1355 struct cortex_m_common *cortex_m = target_to_cm(target);
1356 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1357
1358 if (!breakpoint->set) {
1359 LOG_WARNING("breakpoint not set");
1360 return ERROR_OK;
1361 }
1362
1363 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1364 breakpoint->unique_id,
1365 (int)(breakpoint->type),
1366 breakpoint->address,
1367 breakpoint->length,
1368 breakpoint->set);
1369
1370 if (breakpoint->type == BKPT_HARD) {
1371 int fp_num = breakpoint->set - 1;
1372 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1373 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1374 return ERROR_OK;
1375 }
1376 comparator_list[fp_num].used = false;
1377 comparator_list[fp_num].fpcr_value = 0;
1378 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1379 comparator_list[fp_num].fpcr_value);
1380 } else {
1381 /* restore original instruction (kept in target endianness) */
1382 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1383 breakpoint->length, 1,
1384 breakpoint->orig_instr);
1385 if (retval != ERROR_OK)
1386 return retval;
1387 }
1388 breakpoint->set = false;
1389
1390 return ERROR_OK;
1391 }
1392
1393 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1394 {
1395 if (breakpoint->length == 3) {
1396 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1397 breakpoint->length = 2;
1398 }
1399
1400 if ((breakpoint->length != 2)) {
1401 LOG_INFO("only breakpoints of two bytes length supported");
1402 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1403 }
1404
1405 return cortex_m_set_breakpoint(target, breakpoint);
1406 }
1407
1408 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1409 {
1410 if (!breakpoint->set)
1411 return ERROR_OK;
1412
1413 return cortex_m_unset_breakpoint(target, breakpoint);
1414 }
1415
1416 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1417 {
1418 int dwt_num = 0;
1419 struct cortex_m_common *cortex_m = target_to_cm(target);
1420
1421 /* REVISIT Don't fully trust these "not used" records ... users
1422 * may set up breakpoints by hand, e.g. dual-address data value
1423 * watchpoint using comparator #1; comparator #0 matching cycle
1424 * count; send data trace info through ITM and TPIU; etc
1425 */
1426 struct cortex_m_dwt_comparator *comparator;
1427
1428 for (comparator = cortex_m->dwt_comparator_list;
1429 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1430 comparator++, dwt_num++)
1431 continue;
1432 if (dwt_num >= cortex_m->dwt_num_comp) {
1433 LOG_ERROR("Can not find free DWT Comparator");
1434 return ERROR_FAIL;
1435 }
1436 comparator->used = true;
1437 watchpoint->set = dwt_num + 1;
1438
1439 comparator->comp = watchpoint->address;
1440 target_write_u32(target, comparator->dwt_comparator_address + 0,
1441 comparator->comp);
1442
1443 if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1444 uint32_t mask = 0, temp;
1445
1446 /* watchpoint params were validated earlier */
1447 temp = watchpoint->length;
1448 while (temp) {
1449 temp >>= 1;
1450 mask++;
1451 }
1452 mask--;
1453
1454 comparator->mask = mask;
1455 target_write_u32(target, comparator->dwt_comparator_address + 4,
1456 comparator->mask);
1457
1458 switch (watchpoint->rw) {
1459 case WPT_READ:
1460 comparator->function = 5;
1461 break;
1462 case WPT_WRITE:
1463 comparator->function = 6;
1464 break;
1465 case WPT_ACCESS:
1466 comparator->function = 7;
1467 break;
1468 }
1469 } else {
1470 uint32_t data_size = watchpoint->length >> 1;
1471 comparator->mask = (watchpoint->length >> 1) | 1;
1472
1473 switch (watchpoint->rw) {
1474 case WPT_ACCESS:
1475 comparator->function = 4;
1476 break;
1477 case WPT_WRITE:
1478 comparator->function = 5;
1479 break;
1480 case WPT_READ:
1481 comparator->function = 6;
1482 break;
1483 }
1484 comparator->function = comparator->function | (1 << 4) |
1485 (data_size << 10);
1486 }
1487
1488 target_write_u32(target, comparator->dwt_comparator_address + 8,
1489 comparator->function);
1490
1491 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1492 watchpoint->unique_id, dwt_num,
1493 (unsigned) comparator->comp,
1494 (unsigned) comparator->mask,
1495 (unsigned) comparator->function);
1496 return ERROR_OK;
1497 }
1498
1499 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1500 {
1501 struct cortex_m_common *cortex_m = target_to_cm(target);
1502 struct cortex_m_dwt_comparator *comparator;
1503 int dwt_num;
1504
1505 if (!watchpoint->set) {
1506 LOG_WARNING("watchpoint (wpid: %d) not set",
1507 watchpoint->unique_id);
1508 return ERROR_OK;
1509 }
1510
1511 dwt_num = watchpoint->set - 1;
1512
1513 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1514 watchpoint->unique_id, dwt_num,
1515 (unsigned) watchpoint->address);
1516
1517 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1518 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1519 return ERROR_OK;
1520 }
1521
1522 comparator = cortex_m->dwt_comparator_list + dwt_num;
1523 comparator->used = false;
1524 comparator->function = 0;
1525 target_write_u32(target, comparator->dwt_comparator_address + 8,
1526 comparator->function);
1527
1528 watchpoint->set = false;
1529
1530 return ERROR_OK;
1531 }
1532
1533 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1534 {
1535 struct cortex_m_common *cortex_m = target_to_cm(target);
1536
1537 if (cortex_m->dwt_comp_available < 1) {
1538 LOG_DEBUG("no comparators?");
1539 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1540 }
1541
1542 /* hardware doesn't support data value masking */
1543 if (watchpoint->mask != ~(uint32_t)0) {
1544 LOG_DEBUG("watchpoint value masks not supported");
1545 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1546 }
1547
1548 /* hardware allows address masks of up to 32K */
1549 unsigned mask;
1550
1551 for (mask = 0; mask < 16; mask++) {
1552 if ((1u << mask) == watchpoint->length)
1553 break;
1554 }
1555 if (mask == 16) {
1556 LOG_DEBUG("unsupported watchpoint length");
1557 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1558 }
1559 if (watchpoint->address & ((1 << mask) - 1)) {
1560 LOG_DEBUG("watchpoint address is unaligned");
1561 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1562 }
1563
1564 /* Caller doesn't seem to be able to describe watching for data
1565 * values of zero; that flags "no value".
1566 *
1567 * REVISIT This DWT may well be able to watch for specific data
1568 * values. Requires comparator #1 to set DATAVMATCH and match
1569 * the data, and another comparator (DATAVADDR0) matching addr.
1570 */
1571 if (watchpoint->value) {
1572 LOG_DEBUG("data value watchpoint not YET supported");
1573 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1574 }
1575
1576 cortex_m->dwt_comp_available--;
1577 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1578
1579 return ERROR_OK;
1580 }
1581
1582 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1583 {
1584 struct cortex_m_common *cortex_m = target_to_cm(target);
1585
1586 /* REVISIT why check? DWT can be updated with core running ... */
1587 if (target->state != TARGET_HALTED) {
1588 LOG_WARNING("target not halted");
1589 return ERROR_TARGET_NOT_HALTED;
1590 }
1591
1592 if (watchpoint->set)
1593 cortex_m_unset_watchpoint(target, watchpoint);
1594
1595 cortex_m->dwt_comp_available++;
1596 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1597
1598 return ERROR_OK;
1599 }
1600
1601 void cortex_m_enable_watchpoints(struct target *target)
1602 {
1603 struct watchpoint *watchpoint = target->watchpoints;
1604
1605 /* set any pending watchpoints */
1606 while (watchpoint) {
1607 if (!watchpoint->set)
1608 cortex_m_set_watchpoint(target, watchpoint);
1609 watchpoint = watchpoint->next;
1610 }
1611 }
1612
1613 static int cortex_m_load_core_reg_u32(struct target *target,
1614 uint32_t num, uint32_t *value)
1615 {
1616 int retval;
1617
1618 /* NOTE: we "know" here that the register identifiers used
1619 * in the v7m header match the Cortex-M3 Debug Core Register
1620 * Selector values for R0..R15, xPSR, MSP, and PSP.
1621 */
1622 switch (num) {
1623 case 0 ... 18:
1624 /* read a normal core register */
1625 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1626
1627 if (retval != ERROR_OK) {
1628 LOG_ERROR("JTAG failure %i", retval);
1629 return ERROR_JTAG_DEVICE_ERROR;
1630 }
1631 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1632 break;
1633
1634 case ARMV7M_FPSCR:
1635 /* Floating-point Status and Registers */
1636 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1637 if (retval != ERROR_OK)
1638 return retval;
1639 retval = target_read_u32(target, DCB_DCRDR, value);
1640 if (retval != ERROR_OK)
1641 return retval;
1642 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1643 break;
1644
1645 case ARMV7M_S0 ... ARMV7M_S31:
1646 /* Floating-point Status and Registers */
1647 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1648 if (retval != ERROR_OK)
1649 return retval;
1650 retval = target_read_u32(target, DCB_DCRDR, value);
1651 if (retval != ERROR_OK)
1652 return retval;
1653 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1654 (int)(num - ARMV7M_S0), *value);
1655 break;
1656
1657 case ARMV7M_PRIMASK:
1658 case ARMV7M_BASEPRI:
1659 case ARMV7M_FAULTMASK:
1660 case ARMV7M_CONTROL:
1661 /* Cortex-M3 packages these four registers as bitfields
1662 * in one Debug Core register. So say r0 and r2 docs;
1663 * it was removed from r1 docs, but still works.
1664 */
1665 cortexm_dap_read_coreregister_u32(target, value, 20);
1666
1667 switch (num) {
1668 case ARMV7M_PRIMASK:
1669 *value = buf_get_u32((uint8_t *)value, 0, 1);
1670 break;
1671
1672 case ARMV7M_BASEPRI:
1673 *value = buf_get_u32((uint8_t *)value, 8, 8);
1674 break;
1675
1676 case ARMV7M_FAULTMASK:
1677 *value = buf_get_u32((uint8_t *)value, 16, 1);
1678 break;
1679
1680 case ARMV7M_CONTROL:
1681 *value = buf_get_u32((uint8_t *)value, 24, 2);
1682 break;
1683 }
1684
1685 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1686 break;
1687
1688 default:
1689 return ERROR_COMMAND_SYNTAX_ERROR;
1690 }
1691
1692 return ERROR_OK;
1693 }
1694
1695 static int cortex_m_store_core_reg_u32(struct target *target,
1696 uint32_t num, uint32_t value)
1697 {
1698 int retval;
1699 uint32_t reg;
1700 struct armv7m_common *armv7m = target_to_armv7m(target);
1701
1702 /* NOTE: we "know" here that the register identifiers used
1703 * in the v7m header match the Cortex-M3 Debug Core Register
1704 * Selector values for R0..R15, xPSR, MSP, and PSP.
1705 */
1706 switch (num) {
1707 case 0 ... 18:
1708 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1709 if (retval != ERROR_OK) {
1710 struct reg *r;
1711
1712 LOG_ERROR("JTAG failure");
1713 r = armv7m->arm.core_cache->reg_list + num;
1714 r->dirty = r->valid;
1715 return ERROR_JTAG_DEVICE_ERROR;
1716 }
1717 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1718 break;
1719
1720 case ARMV7M_FPSCR:
1721 /* Floating-point Status and Registers */
1722 retval = target_write_u32(target, DCB_DCRDR, value);
1723 if (retval != ERROR_OK)
1724 return retval;
1725 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1726 if (retval != ERROR_OK)
1727 return retval;
1728 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1729 break;
1730
1731 case ARMV7M_S0 ... ARMV7M_S31:
1732 /* Floating-point Status and Registers */
1733 retval = target_write_u32(target, DCB_DCRDR, value);
1734 if (retval != ERROR_OK)
1735 return retval;
1736 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1737 if (retval != ERROR_OK)
1738 return retval;
1739 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1740 (int)(num - ARMV7M_S0), value);
1741 break;
1742
1743 case ARMV7M_PRIMASK:
1744 case ARMV7M_BASEPRI:
1745 case ARMV7M_FAULTMASK:
1746 case ARMV7M_CONTROL:
1747 /* Cortex-M3 packages these four registers as bitfields
1748 * in one Debug Core register. So say r0 and r2 docs;
1749 * it was removed from r1 docs, but still works.
1750 */
1751 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1752
1753 switch (num) {
1754 case ARMV7M_PRIMASK:
1755 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1756 break;
1757
1758 case ARMV7M_BASEPRI:
1759 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1760 break;
1761
1762 case ARMV7M_FAULTMASK:
1763 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1764 break;
1765
1766 case ARMV7M_CONTROL:
1767 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1768 break;
1769 }
1770
1771 cortexm_dap_write_coreregister_u32(target, reg, 20);
1772
1773 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1774 break;
1775
1776 default:
1777 return ERROR_COMMAND_SYNTAX_ERROR;
1778 }
1779
1780 return ERROR_OK;
1781 }
1782
1783 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1784 uint32_t size, uint32_t count, uint8_t *buffer)
1785 {
1786 struct armv7m_common *armv7m = target_to_armv7m(target);
1787
1788 if (armv7m->arm.is_armv6m) {
1789 /* armv6m does not handle unaligned memory access */
1790 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1791 return ERROR_TARGET_UNALIGNED_ACCESS;
1792 }
1793
1794 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1795 }
1796
1797 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1798 uint32_t size, uint32_t count, const uint8_t *buffer)
1799 {
1800 struct armv7m_common *armv7m = target_to_armv7m(target);
1801
1802 if (armv7m->arm.is_armv6m) {
1803 /* armv6m does not handle unaligned memory access */
1804 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1805 return ERROR_TARGET_UNALIGNED_ACCESS;
1806 }
1807
1808 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1809 }
1810
1811 static int cortex_m_init_target(struct command_context *cmd_ctx,
1812 struct target *target)
1813 {
1814 armv7m_build_reg_cache(target);
1815 arm_semihosting_init(target);
1816 return ERROR_OK;
1817 }
1818
1819 void cortex_m_deinit_target(struct target *target)
1820 {
1821 struct cortex_m_common *cortex_m = target_to_cm(target);
1822
1823 free(cortex_m->fp_comparator_list);
1824
1825 cortex_m_dwt_free(target);
1826 armv7m_free_reg_cache(target);
1827
1828 free(target->private_config);
1829 free(cortex_m);
1830 }
1831
1832 int cortex_m_profiling(struct target *target, uint32_t *samples,
1833 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1834 {
1835 struct timeval timeout, now;
1836 struct armv7m_common *armv7m = target_to_armv7m(target);
1837 uint32_t reg_value;
1838 bool use_pcsr = false;
1839 int retval = ERROR_OK;
1840 struct reg *reg;
1841
1842 gettimeofday(&timeout, NULL);
1843 timeval_add_time(&timeout, seconds, 0);
1844
1845 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1846 if (retval != ERROR_OK) {
1847 LOG_ERROR("Error while reading PCSR");
1848 return retval;
1849 }
1850
1851 if (reg_value != 0) {
1852 use_pcsr = true;
1853 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1854 } else {
1855 LOG_INFO("Starting profiling. Halting and resuming the"
1856 " target as often as we can...");
1857 reg = register_get_by_name(target->reg_cache, "pc", 1);
1858 }
1859
1860 /* Make sure the target is running */
1861 target_poll(target);
1862 if (target->state == TARGET_HALTED)
1863 retval = target_resume(target, 1, 0, 0, 0);
1864
1865 if (retval != ERROR_OK) {
1866 LOG_ERROR("Error while resuming target");
1867 return retval;
1868 }
1869
1870 uint32_t sample_count = 0;
1871
1872 for (;;) {
1873 if (use_pcsr) {
1874 if (armv7m && armv7m->debug_ap) {
1875 uint32_t read_count = max_num_samples - sample_count;
1876 if (read_count > 1024)
1877 read_count = 1024;
1878
1879 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1880 (void *)&samples[sample_count],
1881 4, read_count, DWT_PCSR);
1882 sample_count += read_count;
1883 } else {
1884 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1885 }
1886 } else {
1887 target_poll(target);
1888 if (target->state == TARGET_HALTED) {
1889 reg_value = buf_get_u32(reg->value, 0, 32);
1890 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1891 retval = target_resume(target, 1, 0, 0, 0);
1892 samples[sample_count++] = reg_value;
1893 target_poll(target);
1894 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1895 } else if (target->state == TARGET_RUNNING) {
1896 /* We want to quickly sample the PC. */
1897 retval = target_halt(target);
1898 } else {
1899 LOG_INFO("Target not halted or running");
1900 retval = ERROR_OK;
1901 break;
1902 }
1903 }
1904
1905 if (retval != ERROR_OK) {
1906 LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1907 return retval;
1908 }
1909
1910
1911 gettimeofday(&now, NULL);
1912 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1913 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1914 break;
1915 }
1916 }
1917
1918 *num_samples = sample_count;
1919 return retval;
1920 }
1921
1922
1923 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1924 * on r/w if the core is not running, and clear on resume or reset ... or
1925 * at least, in a post_restore_context() method.
1926 */
1927
1928 struct dwt_reg_state {
1929 struct target *target;
1930 uint32_t addr;
1931 uint8_t value[4]; /* scratch/cache */
1932 };
1933
1934 static int cortex_m_dwt_get_reg(struct reg *reg)
1935 {
1936 struct dwt_reg_state *state = reg->arch_info;
1937
1938 uint32_t tmp;
1939 int retval = target_read_u32(state->target, state->addr, &tmp);
1940 if (retval != ERROR_OK)
1941 return retval;
1942
1943 buf_set_u32(state->value, 0, 32, tmp);
1944 return ERROR_OK;
1945 }
1946
1947 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1948 {
1949 struct dwt_reg_state *state = reg->arch_info;
1950
1951 return target_write_u32(state->target, state->addr,
1952 buf_get_u32(buf, 0, reg->size));
1953 }
1954
1955 struct dwt_reg {
1956 uint32_t addr;
1957 const char *name;
1958 unsigned size;
1959 };
1960
1961 static const struct dwt_reg dwt_base_regs[] = {
1962 { DWT_CTRL, "dwt_ctrl", 32, },
1963 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1964 * increments while the core is asleep.
1965 */
1966 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1967 /* plus some 8 bit counters, useful for profiling with TPIU */
1968 };
1969
1970 static const struct dwt_reg dwt_comp[] = {
1971 #define DWT_COMPARATOR(i) \
1972 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1973 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1974 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1975 DWT_COMPARATOR(0),
1976 DWT_COMPARATOR(1),
1977 DWT_COMPARATOR(2),
1978 DWT_COMPARATOR(3),
1979 DWT_COMPARATOR(4),
1980 DWT_COMPARATOR(5),
1981 DWT_COMPARATOR(6),
1982 DWT_COMPARATOR(7),
1983 DWT_COMPARATOR(8),
1984 DWT_COMPARATOR(9),
1985 DWT_COMPARATOR(10),
1986 DWT_COMPARATOR(11),
1987 DWT_COMPARATOR(12),
1988 DWT_COMPARATOR(13),
1989 DWT_COMPARATOR(14),
1990 DWT_COMPARATOR(15),
1991 #undef DWT_COMPARATOR
1992 };
1993
1994 static const struct reg_arch_type dwt_reg_type = {
1995 .get = cortex_m_dwt_get_reg,
1996 .set = cortex_m_dwt_set_reg,
1997 };
1998
1999 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
2000 {
2001 struct dwt_reg_state *state;
2002
2003 state = calloc(1, sizeof(*state));
2004 if (!state)
2005 return;
2006 state->addr = d->addr;
2007 state->target = t;
2008
2009 r->name = d->name;
2010 r->size = d->size;
2011 r->value = state->value;
2012 r->arch_info = state;
2013 r->type = &dwt_reg_type;
2014 }
2015
2016 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
2017 {
2018 uint32_t dwtcr;
2019 struct reg_cache *cache;
2020 struct cortex_m_dwt_comparator *comparator;
2021 int reg, i;
2022
2023 target_read_u32(target, DWT_CTRL, &dwtcr);
2024 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
2025 if (!dwtcr) {
2026 LOG_DEBUG("no DWT");
2027 return;
2028 }
2029
2030 target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
2031 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
2032
2033 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
2034 cm->dwt_comp_available = cm->dwt_num_comp;
2035 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
2036 sizeof(struct cortex_m_dwt_comparator));
2037 if (!cm->dwt_comparator_list) {
2038 fail0:
2039 cm->dwt_num_comp = 0;
2040 LOG_ERROR("out of mem");
2041 return;
2042 }
2043
2044 cache = calloc(1, sizeof(*cache));
2045 if (!cache) {
2046 fail1:
2047 free(cm->dwt_comparator_list);
2048 goto fail0;
2049 }
2050 cache->name = "Cortex-M DWT registers";
2051 cache->num_regs = 2 + cm->dwt_num_comp * 3;
2052 cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
2053 if (!cache->reg_list) {
2054 free(cache);
2055 goto fail1;
2056 }
2057
2058 for (reg = 0; reg < 2; reg++)
2059 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2060 dwt_base_regs + reg);
2061
2062 comparator = cm->dwt_comparator_list;
2063 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
2064 int j;
2065
2066 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
2067 for (j = 0; j < 3; j++, reg++)
2068 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2069 dwt_comp + 3 * i + j);
2070
2071 /* make sure we clear any watchpoints enabled on the target */
2072 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
2073 }
2074
2075 *register_get_last_cache_p(&target->reg_cache) = cache;
2076 cm->dwt_cache = cache;
2077
2078 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
2079 dwtcr, cm->dwt_num_comp,
2080 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
2081
2082 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2083 * implement single-address data value watchpoints ... so we
2084 * won't need to check it later, when asked to set one up.
2085 */
2086 }
2087
2088 static void cortex_m_dwt_free(struct target *target)
2089 {
2090 struct cortex_m_common *cm = target_to_cm(target);
2091 struct reg_cache *cache = cm->dwt_cache;
2092
2093 free(cm->dwt_comparator_list);
2094 cm->dwt_comparator_list = NULL;
2095 cm->dwt_num_comp = 0;
2096
2097 if (cache) {
2098 register_unlink_cache(&target->reg_cache, cache);
2099
2100 if (cache->reg_list) {
2101 for (size_t i = 0; i < cache->num_regs; i++)
2102 free(cache->reg_list[i].arch_info);
2103 free(cache->reg_list);
2104 }
2105 free(cache);
2106 }
2107 cm->dwt_cache = NULL;
2108 }
2109
2110 #define MVFR0 0xe000ef40
2111 #define MVFR1 0xe000ef44
2112
2113 #define MVFR0_DEFAULT_M4 0x10110021
2114 #define MVFR1_DEFAULT_M4 0x11000011
2115
2116 #define MVFR0_DEFAULT_M7_SP 0x10110021
2117 #define MVFR0_DEFAULT_M7_DP 0x10110221
2118 #define MVFR1_DEFAULT_M7_SP 0x11000011
2119 #define MVFR1_DEFAULT_M7_DP 0x12000011
2120
2121 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
2122 struct adiv5_ap **debug_ap)
2123 {
2124 if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
2125 return ERROR_OK;
2126
2127 return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
2128 }
2129
2130 int cortex_m_examine(struct target *target)
2131 {
2132 int retval;
2133 uint32_t cpuid, fpcr, mvfr0, mvfr1;
2134 int i;
2135 struct cortex_m_common *cortex_m = target_to_cm(target);
2136 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2137 struct armv7m_common *armv7m = target_to_armv7m(target);
2138
2139 /* stlink shares the examine handler but does not support
2140 * all its calls */
2141 if (!armv7m->stlink) {
2142 if (cortex_m->apsel == DP_APSEL_INVALID) {
2143 /* Search for the MEM-AP */
2144 retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
2145 if (retval != ERROR_OK) {
2146 LOG_ERROR("Could not find MEM-AP to control the core");
2147 return retval;
2148 }
2149 } else {
2150 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2151 }
2152
2153 /* Leave (only) generic DAP stuff for debugport_init(); */
2154 armv7m->debug_ap->memaccess_tck = 8;
2155
2156 retval = mem_ap_init(armv7m->debug_ap);
2157 if (retval != ERROR_OK)
2158 return retval;
2159 }
2160
2161 if (!target_was_examined(target)) {
2162 target_set_examined(target);
2163
2164 /* Read from Device Identification Registers */
2165 retval = target_read_u32(target, CPUID, &cpuid);
2166 if (retval != ERROR_OK)
2167 return retval;
2168
2169 /* Get CPU Type */
2170 i = (cpuid >> 4) & 0xf;
2171
2172 /* Check if it is an ARMv8-M core */
2173 armv7m->arm.is_armv8m = true;
2174
2175 switch (cpuid & ARM_CPUID_PARTNO_MASK) {
2176 case CORTEX_M23_PARTNO:
2177 i = 23;
2178 break;
2179 case CORTEX_M33_PARTNO:
2180 i = 33;
2181 break;
2182 case CORTEX_M35P_PARTNO:
2183 i = 35;
2184 break;
2185 case CORTEX_M55_PARTNO:
2186 i = 55;
2187 break;
2188 default:
2189 armv7m->arm.is_armv8m = false;
2190 break;
2191 }
2192
2193
2194 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2195 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2196 cortex_m->maskints_erratum = false;
2197 if (i == 7) {
2198 uint8_t rev, patch;
2199 rev = (cpuid >> 20) & 0xf;
2200 patch = (cpuid >> 0) & 0xf;
2201 if ((rev == 0) && (patch < 2)) {
2202 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2203 cortex_m->maskints_erratum = true;
2204 }
2205 }
2206 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2207
2208 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2209 cortex_m->vectreset_supported = i > 1;
2210
2211 if (i == 4) {
2212 target_read_u32(target, MVFR0, &mvfr0);
2213 target_read_u32(target, MVFR1, &mvfr1);
2214
2215 /* test for floating point feature on Cortex-M4 */
2216 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2217 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2218 armv7m->fp_feature = FPv4_SP;
2219 }
2220 } else if (i == 7 || i == 33 || i == 35 || i == 55) {
2221 target_read_u32(target, MVFR0, &mvfr0);
2222 target_read_u32(target, MVFR1, &mvfr1);
2223
2224 /* test for floating point features on Cortex-M7 */
2225 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2226 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2227 armv7m->fp_feature = FPv5_SP;
2228 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2229 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2230 armv7m->fp_feature = FPv5_DP;
2231 }
2232 } else if (i == 0) {
2233 /* Cortex-M0 does not support unaligned memory access */
2234 armv7m->arm.is_armv6m = true;
2235 }
2236
2237 if (armv7m->fp_feature == FP_NONE &&
2238 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2239 /* free unavailable FPU registers */
2240 size_t idx;
2241
2242 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2243 idx < armv7m->arm.core_cache->num_regs;
2244 idx++) {
2245 free(armv7m->arm.core_cache->reg_list[idx].value);
2246 free(armv7m->arm.core_cache->reg_list[idx].feature);
2247 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2248 }
2249 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2250 }
2251
2252 if (!armv7m->stlink) {
2253 if (i == 3 || i == 4)
2254 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2255 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2256 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2257 else if (i == 7)
2258 /* Cortex-M7 has only 1024 bytes autoincrement range */
2259 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2260 }
2261
2262 /* Enable debug requests */
2263 retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
2264 if (retval != ERROR_OK)
2265 return retval;
2266 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
2267 uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
2268
2269 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
2270 if (retval != ERROR_OK)
2271 return retval;
2272 cortex_m->dcb_dhcsr = dhcsr;
2273 }
2274
2275 /* Configure trace modules */
2276 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2277 if (retval != ERROR_OK)
2278 return retval;
2279
2280 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2281 armv7m_trace_tpiu_config(target);
2282 armv7m_trace_itm_config(target);
2283 }
2284
2285 /* NOTE: FPB and DWT are both optional. */
2286
2287 /* Setup FPB */
2288 target_read_u32(target, FP_CTRL, &fpcr);
2289 /* bits [14:12] and [7:4] */
2290 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2291 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2292 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2293 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2294 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2295 free(cortex_m->fp_comparator_list);
2296 cortex_m->fp_comparator_list = calloc(
2297 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2298 sizeof(struct cortex_m_fp_comparator));
2299 cortex_m->fpb_enabled = fpcr & 1;
2300 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2301 cortex_m->fp_comparator_list[i].type =
2302 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2303 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2304
2305 /* make sure we clear any breakpoints enabled on the target */
2306 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2307 }
2308 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2309 fpcr,
2310 cortex_m->fp_num_code,
2311 cortex_m->fp_num_lit);
2312
2313 /* Setup DWT */
2314 cortex_m_dwt_free(target);
2315 cortex_m_dwt_setup(cortex_m, target);
2316
2317 /* These hardware breakpoints only work for code in flash! */
2318 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2319 target_name(target),
2320 cortex_m->fp_num_code,
2321 cortex_m->dwt_num_comp);
2322 }
2323
2324 return ERROR_OK;
2325 }
2326
2327 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2328 {
2329 struct armv7m_common *armv7m = target_to_armv7m(target);
2330 uint16_t dcrdr;
2331 uint8_t buf[2];
2332 int retval;
2333
2334 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2335 if (retval != ERROR_OK)
2336 return retval;
2337
2338 dcrdr = target_buffer_get_u16(target, buf);
2339 *ctrl = (uint8_t)dcrdr;
2340 *value = (uint8_t)(dcrdr >> 8);
2341
2342 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2343
2344 /* write ack back to software dcc register
2345 * signify we have read data */
2346 if (dcrdr & (1 << 0)) {
2347 target_buffer_set_u16(target, buf, 0);
2348 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2349 if (retval != ERROR_OK)
2350 return retval;
2351 }
2352
2353 return ERROR_OK;
2354 }
2355
2356 static int cortex_m_target_request_data(struct target *target,
2357 uint32_t size, uint8_t *buffer)
2358 {
2359 uint8_t data;
2360 uint8_t ctrl;
2361 uint32_t i;
2362
2363 for (i = 0; i < (size * 4); i++) {
2364 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2365 if (retval != ERROR_OK)
2366 return retval;
2367 buffer[i] = data;
2368 }
2369
2370 return ERROR_OK;
2371 }
2372
2373 static int cortex_m_handle_target_request(void *priv)
2374 {
2375 struct target *target = priv;
2376 if (!target_was_examined(target))
2377 return ERROR_OK;
2378
2379 if (!target->dbg_msg_enabled)
2380 return ERROR_OK;
2381
2382 if (target->state == TARGET_RUNNING) {
2383 uint8_t data;
2384 uint8_t ctrl;
2385 int retval;
2386
2387 retval = cortex_m_dcc_read(target, &data, &ctrl);
2388 if (retval != ERROR_OK)
2389 return retval;
2390
2391 /* check if we have data */
2392 if (ctrl & (1 << 0)) {
2393 uint32_t request;
2394
2395 /* we assume target is quick enough */
2396 request = data;
2397 for (int i = 1; i <= 3; i++) {
2398 retval = cortex_m_dcc_read(target, &data, &ctrl);
2399 if (retval != ERROR_OK)
2400 return retval;
2401 request |= ((uint32_t)data << (i * 8));
2402 }
2403 target_request(target, request);
2404 }
2405 }
2406
2407 return ERROR_OK;
2408 }
2409
2410 static int cortex_m_init_arch_info(struct target *target,
2411 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2412 {
2413 struct armv7m_common *armv7m = &cortex_m->armv7m;
2414
2415 armv7m_init_arch_info(target, armv7m);
2416
2417 /* default reset mode is to use srst if fitted
2418 * if not it will use CORTEX_M3_RESET_VECTRESET */
2419 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2420
2421 armv7m->arm.dap = dap;
2422
2423 /* register arch-specific functions */
2424 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2425
2426 armv7m->post_debug_entry = NULL;
2427
2428 armv7m->pre_restore_context = NULL;
2429
2430 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2431 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2432
2433 target_register_timer_callback(cortex_m_handle_target_request, 1,
2434 TARGET_TIMER_TYPE_PERIODIC, target);
2435
2436 return ERROR_OK;
2437 }
2438
2439 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2440 {
2441 struct adiv5_private_config *pc;
2442
2443 pc = (struct adiv5_private_config *)target->private_config;
2444 if (adiv5_verify_config(pc) != ERROR_OK)
2445 return ERROR_FAIL;
2446
2447 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2448 if (cortex_m == NULL) {
2449 LOG_ERROR("No memory creating target");
2450 return ERROR_FAIL;
2451 }
2452
2453 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2454 cortex_m->apsel = pc->ap_num;
2455
2456 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2457
2458 return ERROR_OK;
2459 }
2460
2461 /*--------------------------------------------------------------------------*/
2462
2463 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2464 struct cortex_m_common *cm)
2465 {
2466 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2467 command_print(cmd, "target is not a Cortex-M");
2468 return ERROR_TARGET_INVALID;
2469 }
2470 return ERROR_OK;
2471 }
2472
2473 /*
2474 * Only stuff below this line should need to verify that its target
2475 * is a Cortex-M3. Everything else should have indirected through the
2476 * cortexm3_target structure, which is only used with CM3 targets.
2477 */
2478
2479 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2480 {
2481 struct target *target = get_current_target(CMD_CTX);
2482 struct cortex_m_common *cortex_m = target_to_cm(target);
2483 struct armv7m_common *armv7m = &cortex_m->armv7m;
2484 uint32_t demcr = 0;
2485 int retval;
2486
2487 static const struct {
2488 char name[10];
2489 unsigned mask;
2490 } vec_ids[] = {
2491 { "hard_err", VC_HARDERR, },
2492 { "int_err", VC_INTERR, },
2493 { "bus_err", VC_BUSERR, },
2494 { "state_err", VC_STATERR, },
2495 { "chk_err", VC_CHKERR, },
2496 { "nocp_err", VC_NOCPERR, },
2497 { "mm_err", VC_MMERR, },
2498 { "reset", VC_CORERESET, },
2499 };
2500
2501 retval = cortex_m_verify_pointer(CMD, cortex_m);
2502 if (retval != ERROR_OK)
2503 return retval;
2504
2505 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2506 if (retval != ERROR_OK)
2507 return retval;
2508
2509 if (CMD_ARGC > 0) {
2510 unsigned catch = 0;
2511
2512 if (CMD_ARGC == 1) {
2513 if (strcmp(CMD_ARGV[0], "all") == 0) {
2514 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2515 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2516 | VC_MMERR | VC_CORERESET;
2517 goto write;
2518 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2519 goto write;
2520 }
2521 while (CMD_ARGC-- > 0) {
2522 unsigned i;
2523 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2524 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2525 continue;
2526 catch |= vec_ids[i].mask;
2527 break;
2528 }
2529 if (i == ARRAY_SIZE(vec_ids)) {
2530 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2531 return ERROR_COMMAND_SYNTAX_ERROR;
2532 }
2533 }
2534 write:
2535 /* For now, armv7m->demcr only stores vector catch flags. */
2536 armv7m->demcr = catch;
2537
2538 demcr &= ~0xffff;
2539 demcr |= catch;
2540
2541 /* write, but don't assume it stuck (why not??) */
2542 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2543 if (retval != ERROR_OK)
2544 return retval;
2545 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2546 if (retval != ERROR_OK)
2547 return retval;
2548
2549 /* FIXME be sure to clear DEMCR on clean server shutdown.
2550 * Otherwise the vector catch hardware could fire when there's
2551 * no debugger hooked up, causing much confusion...
2552 */
2553 }
2554
2555 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2556 command_print(CMD, "%9s: %s", vec_ids[i].name,
2557 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2558 }
2559
2560 return ERROR_OK;
2561 }
2562
2563 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2564 {
2565 struct target *target = get_current_target(CMD_CTX);
2566 struct cortex_m_common *cortex_m = target_to_cm(target);
2567 int retval;
2568
2569 static const Jim_Nvp nvp_maskisr_modes[] = {
2570 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2571 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2572 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2573 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2574 { .name = NULL, .value = -1 },
2575 };
2576 const Jim_Nvp *n;
2577
2578
2579 retval = cortex_m_verify_pointer(CMD, cortex_m);
2580 if (retval != ERROR_OK)
2581 return retval;
2582
2583 if (target->state != TARGET_HALTED) {
2584 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2585 return ERROR_OK;
2586 }
2587
2588 if (CMD_ARGC > 0) {
2589 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2590 if (n->name == NULL)
2591 return ERROR_COMMAND_SYNTAX_ERROR;
2592 cortex_m->isrmasking_mode = n->value;
2593 cortex_m_set_maskints_for_halt(target);
2594 }
2595
2596 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2597 command_print(CMD, "cortex_m interrupt mask %s", n->name);
2598
2599 return ERROR_OK;
2600 }
2601
2602 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2603 {
2604 struct target *target = get_current_target(CMD_CTX);
2605 struct cortex_m_common *cortex_m = target_to_cm(target);
2606 int retval;
2607 char *reset_config;
2608
2609 retval = cortex_m_verify_pointer(CMD, cortex_m);
2610 if (retval != ERROR_OK)
2611 return retval;
2612
2613 if (CMD_ARGC > 0) {
2614 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2615 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2616
2617 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2618 if (target_was_examined(target)
2619 && !cortex_m->vectreset_supported)
2620 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2621 else
2622 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2623
2624 } else
2625 return ERROR_COMMAND_SYNTAX_ERROR;
2626 }
2627
2628 switch (cortex_m->soft_reset_config) {
2629 case CORTEX_M_RESET_SYSRESETREQ:
2630 reset_config = "sysresetreq";
2631 break;
2632
2633 case CORTEX_M_RESET_VECTRESET:
2634 reset_config = "vectreset";
2635 break;
2636
2637 default:
2638 reset_config = "unknown";
2639 break;
2640 }
2641
2642 command_print(CMD, "cortex_m reset_config %s", reset_config);
2643
2644 return ERROR_OK;
2645 }
2646
2647 static const struct command_registration cortex_m_exec_command_handlers[] = {
2648 {
2649 .name = "maskisr",
2650 .handler = handle_cortex_m_mask_interrupts_command,
2651 .mode = COMMAND_EXEC,
2652 .help = "mask cortex_m interrupts",
2653 .usage = "['auto'|'on'|'off'|'steponly']",
2654 },
2655 {
2656 .name = "vector_catch",
2657 .handler = handle_cortex_m_vector_catch_command,
2658 .mode = COMMAND_EXEC,
2659 .help = "configure hardware vectors to trigger debug entry",
2660 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2661 },
2662 {
2663 .name = "reset_config",
2664 .handler = handle_cortex_m_reset_config_command,
2665 .mode = COMMAND_ANY,
2666 .help = "configure software reset handling",
2667 .usage = "['sysresetreq'|'vectreset']",
2668 },
2669 COMMAND_REGISTRATION_DONE
2670 };
2671 static const struct command_registration cortex_m_command_handlers[] = {
2672 {
2673 .chain = armv7m_command_handlers,
2674 },
2675 {
2676 .chain = armv7m_trace_command_handlers,
2677 },
2678 {
2679 .name = "cortex_m",
2680 .mode = COMMAND_EXEC,
2681 .help = "Cortex-M command group",
2682 .usage = "",
2683 .chain = cortex_m_exec_command_handlers,
2684 },
2685 COMMAND_REGISTRATION_DONE
2686 };
2687
2688 struct target_type cortexm_target = {
2689 .name = "cortex_m",
2690 .deprecated_name = "cortex_m3",
2691
2692 .poll = cortex_m_poll,
2693 .arch_state = armv7m_arch_state,
2694
2695 .target_request_data = cortex_m_target_request_data,
2696
2697 .halt = cortex_m_halt,
2698 .resume = cortex_m_resume,
2699 .step = cortex_m_step,
2700
2701 .assert_reset = cortex_m_assert_reset,
2702 .deassert_reset = cortex_m_deassert_reset,
2703 .soft_reset_halt = cortex_m_soft_reset_halt,
2704
2705 .get_gdb_arch = arm_get_gdb_arch,
2706 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2707
2708 .read_memory = cortex_m_read_memory,
2709 .write_memory = cortex_m_write_memory,
2710 .checksum_memory = armv7m_checksum_memory,
2711 .blank_check_memory = armv7m_blank_check_memory,
2712
2713 .run_algorithm = armv7m_run_algorithm,
2714 .start_algorithm = armv7m_start_algorithm,
2715 .wait_algorithm = armv7m_wait_algorithm,
2716
2717 .add_breakpoint = cortex_m_add_breakpoint,
2718 .remove_breakpoint = cortex_m_remove_breakpoint,
2719 .add_watchpoint = cortex_m_add_watchpoint,
2720 .remove_watchpoint = cortex_m_remove_watchpoint,
2721
2722 .commands = cortex_m_command_handlers,
2723 .target_create = cortex_m_target_create,
2724 .target_jim_configure = adiv5_jim_configure,
2725 .init_target = cortex_m_init_target,
2726 .examine = cortex_m_examine,
2727 .deinit_target = cortex_m_deinit_target,
2728
2729 .profiling = cortex_m_profiling,
2730 };