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target/cortex_m: remove dependency from jtag queue
[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortexm_dap_read_coreregister_u32(struct target *target,
60 uint32_t *value, int regnum)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortexm_dap_write_coreregister_u32(struct target *target,
93 uint32_t value, int regnum)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_set_maskints(struct target *target, bool mask)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
143 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
144 else
145 return ERROR_OK;
146 }
147
148 static int cortex_m_set_maskints_for_halt(struct target *target)
149 {
150 struct cortex_m_common *cortex_m = target_to_cm(target);
151 switch (cortex_m->isrmasking_mode) {
152 case CORTEX_M_ISRMASK_AUTO:
153 /* interrupts taken at resume, whether for step or run -> no mask */
154 return cortex_m_set_maskints(target, false);
155
156 case CORTEX_M_ISRMASK_OFF:
157 /* interrupts never masked */
158 return cortex_m_set_maskints(target, false);
159
160 case CORTEX_M_ISRMASK_ON:
161 /* interrupts always masked */
162 return cortex_m_set_maskints(target, true);
163
164 case CORTEX_M_ISRMASK_STEPONLY:
165 /* interrupts masked for single step only -> mask now if MASKINTS
166 * erratum, otherwise only mask before stepping */
167 return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
168 }
169 return ERROR_OK;
170 }
171
172 static int cortex_m_set_maskints_for_run(struct target *target)
173 {
174 switch (target_to_cm(target)->isrmasking_mode) {
175 case CORTEX_M_ISRMASK_AUTO:
176 /* interrupts taken at resume, whether for step or run -> no mask */
177 return cortex_m_set_maskints(target, false);
178
179 case CORTEX_M_ISRMASK_OFF:
180 /* interrupts never masked */
181 return cortex_m_set_maskints(target, false);
182
183 case CORTEX_M_ISRMASK_ON:
184 /* interrupts always masked */
185 return cortex_m_set_maskints(target, true);
186
187 case CORTEX_M_ISRMASK_STEPONLY:
188 /* interrupts masked for single step only -> no mask */
189 return cortex_m_set_maskints(target, false);
190 }
191 return ERROR_OK;
192 }
193
194 static int cortex_m_set_maskints_for_step(struct target *target)
195 {
196 switch (target_to_cm(target)->isrmasking_mode) {
197 case CORTEX_M_ISRMASK_AUTO:
198 /* the auto-interrupt should already be done -> mask */
199 return cortex_m_set_maskints(target, true);
200
201 case CORTEX_M_ISRMASK_OFF:
202 /* interrupts never masked */
203 return cortex_m_set_maskints(target, false);
204
205 case CORTEX_M_ISRMASK_ON:
206 /* interrupts always masked */
207 return cortex_m_set_maskints(target, true);
208
209 case CORTEX_M_ISRMASK_STEPONLY:
210 /* interrupts masked for single step only -> mask */
211 return cortex_m_set_maskints(target, true);
212 }
213 return ERROR_OK;
214 }
215
216 static int cortex_m_clear_halt(struct target *target)
217 {
218 struct cortex_m_common *cortex_m = target_to_cm(target);
219 struct armv7m_common *armv7m = &cortex_m->armv7m;
220 int retval;
221
222 /* clear step if any */
223 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
224
225 /* Read Debug Fault Status Register */
226 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Clear Debug Fault Status */
231 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
232 if (retval != ERROR_OK)
233 return retval;
234 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
235
236 return ERROR_OK;
237 }
238
239 static int cortex_m_single_step_core(struct target *target)
240 {
241 struct cortex_m_common *cortex_m = target_to_cm(target);
242 struct armv7m_common *armv7m = &cortex_m->armv7m;
243 int retval;
244
245 /* Mask interrupts before clearing halt, if not done already. This avoids
246 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
247 * HALT can put the core into an unknown state.
248 */
249 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
250 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
251 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
252 if (retval != ERROR_OK)
253 return retval;
254 }
255 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
256 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
257 if (retval != ERROR_OK)
258 return retval;
259 LOG_DEBUG(" ");
260
261 /* restore dhcsr reg */
262 cortex_m_clear_halt(target);
263
264 return ERROR_OK;
265 }
266
267 static int cortex_m_enable_fpb(struct target *target)
268 {
269 int retval = target_write_u32(target, FP_CTRL, 3);
270 if (retval != ERROR_OK)
271 return retval;
272
273 /* check the fpb is actually enabled */
274 uint32_t fpctrl;
275 retval = target_read_u32(target, FP_CTRL, &fpctrl);
276 if (retval != ERROR_OK)
277 return retval;
278
279 if (fpctrl & 1)
280 return ERROR_OK;
281
282 return ERROR_FAIL;
283 }
284
285 static int cortex_m_endreset_event(struct target *target)
286 {
287 int i;
288 int retval;
289 uint32_t dcb_demcr;
290 struct cortex_m_common *cortex_m = target_to_cm(target);
291 struct armv7m_common *armv7m = &cortex_m->armv7m;
292 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
293 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
294 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
295
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
298 if (retval != ERROR_OK)
299 return retval;
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
301
302 /* this register is used for emulated dcc channel */
303 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
304 if (retval != ERROR_OK)
305 return retval;
306
307 /* Enable debug requests */
308 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
309 if (retval != ERROR_OK)
310 return retval;
311 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
312 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
313 if (retval != ERROR_OK)
314 return retval;
315 }
316
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target);
319
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
322 *
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
326 */
327 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
328 if (retval != ERROR_OK)
329 return retval;
330
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
333 */
334
335 /* Enable FPB */
336 retval = cortex_m_enable_fpb(target);
337 if (retval != ERROR_OK) {
338 LOG_ERROR("Failed to enable the FPB");
339 return retval;
340 }
341
342 cortex_m->fpb_enabled = true;
343
344 /* Restore FPB registers */
345 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
346 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350
351 /* Restore DWT registers */
352 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
353 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
354 dwt_list[i].comp);
355 if (retval != ERROR_OK)
356 return retval;
357 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
358 dwt_list[i].mask);
359 if (retval != ERROR_OK)
360 return retval;
361 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
362 dwt_list[i].function);
363 if (retval != ERROR_OK)
364 return retval;
365 }
366 retval = dap_run(swjdp);
367 if (retval != ERROR_OK)
368 return retval;
369
370 register_cache_invalidate(armv7m->arm.core_cache);
371
372 /* make sure we have latest dhcsr flags */
373 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
374
375 return retval;
376 }
377
378 static int cortex_m_examine_debug_reason(struct target *target)
379 {
380 struct cortex_m_common *cortex_m = target_to_cm(target);
381
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
384
385 if ((target->debug_reason != DBG_REASON_DBGRQ)
386 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
387 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
388 target->debug_reason = DBG_REASON_BREAKPOINT;
389 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
390 target->debug_reason = DBG_REASON_WPTANDBKPT;
391 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
392 target->debug_reason = DBG_REASON_WATCHPOINT;
393 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
394 target->debug_reason = DBG_REASON_BREAKPOINT;
395 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
396 target->debug_reason = DBG_REASON_DBGRQ;
397 else /* HALTED */
398 target->debug_reason = DBG_REASON_UNDEFINED;
399 }
400
401 return ERROR_OK;
402 }
403
404 static int cortex_m_examine_exception_reason(struct target *target)
405 {
406 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
407 struct armv7m_common *armv7m = target_to_armv7m(target);
408 struct adiv5_dap *swjdp = armv7m->arm.dap;
409 int retval;
410
411 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
412 if (retval != ERROR_OK)
413 return retval;
414 switch (armv7m->exception_number) {
415 case 2: /* NMI */
416 break;
417 case 3: /* Hard Fault */
418 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
419 if (retval != ERROR_OK)
420 return retval;
421 if (except_sr & 0x40000000) {
422 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
423 if (retval != ERROR_OK)
424 return retval;
425 }
426 break;
427 case 4: /* Memory Management */
428 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
429 if (retval != ERROR_OK)
430 return retval;
431 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
432 if (retval != ERROR_OK)
433 return retval;
434 break;
435 case 5: /* Bus Fault */
436 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
437 if (retval != ERROR_OK)
438 return retval;
439 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
440 if (retval != ERROR_OK)
441 return retval;
442 break;
443 case 6: /* Usage Fault */
444 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
445 if (retval != ERROR_OK)
446 return retval;
447 break;
448 case 11: /* SVCall */
449 break;
450 case 12: /* Debug Monitor */
451 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
452 if (retval != ERROR_OK)
453 return retval;
454 break;
455 case 14: /* PendSV */
456 break;
457 case 15: /* SysTick */
458 break;
459 default:
460 except_sr = 0;
461 break;
462 }
463 retval = dap_run(swjdp);
464 if (retval == ERROR_OK)
465 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
466 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
467 armv7m_exception_string(armv7m->exception_number),
468 shcsr, except_sr, cfsr, except_ar);
469 return retval;
470 }
471
472 static int cortex_m_debug_entry(struct target *target)
473 {
474 int i;
475 uint32_t xPSR;
476 int retval;
477 struct cortex_m_common *cortex_m = target_to_cm(target);
478 struct armv7m_common *armv7m = &cortex_m->armv7m;
479 struct arm *arm = &armv7m->arm;
480 struct reg *r;
481
482 LOG_DEBUG(" ");
483
484 /* Do this really early to minimize the window where the MASKINTS erratum
485 * can pile up pending interrupts. */
486 cortex_m_set_maskints_for_halt(target);
487
488 cortex_m_clear_halt(target);
489 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
490 if (retval != ERROR_OK)
491 return retval;
492
493 retval = armv7m->examine_debug_reason(target);
494 if (retval != ERROR_OK)
495 return retval;
496
497 /* Examine target state and mode
498 * First load register accessible through core debug port */
499 int num_regs = arm->core_cache->num_regs;
500
501 for (i = 0; i < num_regs; i++) {
502 r = &armv7m->arm.core_cache->reg_list[i];
503 if (!r->valid)
504 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
505 }
506
507 r = arm->cpsr;
508 xPSR = buf_get_u32(r->value, 0, 32);
509
510 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
511 if (xPSR & 0xf00) {
512 r->dirty = r->valid;
513 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
514 }
515
516 /* Are we in an exception handler */
517 if (xPSR & 0x1FF) {
518 armv7m->exception_number = (xPSR & 0x1FF);
519
520 arm->core_mode = ARM_MODE_HANDLER;
521 arm->map = armv7m_msp_reg_map;
522 } else {
523 unsigned control = buf_get_u32(arm->core_cache
524 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
525
526 /* is this thread privileged? */
527 arm->core_mode = control & 1
528 ? ARM_MODE_USER_THREAD
529 : ARM_MODE_THREAD;
530
531 /* which stack is it using? */
532 if (control & 2)
533 arm->map = armv7m_psp_reg_map;
534 else
535 arm->map = armv7m_msp_reg_map;
536
537 armv7m->exception_number = 0;
538 }
539
540 if (armv7m->exception_number)
541 cortex_m_examine_exception_reason(target);
542
543 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
544 arm_mode_name(arm->core_mode),
545 buf_get_u32(arm->pc->value, 0, 32),
546 target_state_name(target));
547
548 if (armv7m->post_debug_entry) {
549 retval = armv7m->post_debug_entry(target);
550 if (retval != ERROR_OK)
551 return retval;
552 }
553
554 return ERROR_OK;
555 }
556
557 static int cortex_m_poll(struct target *target)
558 {
559 int detected_failure = ERROR_OK;
560 int retval = ERROR_OK;
561 enum target_state prev_target_state = target->state;
562 struct cortex_m_common *cortex_m = target_to_cm(target);
563 struct armv7m_common *armv7m = &cortex_m->armv7m;
564
565 /* Read from Debug Halting Control and Status Register */
566 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
567 if (retval != ERROR_OK) {
568 target->state = TARGET_UNKNOWN;
569 return retval;
570 }
571
572 /* Recover from lockup. See ARMv7-M architecture spec,
573 * section B1.5.15 "Unrecoverable exception cases".
574 */
575 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
576 LOG_ERROR("%s -- clearing lockup after double fault",
577 target_name(target));
578 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
579 target->debug_reason = DBG_REASON_DBGRQ;
580
581 /* We have to execute the rest (the "finally" equivalent, but
582 * still throw this exception again).
583 */
584 detected_failure = ERROR_FAIL;
585
586 /* refresh status bits */
587 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
588 if (retval != ERROR_OK)
589 return retval;
590 }
591
592 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
593 if (target->state != TARGET_RESET) {
594 target->state = TARGET_RESET;
595 LOG_INFO("%s: external reset detected", target_name(target));
596 }
597 return ERROR_OK;
598 }
599
600 if (target->state == TARGET_RESET) {
601 /* Cannot switch context while running so endreset is
602 * called with target->state == TARGET_RESET
603 */
604 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
605 cortex_m->dcb_dhcsr);
606 retval = cortex_m_endreset_event(target);
607 if (retval != ERROR_OK) {
608 target->state = TARGET_UNKNOWN;
609 return retval;
610 }
611 target->state = TARGET_RUNNING;
612 prev_target_state = TARGET_RUNNING;
613 }
614
615 if (cortex_m->dcb_dhcsr & S_HALT) {
616 target->state = TARGET_HALTED;
617
618 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
619 retval = cortex_m_debug_entry(target);
620 if (retval != ERROR_OK)
621 return retval;
622
623 if (arm_semihosting(target, &retval) != 0)
624 return retval;
625
626 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
627 }
628 if (prev_target_state == TARGET_DEBUG_RUNNING) {
629 LOG_DEBUG(" ");
630 retval = cortex_m_debug_entry(target);
631 if (retval != ERROR_OK)
632 return retval;
633
634 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
635 }
636 }
637
638 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
639 * How best to model low power modes?
640 */
641
642 if (target->state == TARGET_UNKNOWN) {
643 /* check if processor is retiring instructions */
644 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
645 target->state = TARGET_RUNNING;
646 retval = ERROR_OK;
647 }
648 }
649
650 /* Check that target is truly halted, since the target could be resumed externally */
651 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
652 /* registers are now invalid */
653 register_cache_invalidate(armv7m->arm.core_cache);
654
655 target->state = TARGET_RUNNING;
656 LOG_WARNING("%s: external resume detected", target_name(target));
657 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
658 retval = ERROR_OK;
659 }
660
661 /* Did we detect a failure condition that we cleared? */
662 if (detected_failure != ERROR_OK)
663 retval = detected_failure;
664 return retval;
665 }
666
667 static int cortex_m_halt(struct target *target)
668 {
669 LOG_DEBUG("target->state: %s",
670 target_state_name(target));
671
672 if (target->state == TARGET_HALTED) {
673 LOG_DEBUG("target was already halted");
674 return ERROR_OK;
675 }
676
677 if (target->state == TARGET_UNKNOWN)
678 LOG_WARNING("target was in unknown state when halt was requested");
679
680 if (target->state == TARGET_RESET) {
681 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
682 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
683 return ERROR_TARGET_FAILURE;
684 } else {
685 /* we came here in a reset_halt or reset_init sequence
686 * debug entry was already prepared in cortex_m3_assert_reset()
687 */
688 target->debug_reason = DBG_REASON_DBGRQ;
689
690 return ERROR_OK;
691 }
692 }
693
694 /* Write to Debug Halting Control and Status Register */
695 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
696
697 /* Do this really early to minimize the window where the MASKINTS erratum
698 * can pile up pending interrupts. */
699 cortex_m_set_maskints_for_halt(target);
700
701 target->debug_reason = DBG_REASON_DBGRQ;
702
703 return ERROR_OK;
704 }
705
706 static int cortex_m_soft_reset_halt(struct target *target)
707 {
708 struct cortex_m_common *cortex_m = target_to_cm(target);
709 struct armv7m_common *armv7m = &cortex_m->armv7m;
710 uint32_t dcb_dhcsr = 0;
711 int retval, timeout = 0;
712
713 /* soft_reset_halt is deprecated on cortex_m as the same functionality
714 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
715 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
716 * core, not the peripherals */
717 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
718
719 /* Enter debug state on reset; restore DEMCR in endreset_event() */
720 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
721 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
722 if (retval != ERROR_OK)
723 return retval;
724
725 /* Request a core-only reset */
726 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
727 AIRCR_VECTKEY | AIRCR_VECTRESET);
728 if (retval != ERROR_OK)
729 return retval;
730 target->state = TARGET_RESET;
731
732 /* registers are now invalid */
733 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
734
735 while (timeout < 100) {
736 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
737 if (retval == ERROR_OK) {
738 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
739 &cortex_m->nvic_dfsr);
740 if (retval != ERROR_OK)
741 return retval;
742 if ((dcb_dhcsr & S_HALT)
743 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
744 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
745 "DFSR 0x%08x",
746 (unsigned) dcb_dhcsr,
747 (unsigned) cortex_m->nvic_dfsr);
748 cortex_m_poll(target);
749 /* FIXME restore user's vector catch config */
750 return ERROR_OK;
751 } else
752 LOG_DEBUG("waiting for system reset-halt, "
753 "DHCSR 0x%08x, %d ms",
754 (unsigned) dcb_dhcsr, timeout);
755 }
756 timeout++;
757 alive_sleep(1);
758 }
759
760 return ERROR_OK;
761 }
762
763 void cortex_m_enable_breakpoints(struct target *target)
764 {
765 struct breakpoint *breakpoint = target->breakpoints;
766
767 /* set any pending breakpoints */
768 while (breakpoint) {
769 if (!breakpoint->set)
770 cortex_m_set_breakpoint(target, breakpoint);
771 breakpoint = breakpoint->next;
772 }
773 }
774
775 static int cortex_m_resume(struct target *target, int current,
776 target_addr_t address, int handle_breakpoints, int debug_execution)
777 {
778 struct armv7m_common *armv7m = target_to_armv7m(target);
779 struct breakpoint *breakpoint = NULL;
780 uint32_t resume_pc;
781 struct reg *r;
782
783 if (target->state != TARGET_HALTED) {
784 LOG_WARNING("target not halted");
785 return ERROR_TARGET_NOT_HALTED;
786 }
787
788 if (!debug_execution) {
789 target_free_all_working_areas(target);
790 cortex_m_enable_breakpoints(target);
791 cortex_m_enable_watchpoints(target);
792 }
793
794 if (debug_execution) {
795 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
796
797 /* Disable interrupts */
798 /* We disable interrupts in the PRIMASK register instead of
799 * masking with C_MASKINTS. This is probably the same issue
800 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
801 * in parallel with disabled interrupts can cause local faults
802 * to not be taken.
803 *
804 * REVISIT this clearly breaks non-debug execution, since the
805 * PRIMASK register state isn't saved/restored... workaround
806 * by never resuming app code after debug execution.
807 */
808 buf_set_u32(r->value, 0, 1, 1);
809 r->dirty = true;
810 r->valid = true;
811
812 /* Make sure we are in Thumb mode */
813 r = armv7m->arm.cpsr;
814 buf_set_u32(r->value, 24, 1, 1);
815 r->dirty = true;
816 r->valid = true;
817 }
818
819 /* current = 1: continue on current pc, otherwise continue at <address> */
820 r = armv7m->arm.pc;
821 if (!current) {
822 buf_set_u32(r->value, 0, 32, address);
823 r->dirty = true;
824 r->valid = true;
825 }
826
827 /* if we halted last time due to a bkpt instruction
828 * then we have to manually step over it, otherwise
829 * the core will break again */
830
831 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
832 && !debug_execution)
833 armv7m_maybe_skip_bkpt_inst(target, NULL);
834
835 resume_pc = buf_get_u32(r->value, 0, 32);
836
837 armv7m_restore_context(target);
838
839 /* the front-end may request us not to handle breakpoints */
840 if (handle_breakpoints) {
841 /* Single step past breakpoint at current address */
842 breakpoint = breakpoint_find(target, resume_pc);
843 if (breakpoint) {
844 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
845 breakpoint->address,
846 breakpoint->unique_id);
847 cortex_m_unset_breakpoint(target, breakpoint);
848 cortex_m_single_step_core(target);
849 cortex_m_set_breakpoint(target, breakpoint);
850 }
851 }
852
853 /* Restart core */
854 cortex_m_set_maskints_for_run(target);
855 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
856
857 target->debug_reason = DBG_REASON_NOTHALTED;
858
859 /* registers are now invalid */
860 register_cache_invalidate(armv7m->arm.core_cache);
861
862 if (!debug_execution) {
863 target->state = TARGET_RUNNING;
864 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
865 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
866 } else {
867 target->state = TARGET_DEBUG_RUNNING;
868 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
869 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
870 }
871
872 return ERROR_OK;
873 }
874
875 /* int irqstepcount = 0; */
876 static int cortex_m_step(struct target *target, int current,
877 target_addr_t address, int handle_breakpoints)
878 {
879 struct cortex_m_common *cortex_m = target_to_cm(target);
880 struct armv7m_common *armv7m = &cortex_m->armv7m;
881 struct breakpoint *breakpoint = NULL;
882 struct reg *pc = armv7m->arm.pc;
883 bool bkpt_inst_found = false;
884 int retval;
885 bool isr_timed_out = false;
886
887 if (target->state != TARGET_HALTED) {
888 LOG_WARNING("target not halted");
889 return ERROR_TARGET_NOT_HALTED;
890 }
891
892 /* current = 1: continue on current pc, otherwise continue at <address> */
893 if (!current)
894 buf_set_u32(pc->value, 0, 32, address);
895
896 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
897
898 /* the front-end may request us not to handle breakpoints */
899 if (handle_breakpoints) {
900 breakpoint = breakpoint_find(target, pc_value);
901 if (breakpoint)
902 cortex_m_unset_breakpoint(target, breakpoint);
903 }
904
905 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
906
907 target->debug_reason = DBG_REASON_SINGLESTEP;
908
909 armv7m_restore_context(target);
910
911 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
912
913 /* if no bkpt instruction is found at pc then we can perform
914 * a normal step, otherwise we have to manually step over the bkpt
915 * instruction - as such simulate a step */
916 if (bkpt_inst_found == false) {
917 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO)) {
918 /* Automatic ISR masking mode off: Just step over the next
919 * instruction, with interrupts on or off as appropriate. */
920 cortex_m_set_maskints_for_step(target);
921 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
922 } else {
923 /* Process interrupts during stepping in a way they don't interfere
924 * debugging.
925 *
926 * Principle:
927 *
928 * Set a temporary break point at the current pc and let the core run
929 * with interrupts enabled. Pending interrupts get served and we run
930 * into the breakpoint again afterwards. Then we step over the next
931 * instruction with interrupts disabled.
932 *
933 * If the pending interrupts don't complete within time, we leave the
934 * core running. This may happen if the interrupts trigger faster
935 * than the core can process them or the handler doesn't return.
936 *
937 * If no more breakpoints are available we simply do a step with
938 * interrupts enabled.
939 *
940 */
941
942 /* 2012-09-29 ph
943 *
944 * If a break point is already set on the lower half word then a break point on
945 * the upper half word will not break again when the core is restarted. So we
946 * just step over the instruction with interrupts disabled.
947 *
948 * The documentation has no information about this, it was found by observation
949 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
950 * suffer from this problem.
951 *
952 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
953 * address has it always cleared. The former is done to indicate thumb mode
954 * to gdb.
955 *
956 */
957 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
958 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
959 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
960 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
961 /* Re-enable interrupts if appropriate */
962 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
963 cortex_m_set_maskints_for_halt(target);
964 }
965 else {
966
967 /* Set a temporary break point */
968 if (breakpoint) {
969 retval = cortex_m_set_breakpoint(target, breakpoint);
970 } else {
971 enum breakpoint_type type = BKPT_HARD;
972 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
973 /* FPB rev.1 cannot handle such addr, try BKPT instr */
974 type = BKPT_SOFT;
975 }
976 retval = breakpoint_add(target, pc_value, 2, type);
977 }
978
979 bool tmp_bp_set = (retval == ERROR_OK);
980
981 /* No more breakpoints left, just do a step */
982 if (!tmp_bp_set) {
983 cortex_m_set_maskints_for_step(target);
984 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
985 /* Re-enable interrupts if appropriate */
986 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
987 cortex_m_set_maskints_for_halt(target);
988 } else {
989 /* Start the core */
990 LOG_DEBUG("Starting core to serve pending interrupts");
991 int64_t t_start = timeval_ms();
992 cortex_m_set_maskints_for_run(target);
993 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
994
995 /* Wait for pending handlers to complete or timeout */
996 do {
997 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
998 DCB_DHCSR,
999 &cortex_m->dcb_dhcsr);
1000 if (retval != ERROR_OK) {
1001 target->state = TARGET_UNKNOWN;
1002 return retval;
1003 }
1004 isr_timed_out = ((timeval_ms() - t_start) > 500);
1005 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1006
1007 /* only remove breakpoint if we created it */
1008 if (breakpoint)
1009 cortex_m_unset_breakpoint(target, breakpoint);
1010 else {
1011 /* Remove the temporary breakpoint */
1012 breakpoint_remove(target, pc_value);
1013 }
1014
1015 if (isr_timed_out) {
1016 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1017 "leaving target running");
1018 } else {
1019 /* Step over next instruction with interrupts disabled */
1020 cortex_m_set_maskints_for_step(target);
1021 cortex_m_write_debug_halt_mask(target,
1022 C_HALT | C_MASKINTS,
1023 0);
1024 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1025 /* Re-enable interrupts if appropriate */
1026 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1027 cortex_m_set_maskints_for_halt(target);
1028 }
1029 }
1030 }
1031 }
1032 }
1033
1034 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1035 if (retval != ERROR_OK)
1036 return retval;
1037
1038 /* registers are now invalid */
1039 register_cache_invalidate(armv7m->arm.core_cache);
1040
1041 if (breakpoint)
1042 cortex_m_set_breakpoint(target, breakpoint);
1043
1044 if (isr_timed_out) {
1045 /* Leave the core running. The user has to stop execution manually. */
1046 target->debug_reason = DBG_REASON_NOTHALTED;
1047 target->state = TARGET_RUNNING;
1048 return ERROR_OK;
1049 }
1050
1051 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1052 " nvic_icsr = 0x%" PRIx32,
1053 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1054
1055 retval = cortex_m_debug_entry(target);
1056 if (retval != ERROR_OK)
1057 return retval;
1058 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1059
1060 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1061 " nvic_icsr = 0x%" PRIx32,
1062 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1063
1064 return ERROR_OK;
1065 }
1066
1067 static int cortex_m_assert_reset(struct target *target)
1068 {
1069 struct cortex_m_common *cortex_m = target_to_cm(target);
1070 struct armv7m_common *armv7m = &cortex_m->armv7m;
1071 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1072
1073 LOG_DEBUG("target->state: %s",
1074 target_state_name(target));
1075
1076 enum reset_types jtag_reset_config = jtag_get_reset_config();
1077
1078 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1079 /* allow scripts to override the reset event */
1080
1081 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1082 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1083 target->state = TARGET_RESET;
1084
1085 return ERROR_OK;
1086 }
1087
1088 /* some cores support connecting while srst is asserted
1089 * use that mode is it has been configured */
1090
1091 bool srst_asserted = false;
1092
1093 if (!target_was_examined(target)) {
1094 if (jtag_reset_config & RESET_HAS_SRST) {
1095 adapter_assert_reset();
1096 if (target->reset_halt)
1097 LOG_ERROR("Target not examined, will not halt after reset!");
1098 return ERROR_OK;
1099 } else {
1100 LOG_ERROR("Target not examined, reset NOT asserted!");
1101 return ERROR_FAIL;
1102 }
1103 }
1104
1105 if ((jtag_reset_config & RESET_HAS_SRST) &&
1106 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1107 adapter_assert_reset();
1108 srst_asserted = true;
1109 }
1110
1111 /* Enable debug requests */
1112 int retval;
1113 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1114 /* Store important errors instead of failing and proceed to reset assert */
1115
1116 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1117 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1118
1119 /* If the processor is sleeping in a WFI or WFE instruction, the
1120 * C_HALT bit must be asserted to regain control */
1121 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1122 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1123
1124 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1125 /* Ignore less important errors */
1126
1127 if (!target->reset_halt) {
1128 /* Set/Clear C_MASKINTS in a separate operation */
1129 cortex_m_set_maskints_for_run(target);
1130
1131 /* clear any debug flags before resuming */
1132 cortex_m_clear_halt(target);
1133
1134 /* clear C_HALT in dhcsr reg */
1135 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1136 } else {
1137 /* Halt in debug on reset; endreset_event() restores DEMCR.
1138 *
1139 * REVISIT catching BUSERR presumably helps to defend against
1140 * bad vector table entries. Should this include MMERR or
1141 * other flags too?
1142 */
1143 int retval2;
1144 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1145 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1146 if (retval != ERROR_OK || retval2 != ERROR_OK)
1147 LOG_INFO("AP write error, reset will not halt");
1148 }
1149
1150 if (jtag_reset_config & RESET_HAS_SRST) {
1151 /* default to asserting srst */
1152 if (!srst_asserted)
1153 adapter_assert_reset();
1154
1155 /* srst is asserted, ignore AP access errors */
1156 retval = ERROR_OK;
1157 } else {
1158 /* Use a standard Cortex-M3 software reset mechanism.
1159 * We default to using VECRESET as it is supported on all current cores
1160 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1161 * This has the disadvantage of not resetting the peripherals, so a
1162 * reset-init event handler is needed to perform any peripheral resets.
1163 */
1164 if (!cortex_m->vectreset_supported
1165 && reset_config == CORTEX_M_RESET_VECTRESET) {
1166 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1167 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1168 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1169 }
1170
1171 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1172 ? "SYSRESETREQ" : "VECTRESET");
1173
1174 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1175 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1176 "handler to reset any peripherals or configure hardware srst support.");
1177 }
1178
1179 int retval3;
1180 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1181 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1182 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1183 if (retval3 != ERROR_OK)
1184 LOG_DEBUG("Ignoring AP write error right after reset");
1185
1186 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1187 if (retval3 != ERROR_OK)
1188 LOG_ERROR("DP initialisation failed");
1189
1190 else {
1191 /* I do not know why this is necessary, but it
1192 * fixes strange effects (step/resume cause NMI
1193 * after reset) on LM3S6918 -- Michael Schwingen
1194 */
1195 uint32_t tmp;
1196 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1197 }
1198 }
1199
1200 target->state = TARGET_RESET;
1201 jtag_sleep(50000);
1202
1203 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1204
1205 /* now return stored error code if any */
1206 if (retval != ERROR_OK)
1207 return retval;
1208
1209 if (target->reset_halt) {
1210 retval = target_halt(target);
1211 if (retval != ERROR_OK)
1212 return retval;
1213 }
1214
1215 return ERROR_OK;
1216 }
1217
1218 static int cortex_m_deassert_reset(struct target *target)
1219 {
1220 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1221
1222 LOG_DEBUG("target->state: %s",
1223 target_state_name(target));
1224
1225 /* deassert reset lines */
1226 adapter_deassert_reset();
1227
1228 enum reset_types jtag_reset_config = jtag_get_reset_config();
1229
1230 if ((jtag_reset_config & RESET_HAS_SRST) &&
1231 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1232 target_was_examined(target)) {
1233 int retval = dap_dp_init(armv7m->debug_ap->dap);
1234 if (retval != ERROR_OK) {
1235 LOG_ERROR("DP initialisation failed");
1236 return retval;
1237 }
1238 }
1239
1240 return ERROR_OK;
1241 }
1242
1243 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1244 {
1245 int retval;
1246 int fp_num = 0;
1247 struct cortex_m_common *cortex_m = target_to_cm(target);
1248 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1249
1250 if (breakpoint->set) {
1251 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1252 return ERROR_OK;
1253 }
1254
1255 if (breakpoint->type == BKPT_HARD) {
1256 uint32_t fpcr_value;
1257 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1258 fp_num++;
1259 if (fp_num >= cortex_m->fp_num_code) {
1260 LOG_ERROR("Can not find free FPB Comparator!");
1261 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1262 }
1263 breakpoint->set = fp_num + 1;
1264 fpcr_value = breakpoint->address | 1;
1265 if (cortex_m->fp_rev == 0) {
1266 if (breakpoint->address > 0x1FFFFFFF) {
1267 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1268 return ERROR_FAIL;
1269 }
1270 uint32_t hilo;
1271 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1272 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1273 } else if (cortex_m->fp_rev > 1) {
1274 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1275 return ERROR_FAIL;
1276 }
1277 comparator_list[fp_num].used = true;
1278 comparator_list[fp_num].fpcr_value = fpcr_value;
1279 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1280 comparator_list[fp_num].fpcr_value);
1281 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1282 fp_num,
1283 comparator_list[fp_num].fpcr_value);
1284 if (!cortex_m->fpb_enabled) {
1285 LOG_DEBUG("FPB wasn't enabled, do it now");
1286 retval = cortex_m_enable_fpb(target);
1287 if (retval != ERROR_OK) {
1288 LOG_ERROR("Failed to enable the FPB");
1289 return retval;
1290 }
1291
1292 cortex_m->fpb_enabled = true;
1293 }
1294 } else if (breakpoint->type == BKPT_SOFT) {
1295 uint8_t code[4];
1296
1297 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1298 * semihosting; don't use that. Otherwise the BKPT
1299 * parameter is arbitrary.
1300 */
1301 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1302 retval = target_read_memory(target,
1303 breakpoint->address & 0xFFFFFFFE,
1304 breakpoint->length, 1,
1305 breakpoint->orig_instr);
1306 if (retval != ERROR_OK)
1307 return retval;
1308 retval = target_write_memory(target,
1309 breakpoint->address & 0xFFFFFFFE,
1310 breakpoint->length, 1,
1311 code);
1312 if (retval != ERROR_OK)
1313 return retval;
1314 breakpoint->set = true;
1315 }
1316
1317 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1318 breakpoint->unique_id,
1319 (int)(breakpoint->type),
1320 breakpoint->address,
1321 breakpoint->length,
1322 breakpoint->set);
1323
1324 return ERROR_OK;
1325 }
1326
1327 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1328 {
1329 int retval;
1330 struct cortex_m_common *cortex_m = target_to_cm(target);
1331 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1332
1333 if (!breakpoint->set) {
1334 LOG_WARNING("breakpoint not set");
1335 return ERROR_OK;
1336 }
1337
1338 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1339 breakpoint->unique_id,
1340 (int)(breakpoint->type),
1341 breakpoint->address,
1342 breakpoint->length,
1343 breakpoint->set);
1344
1345 if (breakpoint->type == BKPT_HARD) {
1346 int fp_num = breakpoint->set - 1;
1347 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1348 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1349 return ERROR_OK;
1350 }
1351 comparator_list[fp_num].used = false;
1352 comparator_list[fp_num].fpcr_value = 0;
1353 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1354 comparator_list[fp_num].fpcr_value);
1355 } else {
1356 /* restore original instruction (kept in target endianness) */
1357 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1358 breakpoint->length, 1,
1359 breakpoint->orig_instr);
1360 if (retval != ERROR_OK)
1361 return retval;
1362 }
1363 breakpoint->set = false;
1364
1365 return ERROR_OK;
1366 }
1367
1368 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1369 {
1370 if (breakpoint->length == 3) {
1371 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1372 breakpoint->length = 2;
1373 }
1374
1375 if ((breakpoint->length != 2)) {
1376 LOG_INFO("only breakpoints of two bytes length supported");
1377 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1378 }
1379
1380 return cortex_m_set_breakpoint(target, breakpoint);
1381 }
1382
1383 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1384 {
1385 if (!breakpoint->set)
1386 return ERROR_OK;
1387
1388 return cortex_m_unset_breakpoint(target, breakpoint);
1389 }
1390
1391 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1392 {
1393 int dwt_num = 0;
1394 uint32_t mask, temp;
1395 struct cortex_m_common *cortex_m = target_to_cm(target);
1396
1397 /* watchpoint params were validated earlier */
1398 mask = 0;
1399 temp = watchpoint->length;
1400 while (temp) {
1401 temp >>= 1;
1402 mask++;
1403 }
1404 mask--;
1405
1406 /* REVISIT Don't fully trust these "not used" records ... users
1407 * may set up breakpoints by hand, e.g. dual-address data value
1408 * watchpoint using comparator #1; comparator #0 matching cycle
1409 * count; send data trace info through ITM and TPIU; etc
1410 */
1411 struct cortex_m_dwt_comparator *comparator;
1412
1413 for (comparator = cortex_m->dwt_comparator_list;
1414 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1415 comparator++, dwt_num++)
1416 continue;
1417 if (dwt_num >= cortex_m->dwt_num_comp) {
1418 LOG_ERROR("Can not find free DWT Comparator");
1419 return ERROR_FAIL;
1420 }
1421 comparator->used = true;
1422 watchpoint->set = dwt_num + 1;
1423
1424 comparator->comp = watchpoint->address;
1425 target_write_u32(target, comparator->dwt_comparator_address + 0,
1426 comparator->comp);
1427
1428 comparator->mask = mask;
1429 target_write_u32(target, comparator->dwt_comparator_address + 4,
1430 comparator->mask);
1431
1432 switch (watchpoint->rw) {
1433 case WPT_READ:
1434 comparator->function = 5;
1435 break;
1436 case WPT_WRITE:
1437 comparator->function = 6;
1438 break;
1439 case WPT_ACCESS:
1440 comparator->function = 7;
1441 break;
1442 }
1443 target_write_u32(target, comparator->dwt_comparator_address + 8,
1444 comparator->function);
1445
1446 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1447 watchpoint->unique_id, dwt_num,
1448 (unsigned) comparator->comp,
1449 (unsigned) comparator->mask,
1450 (unsigned) comparator->function);
1451 return ERROR_OK;
1452 }
1453
1454 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1455 {
1456 struct cortex_m_common *cortex_m = target_to_cm(target);
1457 struct cortex_m_dwt_comparator *comparator;
1458 int dwt_num;
1459
1460 if (!watchpoint->set) {
1461 LOG_WARNING("watchpoint (wpid: %d) not set",
1462 watchpoint->unique_id);
1463 return ERROR_OK;
1464 }
1465
1466 dwt_num = watchpoint->set - 1;
1467
1468 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1469 watchpoint->unique_id, dwt_num,
1470 (unsigned) watchpoint->address);
1471
1472 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1473 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1474 return ERROR_OK;
1475 }
1476
1477 comparator = cortex_m->dwt_comparator_list + dwt_num;
1478 comparator->used = false;
1479 comparator->function = 0;
1480 target_write_u32(target, comparator->dwt_comparator_address + 8,
1481 comparator->function);
1482
1483 watchpoint->set = false;
1484
1485 return ERROR_OK;
1486 }
1487
1488 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1489 {
1490 struct cortex_m_common *cortex_m = target_to_cm(target);
1491
1492 if (cortex_m->dwt_comp_available < 1) {
1493 LOG_DEBUG("no comparators?");
1494 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1495 }
1496
1497 /* hardware doesn't support data value masking */
1498 if (watchpoint->mask != ~(uint32_t)0) {
1499 LOG_DEBUG("watchpoint value masks not supported");
1500 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1501 }
1502
1503 /* hardware allows address masks of up to 32K */
1504 unsigned mask;
1505
1506 for (mask = 0; mask < 16; mask++) {
1507 if ((1u << mask) == watchpoint->length)
1508 break;
1509 }
1510 if (mask == 16) {
1511 LOG_DEBUG("unsupported watchpoint length");
1512 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1513 }
1514 if (watchpoint->address & ((1 << mask) - 1)) {
1515 LOG_DEBUG("watchpoint address is unaligned");
1516 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1517 }
1518
1519 /* Caller doesn't seem to be able to describe watching for data
1520 * values of zero; that flags "no value".
1521 *
1522 * REVISIT This DWT may well be able to watch for specific data
1523 * values. Requires comparator #1 to set DATAVMATCH and match
1524 * the data, and another comparator (DATAVADDR0) matching addr.
1525 */
1526 if (watchpoint->value) {
1527 LOG_DEBUG("data value watchpoint not YET supported");
1528 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1529 }
1530
1531 cortex_m->dwt_comp_available--;
1532 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1533
1534 return ERROR_OK;
1535 }
1536
1537 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1538 {
1539 struct cortex_m_common *cortex_m = target_to_cm(target);
1540
1541 /* REVISIT why check? DWT can be updated with core running ... */
1542 if (target->state != TARGET_HALTED) {
1543 LOG_WARNING("target not halted");
1544 return ERROR_TARGET_NOT_HALTED;
1545 }
1546
1547 if (watchpoint->set)
1548 cortex_m_unset_watchpoint(target, watchpoint);
1549
1550 cortex_m->dwt_comp_available++;
1551 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1552
1553 return ERROR_OK;
1554 }
1555
1556 void cortex_m_enable_watchpoints(struct target *target)
1557 {
1558 struct watchpoint *watchpoint = target->watchpoints;
1559
1560 /* set any pending watchpoints */
1561 while (watchpoint) {
1562 if (!watchpoint->set)
1563 cortex_m_set_watchpoint(target, watchpoint);
1564 watchpoint = watchpoint->next;
1565 }
1566 }
1567
1568 static int cortex_m_load_core_reg_u32(struct target *target,
1569 uint32_t num, uint32_t *value)
1570 {
1571 int retval;
1572
1573 /* NOTE: we "know" here that the register identifiers used
1574 * in the v7m header match the Cortex-M3 Debug Core Register
1575 * Selector values for R0..R15, xPSR, MSP, and PSP.
1576 */
1577 switch (num) {
1578 case 0 ... 18:
1579 /* read a normal core register */
1580 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1581
1582 if (retval != ERROR_OK) {
1583 LOG_ERROR("JTAG failure %i", retval);
1584 return ERROR_JTAG_DEVICE_ERROR;
1585 }
1586 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1587 break;
1588
1589 case ARMV7M_FPSCR:
1590 /* Floating-point Status and Registers */
1591 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1592 if (retval != ERROR_OK)
1593 return retval;
1594 retval = target_read_u32(target, DCB_DCRDR, value);
1595 if (retval != ERROR_OK)
1596 return retval;
1597 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1598 break;
1599
1600 case ARMV7M_S0 ... ARMV7M_S31:
1601 /* Floating-point Status and Registers */
1602 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1603 if (retval != ERROR_OK)
1604 return retval;
1605 retval = target_read_u32(target, DCB_DCRDR, value);
1606 if (retval != ERROR_OK)
1607 return retval;
1608 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1609 (int)(num - ARMV7M_S0), *value);
1610 break;
1611
1612 case ARMV7M_PRIMASK:
1613 case ARMV7M_BASEPRI:
1614 case ARMV7M_FAULTMASK:
1615 case ARMV7M_CONTROL:
1616 /* Cortex-M3 packages these four registers as bitfields
1617 * in one Debug Core register. So say r0 and r2 docs;
1618 * it was removed from r1 docs, but still works.
1619 */
1620 cortexm_dap_read_coreregister_u32(target, value, 20);
1621
1622 switch (num) {
1623 case ARMV7M_PRIMASK:
1624 *value = buf_get_u32((uint8_t *)value, 0, 1);
1625 break;
1626
1627 case ARMV7M_BASEPRI:
1628 *value = buf_get_u32((uint8_t *)value, 8, 8);
1629 break;
1630
1631 case ARMV7M_FAULTMASK:
1632 *value = buf_get_u32((uint8_t *)value, 16, 1);
1633 break;
1634
1635 case ARMV7M_CONTROL:
1636 *value = buf_get_u32((uint8_t *)value, 24, 2);
1637 break;
1638 }
1639
1640 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1641 break;
1642
1643 default:
1644 return ERROR_COMMAND_SYNTAX_ERROR;
1645 }
1646
1647 return ERROR_OK;
1648 }
1649
1650 static int cortex_m_store_core_reg_u32(struct target *target,
1651 uint32_t num, uint32_t value)
1652 {
1653 int retval;
1654 uint32_t reg;
1655 struct armv7m_common *armv7m = target_to_armv7m(target);
1656
1657 /* NOTE: we "know" here that the register identifiers used
1658 * in the v7m header match the Cortex-M3 Debug Core Register
1659 * Selector values for R0..R15, xPSR, MSP, and PSP.
1660 */
1661 switch (num) {
1662 case 0 ... 18:
1663 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1664 if (retval != ERROR_OK) {
1665 struct reg *r;
1666
1667 LOG_ERROR("JTAG failure");
1668 r = armv7m->arm.core_cache->reg_list + num;
1669 r->dirty = r->valid;
1670 return ERROR_JTAG_DEVICE_ERROR;
1671 }
1672 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1673 break;
1674
1675 case ARMV7M_FPSCR:
1676 /* Floating-point Status and Registers */
1677 retval = target_write_u32(target, DCB_DCRDR, value);
1678 if (retval != ERROR_OK)
1679 return retval;
1680 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1681 if (retval != ERROR_OK)
1682 return retval;
1683 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1684 break;
1685
1686 case ARMV7M_S0 ... ARMV7M_S31:
1687 /* Floating-point Status and Registers */
1688 retval = target_write_u32(target, DCB_DCRDR, value);
1689 if (retval != ERROR_OK)
1690 return retval;
1691 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1692 if (retval != ERROR_OK)
1693 return retval;
1694 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1695 (int)(num - ARMV7M_S0), value);
1696 break;
1697
1698 case ARMV7M_PRIMASK:
1699 case ARMV7M_BASEPRI:
1700 case ARMV7M_FAULTMASK:
1701 case ARMV7M_CONTROL:
1702 /* Cortex-M3 packages these four registers as bitfields
1703 * in one Debug Core register. So say r0 and r2 docs;
1704 * it was removed from r1 docs, but still works.
1705 */
1706 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1707
1708 switch (num) {
1709 case ARMV7M_PRIMASK:
1710 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1711 break;
1712
1713 case ARMV7M_BASEPRI:
1714 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1715 break;
1716
1717 case ARMV7M_FAULTMASK:
1718 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1719 break;
1720
1721 case ARMV7M_CONTROL:
1722 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1723 break;
1724 }
1725
1726 cortexm_dap_write_coreregister_u32(target, reg, 20);
1727
1728 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1729 break;
1730
1731 default:
1732 return ERROR_COMMAND_SYNTAX_ERROR;
1733 }
1734
1735 return ERROR_OK;
1736 }
1737
1738 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1739 uint32_t size, uint32_t count, uint8_t *buffer)
1740 {
1741 struct armv7m_common *armv7m = target_to_armv7m(target);
1742
1743 if (armv7m->arm.is_armv6m) {
1744 /* armv6m does not handle unaligned memory access */
1745 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1746 return ERROR_TARGET_UNALIGNED_ACCESS;
1747 }
1748
1749 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1750 }
1751
1752 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1753 uint32_t size, uint32_t count, const uint8_t *buffer)
1754 {
1755 struct armv7m_common *armv7m = target_to_armv7m(target);
1756
1757 if (armv7m->arm.is_armv6m) {
1758 /* armv6m does not handle unaligned memory access */
1759 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1760 return ERROR_TARGET_UNALIGNED_ACCESS;
1761 }
1762
1763 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1764 }
1765
1766 static int cortex_m_init_target(struct command_context *cmd_ctx,
1767 struct target *target)
1768 {
1769 armv7m_build_reg_cache(target);
1770 arm_semihosting_init(target);
1771 return ERROR_OK;
1772 }
1773
1774 void cortex_m_deinit_target(struct target *target)
1775 {
1776 struct cortex_m_common *cortex_m = target_to_cm(target);
1777
1778 free(cortex_m->fp_comparator_list);
1779
1780 cortex_m_dwt_free(target);
1781 armv7m_free_reg_cache(target);
1782
1783 free(target->private_config);
1784 free(cortex_m);
1785 }
1786
1787 int cortex_m_profiling(struct target *target, uint32_t *samples,
1788 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1789 {
1790 struct timeval timeout, now;
1791 struct armv7m_common *armv7m = target_to_armv7m(target);
1792 uint32_t reg_value;
1793 bool use_pcsr = false;
1794 int retval = ERROR_OK;
1795 struct reg *reg;
1796
1797 gettimeofday(&timeout, NULL);
1798 timeval_add_time(&timeout, seconds, 0);
1799
1800 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1801 if (retval != ERROR_OK) {
1802 LOG_ERROR("Error while reading PCSR");
1803 return retval;
1804 }
1805
1806 if (reg_value != 0) {
1807 use_pcsr = true;
1808 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1809 } else {
1810 LOG_INFO("Starting profiling. Halting and resuming the"
1811 " target as often as we can...");
1812 reg = register_get_by_name(target->reg_cache, "pc", 1);
1813 }
1814
1815 /* Make sure the target is running */
1816 target_poll(target);
1817 if (target->state == TARGET_HALTED)
1818 retval = target_resume(target, 1, 0, 0, 0);
1819
1820 if (retval != ERROR_OK) {
1821 LOG_ERROR("Error while resuming target");
1822 return retval;
1823 }
1824
1825 uint32_t sample_count = 0;
1826
1827 for (;;) {
1828 if (use_pcsr) {
1829 if (armv7m && armv7m->debug_ap) {
1830 uint32_t read_count = max_num_samples - sample_count;
1831 if (read_count > 1024)
1832 read_count = 1024;
1833
1834 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1835 (void *)&samples[sample_count],
1836 4, read_count, DWT_PCSR);
1837 sample_count += read_count;
1838 } else {
1839 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1840 }
1841 } else {
1842 target_poll(target);
1843 if (target->state == TARGET_HALTED) {
1844 reg_value = buf_get_u32(reg->value, 0, 32);
1845 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1846 retval = target_resume(target, 1, 0, 0, 0);
1847 samples[sample_count++] = reg_value;
1848 target_poll(target);
1849 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1850 } else if (target->state == TARGET_RUNNING) {
1851 /* We want to quickly sample the PC. */
1852 retval = target_halt(target);
1853 } else {
1854 LOG_INFO("Target not halted or running");
1855 retval = ERROR_OK;
1856 break;
1857 }
1858 }
1859
1860 if (retval != ERROR_OK) {
1861 LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1862 return retval;
1863 }
1864
1865
1866 gettimeofday(&now, NULL);
1867 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1868 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1869 break;
1870 }
1871 }
1872
1873 *num_samples = sample_count;
1874 return retval;
1875 }
1876
1877
1878 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1879 * on r/w if the core is not running, and clear on resume or reset ... or
1880 * at least, in a post_restore_context() method.
1881 */
1882
1883 struct dwt_reg_state {
1884 struct target *target;
1885 uint32_t addr;
1886 uint8_t value[4]; /* scratch/cache */
1887 };
1888
1889 static int cortex_m_dwt_get_reg(struct reg *reg)
1890 {
1891 struct dwt_reg_state *state = reg->arch_info;
1892
1893 uint32_t tmp;
1894 int retval = target_read_u32(state->target, state->addr, &tmp);
1895 if (retval != ERROR_OK)
1896 return retval;
1897
1898 buf_set_u32(state->value, 0, 32, tmp);
1899 return ERROR_OK;
1900 }
1901
1902 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1903 {
1904 struct dwt_reg_state *state = reg->arch_info;
1905
1906 return target_write_u32(state->target, state->addr,
1907 buf_get_u32(buf, 0, reg->size));
1908 }
1909
1910 struct dwt_reg {
1911 uint32_t addr;
1912 const char *name;
1913 unsigned size;
1914 };
1915
1916 static const struct dwt_reg dwt_base_regs[] = {
1917 { DWT_CTRL, "dwt_ctrl", 32, },
1918 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1919 * increments while the core is asleep.
1920 */
1921 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1922 /* plus some 8 bit counters, useful for profiling with TPIU */
1923 };
1924
1925 static const struct dwt_reg dwt_comp[] = {
1926 #define DWT_COMPARATOR(i) \
1927 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1928 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1929 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1930 DWT_COMPARATOR(0),
1931 DWT_COMPARATOR(1),
1932 DWT_COMPARATOR(2),
1933 DWT_COMPARATOR(3),
1934 DWT_COMPARATOR(4),
1935 DWT_COMPARATOR(5),
1936 DWT_COMPARATOR(6),
1937 DWT_COMPARATOR(7),
1938 DWT_COMPARATOR(8),
1939 DWT_COMPARATOR(9),
1940 DWT_COMPARATOR(10),
1941 DWT_COMPARATOR(11),
1942 DWT_COMPARATOR(12),
1943 DWT_COMPARATOR(13),
1944 DWT_COMPARATOR(14),
1945 DWT_COMPARATOR(15),
1946 #undef DWT_COMPARATOR
1947 };
1948
1949 static const struct reg_arch_type dwt_reg_type = {
1950 .get = cortex_m_dwt_get_reg,
1951 .set = cortex_m_dwt_set_reg,
1952 };
1953
1954 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1955 {
1956 struct dwt_reg_state *state;
1957
1958 state = calloc(1, sizeof *state);
1959 if (!state)
1960 return;
1961 state->addr = d->addr;
1962 state->target = t;
1963
1964 r->name = d->name;
1965 r->size = d->size;
1966 r->value = state->value;
1967 r->arch_info = state;
1968 r->type = &dwt_reg_type;
1969 }
1970
1971 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1972 {
1973 uint32_t dwtcr;
1974 struct reg_cache *cache;
1975 struct cortex_m_dwt_comparator *comparator;
1976 int reg, i;
1977
1978 target_read_u32(target, DWT_CTRL, &dwtcr);
1979 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1980 if (!dwtcr) {
1981 LOG_DEBUG("no DWT");
1982 return;
1983 }
1984
1985 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1986 cm->dwt_comp_available = cm->dwt_num_comp;
1987 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1988 sizeof(struct cortex_m_dwt_comparator));
1989 if (!cm->dwt_comparator_list) {
1990 fail0:
1991 cm->dwt_num_comp = 0;
1992 LOG_ERROR("out of mem");
1993 return;
1994 }
1995
1996 cache = calloc(1, sizeof *cache);
1997 if (!cache) {
1998 fail1:
1999 free(cm->dwt_comparator_list);
2000 goto fail0;
2001 }
2002 cache->name = "Cortex-M DWT registers";
2003 cache->num_regs = 2 + cm->dwt_num_comp * 3;
2004 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
2005 if (!cache->reg_list) {
2006 free(cache);
2007 goto fail1;
2008 }
2009
2010 for (reg = 0; reg < 2; reg++)
2011 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2012 dwt_base_regs + reg);
2013
2014 comparator = cm->dwt_comparator_list;
2015 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
2016 int j;
2017
2018 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
2019 for (j = 0; j < 3; j++, reg++)
2020 cortex_m_dwt_addreg(target, cache->reg_list + reg,
2021 dwt_comp + 3 * i + j);
2022
2023 /* make sure we clear any watchpoints enabled on the target */
2024 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
2025 }
2026
2027 *register_get_last_cache_p(&target->reg_cache) = cache;
2028 cm->dwt_cache = cache;
2029
2030 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
2031 dwtcr, cm->dwt_num_comp,
2032 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
2033
2034 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2035 * implement single-address data value watchpoints ... so we
2036 * won't need to check it later, when asked to set one up.
2037 */
2038 }
2039
2040 static void cortex_m_dwt_free(struct target *target)
2041 {
2042 struct cortex_m_common *cm = target_to_cm(target);
2043 struct reg_cache *cache = cm->dwt_cache;
2044
2045 free(cm->dwt_comparator_list);
2046 cm->dwt_comparator_list = NULL;
2047 cm->dwt_num_comp = 0;
2048
2049 if (cache) {
2050 register_unlink_cache(&target->reg_cache, cache);
2051
2052 if (cache->reg_list) {
2053 for (size_t i = 0; i < cache->num_regs; i++)
2054 free(cache->reg_list[i].arch_info);
2055 free(cache->reg_list);
2056 }
2057 free(cache);
2058 }
2059 cm->dwt_cache = NULL;
2060 }
2061
2062 #define MVFR0 0xe000ef40
2063 #define MVFR1 0xe000ef44
2064
2065 #define MVFR0_DEFAULT_M4 0x10110021
2066 #define MVFR1_DEFAULT_M4 0x11000011
2067
2068 #define MVFR0_DEFAULT_M7_SP 0x10110021
2069 #define MVFR0_DEFAULT_M7_DP 0x10110221
2070 #define MVFR1_DEFAULT_M7_SP 0x11000011
2071 #define MVFR1_DEFAULT_M7_DP 0x12000011
2072
2073 int cortex_m_examine(struct target *target)
2074 {
2075 int retval;
2076 uint32_t cpuid, fpcr, mvfr0, mvfr1;
2077 int i;
2078 struct cortex_m_common *cortex_m = target_to_cm(target);
2079 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2080 struct armv7m_common *armv7m = target_to_armv7m(target);
2081
2082 /* stlink shares the examine handler but does not support
2083 * all its calls */
2084 if (!armv7m->stlink) {
2085 if (cortex_m->apsel == DP_APSEL_INVALID) {
2086 /* Search for the MEM-AP */
2087 retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
2088 if (retval != ERROR_OK) {
2089 LOG_ERROR("Could not find MEM-AP to control the core");
2090 return retval;
2091 }
2092 } else {
2093 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2094 }
2095
2096 /* Leave (only) generic DAP stuff for debugport_init(); */
2097 armv7m->debug_ap->memaccess_tck = 8;
2098
2099 retval = mem_ap_init(armv7m->debug_ap);
2100 if (retval != ERROR_OK)
2101 return retval;
2102 }
2103
2104 if (!target_was_examined(target)) {
2105 target_set_examined(target);
2106
2107 /* Read from Device Identification Registers */
2108 retval = target_read_u32(target, CPUID, &cpuid);
2109 if (retval != ERROR_OK)
2110 return retval;
2111
2112 /* Get CPU Type */
2113 i = (cpuid >> 4) & 0xf;
2114
2115 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2116 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2117 cortex_m->maskints_erratum = false;
2118 if (i == 7) {
2119 uint8_t rev, patch;
2120 rev = (cpuid >> 20) & 0xf;
2121 patch = (cpuid >> 0) & 0xf;
2122 if ((rev == 0) && (patch < 2)) {
2123 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2124 cortex_m->maskints_erratum = true;
2125 }
2126 }
2127 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2128
2129 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2130 cortex_m->vectreset_supported = i > 1;
2131
2132 if (i == 4) {
2133 target_read_u32(target, MVFR0, &mvfr0);
2134 target_read_u32(target, MVFR1, &mvfr1);
2135
2136 /* test for floating point feature on Cortex-M4 */
2137 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2138 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2139 armv7m->fp_feature = FPv4_SP;
2140 }
2141 } else if (i == 7) {
2142 target_read_u32(target, MVFR0, &mvfr0);
2143 target_read_u32(target, MVFR1, &mvfr1);
2144
2145 /* test for floating point features on Cortex-M7 */
2146 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2147 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2148 armv7m->fp_feature = FPv5_SP;
2149 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2150 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2151 armv7m->fp_feature = FPv5_DP;
2152 }
2153 } else if (i == 0) {
2154 /* Cortex-M0 does not support unaligned memory access */
2155 armv7m->arm.is_armv6m = true;
2156 }
2157
2158 if (armv7m->fp_feature == FP_NONE &&
2159 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2160 /* free unavailable FPU registers */
2161 size_t idx;
2162
2163 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2164 idx < armv7m->arm.core_cache->num_regs;
2165 idx++) {
2166 free(armv7m->arm.core_cache->reg_list[idx].value);
2167 free(armv7m->arm.core_cache->reg_list[idx].feature);
2168 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2169 }
2170 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2171 }
2172
2173 if (!armv7m->stlink) {
2174 if (i == 3 || i == 4)
2175 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2176 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2177 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2178 else if (i == 7)
2179 /* Cortex-M7 has only 1024 bytes autoincrement range */
2180 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2181 }
2182
2183 /* Configure trace modules */
2184 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2185 if (retval != ERROR_OK)
2186 return retval;
2187
2188 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2189 armv7m_trace_tpiu_config(target);
2190 armv7m_trace_itm_config(target);
2191 }
2192
2193 /* NOTE: FPB and DWT are both optional. */
2194
2195 /* Setup FPB */
2196 target_read_u32(target, FP_CTRL, &fpcr);
2197 /* bits [14:12] and [7:4] */
2198 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2199 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2200 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2201 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2202 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2203 free(cortex_m->fp_comparator_list);
2204 cortex_m->fp_comparator_list = calloc(
2205 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2206 sizeof(struct cortex_m_fp_comparator));
2207 cortex_m->fpb_enabled = fpcr & 1;
2208 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2209 cortex_m->fp_comparator_list[i].type =
2210 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2211 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2212
2213 /* make sure we clear any breakpoints enabled on the target */
2214 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2215 }
2216 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2217 fpcr,
2218 cortex_m->fp_num_code,
2219 cortex_m->fp_num_lit);
2220
2221 /* Setup DWT */
2222 cortex_m_dwt_free(target);
2223 cortex_m_dwt_setup(cortex_m, target);
2224
2225 /* These hardware breakpoints only work for code in flash! */
2226 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2227 target_name(target),
2228 cortex_m->fp_num_code,
2229 cortex_m->dwt_num_comp);
2230 }
2231
2232 return ERROR_OK;
2233 }
2234
2235 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2236 {
2237 struct armv7m_common *armv7m = target_to_armv7m(target);
2238 uint16_t dcrdr;
2239 uint8_t buf[2];
2240 int retval;
2241
2242 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2243 if (retval != ERROR_OK)
2244 return retval;
2245
2246 dcrdr = target_buffer_get_u16(target, buf);
2247 *ctrl = (uint8_t)dcrdr;
2248 *value = (uint8_t)(dcrdr >> 8);
2249
2250 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2251
2252 /* write ack back to software dcc register
2253 * signify we have read data */
2254 if (dcrdr & (1 << 0)) {
2255 target_buffer_set_u16(target, buf, 0);
2256 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2257 if (retval != ERROR_OK)
2258 return retval;
2259 }
2260
2261 return ERROR_OK;
2262 }
2263
2264 static int cortex_m_target_request_data(struct target *target,
2265 uint32_t size, uint8_t *buffer)
2266 {
2267 uint8_t data;
2268 uint8_t ctrl;
2269 uint32_t i;
2270
2271 for (i = 0; i < (size * 4); i++) {
2272 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2273 if (retval != ERROR_OK)
2274 return retval;
2275 buffer[i] = data;
2276 }
2277
2278 return ERROR_OK;
2279 }
2280
2281 static int cortex_m_handle_target_request(void *priv)
2282 {
2283 struct target *target = priv;
2284 if (!target_was_examined(target))
2285 return ERROR_OK;
2286
2287 if (!target->dbg_msg_enabled)
2288 return ERROR_OK;
2289
2290 if (target->state == TARGET_RUNNING) {
2291 uint8_t data;
2292 uint8_t ctrl;
2293 int retval;
2294
2295 retval = cortex_m_dcc_read(target, &data, &ctrl);
2296 if (retval != ERROR_OK)
2297 return retval;
2298
2299 /* check if we have data */
2300 if (ctrl & (1 << 0)) {
2301 uint32_t request;
2302
2303 /* we assume target is quick enough */
2304 request = data;
2305 for (int i = 1; i <= 3; i++) {
2306 retval = cortex_m_dcc_read(target, &data, &ctrl);
2307 if (retval != ERROR_OK)
2308 return retval;
2309 request |= ((uint32_t)data << (i * 8));
2310 }
2311 target_request(target, request);
2312 }
2313 }
2314
2315 return ERROR_OK;
2316 }
2317
2318 static int cortex_m_init_arch_info(struct target *target,
2319 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2320 {
2321 struct armv7m_common *armv7m = &cortex_m->armv7m;
2322
2323 armv7m_init_arch_info(target, armv7m);
2324
2325 /* default reset mode is to use srst if fitted
2326 * if not it will use CORTEX_M3_RESET_VECTRESET */
2327 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2328
2329 armv7m->arm.dap = dap;
2330
2331 /* register arch-specific functions */
2332 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2333
2334 armv7m->post_debug_entry = NULL;
2335
2336 armv7m->pre_restore_context = NULL;
2337
2338 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2339 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2340
2341 target_register_timer_callback(cortex_m_handle_target_request, 1,
2342 TARGET_TIMER_TYPE_PERIODIC, target);
2343
2344 return ERROR_OK;
2345 }
2346
2347 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2348 {
2349 struct adiv5_private_config *pc;
2350
2351 pc = (struct adiv5_private_config *)target->private_config;
2352 if (adiv5_verify_config(pc) != ERROR_OK)
2353 return ERROR_FAIL;
2354
2355 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2356 if (cortex_m == NULL) {
2357 LOG_ERROR("No memory creating target");
2358 return ERROR_FAIL;
2359 }
2360
2361 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2362 cortex_m->apsel = pc->ap_num;
2363
2364 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2365
2366 return ERROR_OK;
2367 }
2368
2369 /*--------------------------------------------------------------------------*/
2370
2371 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2372 struct cortex_m_common *cm)
2373 {
2374 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2375 command_print(cmd, "target is not a Cortex-M");
2376 return ERROR_TARGET_INVALID;
2377 }
2378 return ERROR_OK;
2379 }
2380
2381 /*
2382 * Only stuff below this line should need to verify that its target
2383 * is a Cortex-M3. Everything else should have indirected through the
2384 * cortexm3_target structure, which is only used with CM3 targets.
2385 */
2386
2387 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2388 {
2389 struct target *target = get_current_target(CMD_CTX);
2390 struct cortex_m_common *cortex_m = target_to_cm(target);
2391 struct armv7m_common *armv7m = &cortex_m->armv7m;
2392 uint32_t demcr = 0;
2393 int retval;
2394
2395 static const struct {
2396 char name[10];
2397 unsigned mask;
2398 } vec_ids[] = {
2399 { "hard_err", VC_HARDERR, },
2400 { "int_err", VC_INTERR, },
2401 { "bus_err", VC_BUSERR, },
2402 { "state_err", VC_STATERR, },
2403 { "chk_err", VC_CHKERR, },
2404 { "nocp_err", VC_NOCPERR, },
2405 { "mm_err", VC_MMERR, },
2406 { "reset", VC_CORERESET, },
2407 };
2408
2409 retval = cortex_m_verify_pointer(CMD, cortex_m);
2410 if (retval != ERROR_OK)
2411 return retval;
2412
2413 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2414 if (retval != ERROR_OK)
2415 return retval;
2416
2417 if (CMD_ARGC > 0) {
2418 unsigned catch = 0;
2419
2420 if (CMD_ARGC == 1) {
2421 if (strcmp(CMD_ARGV[0], "all") == 0) {
2422 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2423 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2424 | VC_MMERR | VC_CORERESET;
2425 goto write;
2426 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2427 goto write;
2428 }
2429 while (CMD_ARGC-- > 0) {
2430 unsigned i;
2431 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2432 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2433 continue;
2434 catch |= vec_ids[i].mask;
2435 break;
2436 }
2437 if (i == ARRAY_SIZE(vec_ids)) {
2438 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2439 return ERROR_COMMAND_SYNTAX_ERROR;
2440 }
2441 }
2442 write:
2443 /* For now, armv7m->demcr only stores vector catch flags. */
2444 armv7m->demcr = catch;
2445
2446 demcr &= ~0xffff;
2447 demcr |= catch;
2448
2449 /* write, but don't assume it stuck (why not??) */
2450 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2451 if (retval != ERROR_OK)
2452 return retval;
2453 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2454 if (retval != ERROR_OK)
2455 return retval;
2456
2457 /* FIXME be sure to clear DEMCR on clean server shutdown.
2458 * Otherwise the vector catch hardware could fire when there's
2459 * no debugger hooked up, causing much confusion...
2460 */
2461 }
2462
2463 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2464 command_print(CMD, "%9s: %s", vec_ids[i].name,
2465 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2466 }
2467
2468 return ERROR_OK;
2469 }
2470
2471 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2472 {
2473 struct target *target = get_current_target(CMD_CTX);
2474 struct cortex_m_common *cortex_m = target_to_cm(target);
2475 int retval;
2476
2477 static const Jim_Nvp nvp_maskisr_modes[] = {
2478 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2479 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2480 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2481 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2482 { .name = NULL, .value = -1 },
2483 };
2484 const Jim_Nvp *n;
2485
2486
2487 retval = cortex_m_verify_pointer(CMD, cortex_m);
2488 if (retval != ERROR_OK)
2489 return retval;
2490
2491 if (target->state != TARGET_HALTED) {
2492 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2493 return ERROR_OK;
2494 }
2495
2496 if (CMD_ARGC > 0) {
2497 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2498 if (n->name == NULL)
2499 return ERROR_COMMAND_SYNTAX_ERROR;
2500 cortex_m->isrmasking_mode = n->value;
2501 cortex_m_set_maskints_for_halt(target);
2502 }
2503
2504 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2505 command_print(CMD, "cortex_m interrupt mask %s", n->name);
2506
2507 return ERROR_OK;
2508 }
2509
2510 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2511 {
2512 struct target *target = get_current_target(CMD_CTX);
2513 struct cortex_m_common *cortex_m = target_to_cm(target);
2514 int retval;
2515 char *reset_config;
2516
2517 retval = cortex_m_verify_pointer(CMD, cortex_m);
2518 if (retval != ERROR_OK)
2519 return retval;
2520
2521 if (CMD_ARGC > 0) {
2522 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2523 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2524
2525 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2526 if (target_was_examined(target)
2527 && !cortex_m->vectreset_supported)
2528 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2529 else
2530 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2531
2532 } else
2533 return ERROR_COMMAND_SYNTAX_ERROR;
2534 }
2535
2536 switch (cortex_m->soft_reset_config) {
2537 case CORTEX_M_RESET_SYSRESETREQ:
2538 reset_config = "sysresetreq";
2539 break;
2540
2541 case CORTEX_M_RESET_VECTRESET:
2542 reset_config = "vectreset";
2543 break;
2544
2545 default:
2546 reset_config = "unknown";
2547 break;
2548 }
2549
2550 command_print(CMD, "cortex_m reset_config %s", reset_config);
2551
2552 return ERROR_OK;
2553 }
2554
2555 static const struct command_registration cortex_m_exec_command_handlers[] = {
2556 {
2557 .name = "maskisr",
2558 .handler = handle_cortex_m_mask_interrupts_command,
2559 .mode = COMMAND_EXEC,
2560 .help = "mask cortex_m interrupts",
2561 .usage = "['auto'|'on'|'off'|'steponly']",
2562 },
2563 {
2564 .name = "vector_catch",
2565 .handler = handle_cortex_m_vector_catch_command,
2566 .mode = COMMAND_EXEC,
2567 .help = "configure hardware vectors to trigger debug entry",
2568 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2569 },
2570 {
2571 .name = "reset_config",
2572 .handler = handle_cortex_m_reset_config_command,
2573 .mode = COMMAND_ANY,
2574 .help = "configure software reset handling",
2575 .usage = "['sysresetreq'|'vectreset']",
2576 },
2577 COMMAND_REGISTRATION_DONE
2578 };
2579 static const struct command_registration cortex_m_command_handlers[] = {
2580 {
2581 .chain = armv7m_command_handlers,
2582 },
2583 {
2584 .chain = armv7m_trace_command_handlers,
2585 },
2586 {
2587 .name = "cortex_m",
2588 .mode = COMMAND_EXEC,
2589 .help = "Cortex-M command group",
2590 .usage = "",
2591 .chain = cortex_m_exec_command_handlers,
2592 },
2593 COMMAND_REGISTRATION_DONE
2594 };
2595
2596 struct target_type cortexm_target = {
2597 .name = "cortex_m",
2598 .deprecated_name = "cortex_m3",
2599
2600 .poll = cortex_m_poll,
2601 .arch_state = armv7m_arch_state,
2602
2603 .target_request_data = cortex_m_target_request_data,
2604
2605 .halt = cortex_m_halt,
2606 .resume = cortex_m_resume,
2607 .step = cortex_m_step,
2608
2609 .assert_reset = cortex_m_assert_reset,
2610 .deassert_reset = cortex_m_deassert_reset,
2611 .soft_reset_halt = cortex_m_soft_reset_halt,
2612
2613 .get_gdb_arch = arm_get_gdb_arch,
2614 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2615
2616 .read_memory = cortex_m_read_memory,
2617 .write_memory = cortex_m_write_memory,
2618 .checksum_memory = armv7m_checksum_memory,
2619 .blank_check_memory = armv7m_blank_check_memory,
2620
2621 .run_algorithm = armv7m_run_algorithm,
2622 .start_algorithm = armv7m_start_algorithm,
2623 .wait_algorithm = armv7m_wait_algorithm,
2624
2625 .add_breakpoint = cortex_m_add_breakpoint,
2626 .remove_breakpoint = cortex_m_remove_breakpoint,
2627 .add_watchpoint = cortex_m_add_watchpoint,
2628 .remove_watchpoint = cortex_m_remove_watchpoint,
2629
2630 .commands = cortex_m_command_handlers,
2631 .target_create = cortex_m_target_create,
2632 .target_jim_configure = adiv5_jim_configure,
2633 .init_target = cortex_m_init_target,
2634 .examine = cortex_m_examine,
2635 .deinit_target = cortex_m_deinit_target,
2636
2637 .profiling = cortex_m_profiling,
2638 };
Open On-Chip Debugger