1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "breakpoints.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
40 #include "arm_opcodes.h"
41 #include "arm_semihosting.h"
42 #include <helper/time_support.h>
44 /* NOTE: most of this should work fine for the Cortex-M1 and
45 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
46 * Some differences: M0/M1 doesn't have FBP remapping or the
47 * DWT tracing/profiling support. (So the cycle counter will
48 * not be usable; the other stuff isn't currently used here.)
50 * Although there are some workarounds for errata seen only in r0p0
51 * silicon, such old parts are hard to find and thus not much tested
56 * Returns the type of a break point required by address location
58 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
61 /* forward declarations */
62 static int cortex_m3_store_core_reg_u32(struct target
*target
,
63 enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
65 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap
*swjdp
,
66 uint32_t *value
, int regnum
)
71 /* because the DCB_DCRDR is used for the emulated dcc channel
72 * we have to save/restore the DCB_DCRDR when used */
74 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
75 if (retval
!= ERROR_OK
)
78 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
79 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
80 if (retval
!= ERROR_OK
)
82 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
83 if (retval
!= ERROR_OK
)
86 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
87 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
88 if (retval
!= ERROR_OK
)
90 retval
= dap_queue_ap_read(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
91 if (retval
!= ERROR_OK
)
94 retval
= dap_run(swjdp
);
95 if (retval
!= ERROR_OK
)
98 /* restore DCB_DCRDR - this needs to be in a seperate
99 * transaction otherwise the emulated DCC channel breaks */
100 if (retval
== ERROR_OK
)
101 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
106 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap
*swjdp
,
107 uint32_t value
, int regnum
)
112 /* because the DCB_DCRDR is used for the emulated dcc channel
113 * we have to save/restore the DCB_DCRDR when used */
115 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
116 if (retval
!= ERROR_OK
)
119 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
120 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
121 if (retval
!= ERROR_OK
)
123 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
124 if (retval
!= ERROR_OK
)
127 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
128 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
129 if (retval
!= ERROR_OK
)
131 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
132 if (retval
!= ERROR_OK
)
135 retval
= dap_run(swjdp
);
136 if (retval
!= ERROR_OK
)
139 /* restore DCB_DCRDR - this needs to be in a seperate
140 * transaction otherwise the emulated DCC channel breaks */
141 if (retval
== ERROR_OK
)
142 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
147 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
148 uint32_t mask_on
, uint32_t mask_off
)
150 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
151 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
153 /* mask off status bits */
154 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
155 /* create new register mask */
156 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
158 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
161 static int cortex_m3_clear_halt(struct target
*target
)
163 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
164 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
167 /* clear step if any */
168 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
170 /* Read Debug Fault Status Register */
171 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
172 if (retval
!= ERROR_OK
)
175 /* Clear Debug Fault Status */
176 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
177 if (retval
!= ERROR_OK
)
179 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
184 static int cortex_m3_single_step_core(struct target
*target
)
186 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
187 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
191 /* backup dhcsr reg */
192 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
194 /* Mask interrupts before clearing halt, if done already. This avoids
195 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
196 * HALT can put the core into an unknown state.
198 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
))
200 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
201 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
202 if (retval
!= ERROR_OK
)
205 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
206 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
207 if (retval
!= ERROR_OK
)
211 /* restore dhcsr reg */
212 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
213 cortex_m3_clear_halt(target
);
218 static int cortex_m3_endreset_event(struct target
*target
)
223 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
224 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
225 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
226 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
227 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
229 /* REVISIT The four debug monitor bits are currently ignored... */
230 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
231 if (retval
!= ERROR_OK
)
233 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"",dcb_demcr
);
235 /* this register is used for emulated dcc channel */
236 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
237 if (retval
!= ERROR_OK
)
240 /* Enable debug requests */
241 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
242 if (retval
!= ERROR_OK
)
244 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
246 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
247 if (retval
!= ERROR_OK
)
251 /* clear any interrupt masking */
252 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
254 /* Enable features controlled by ITM and DWT blocks, and catch only
255 * the vectors we were told to pay attention to.
257 * Target firmware is responsible for all fault handling policy
258 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
259 * or manual updates to the NVIC SHCSR and CCR registers.
261 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
262 if (retval
!= ERROR_OK
)
265 /* Paranoia: evidently some (early?) chips don't preserve all the
266 * debug state (including FBP, DWT, etc) across reset...
270 retval
= target_write_u32(target
, FP_CTRL
, 3);
271 if (retval
!= ERROR_OK
)
274 cortex_m3
->fpb_enabled
= 1;
276 /* Restore FPB registers */
277 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
279 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
280 if (retval
!= ERROR_OK
)
284 /* Restore DWT registers */
285 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++)
287 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
289 if (retval
!= ERROR_OK
)
291 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
293 if (retval
!= ERROR_OK
)
295 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
296 dwt_list
[i
].function
);
297 if (retval
!= ERROR_OK
)
300 retval
= dap_run(swjdp
);
301 if (retval
!= ERROR_OK
)
304 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
306 /* make sure we have latest dhcsr flags */
307 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
312 static int cortex_m3_examine_debug_reason(struct target
*target
)
314 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
316 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
317 /* only check the debug reason if we don't know it already */
319 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
320 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
322 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
)
324 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
325 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
326 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
328 else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
329 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
330 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
331 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
332 else /* EXTERNAL, HALTED */
333 target
->debug_reason
= DBG_REASON_UNDEFINED
;
339 static int cortex_m3_examine_exception_reason(struct target
*target
)
341 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
342 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
343 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
346 retval
= mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
347 if (retval
!= ERROR_OK
)
349 switch (armv7m
->exception_number
)
353 case 3: /* Hard Fault */
354 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
355 if (retval
!= ERROR_OK
)
357 if (except_sr
& 0x40000000)
359 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
360 if (retval
!= ERROR_OK
)
364 case 4: /* Memory Management */
365 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
366 if (retval
!= ERROR_OK
)
368 retval
= mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
369 if (retval
!= ERROR_OK
)
372 case 5: /* Bus Fault */
373 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
374 if (retval
!= ERROR_OK
)
376 retval
= mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
377 if (retval
!= ERROR_OK
)
380 case 6: /* Usage Fault */
381 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
382 if (retval
!= ERROR_OK
)
385 case 11: /* SVCall */
387 case 12: /* Debug Monitor */
388 retval
= mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
389 if (retval
!= ERROR_OK
)
392 case 14: /* PendSV */
394 case 15: /* SysTick */
400 retval
= dap_run(swjdp
);
401 if (retval
== ERROR_OK
)
402 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
403 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
404 armv7m_exception_string(armv7m
->exception_number
),
405 shcsr
, except_sr
, cfsr
, except_ar
);
409 static int cortex_m3_debug_entry(struct target
*target
)
414 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
415 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
416 struct arm
*arm
= &armv7m
->arm
;
417 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
422 cortex_m3_clear_halt(target
);
423 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
424 if (retval
!= ERROR_OK
)
427 if ((retval
= armv7m
->examine_debug_reason(target
)) != ERROR_OK
)
430 /* Examine target state and mode */
431 /* First load register acessible through core debug port*/
432 int num_regs
= armv7m
->core_cache
->num_regs
;
434 for (i
= 0; i
< num_regs
; i
++)
436 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
437 armv7m
->read_core_reg(target
, i
);
440 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
441 xPSR
= buf_get_u32(r
->value
, 0, 32);
443 #ifdef ARMV7_GDB_HACKS
444 /* FIXME this breaks on scan chains with more than one Cortex-M3.
445 * Instead, each CM3 should have its own dummy value...
447 /* copy real xpsr reg for gdb, setting thumb bit */
448 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
449 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
450 armv7m_gdb_dummy_cpsr_reg
.valid
= r
->valid
;
451 armv7m_gdb_dummy_cpsr_reg
.dirty
= r
->dirty
;
454 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
458 cortex_m3_store_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 16, xPSR
&~ 0xff);
461 /* Are we in an exception handler */
464 armv7m
->core_mode
= ARMV7M_MODE_HANDLER
;
465 armv7m
->exception_number
= (xPSR
& 0x1FF);
467 arm
->core_mode
= ARM_MODE_HANDLER
;
468 arm
->map
= armv7m_msp_reg_map
;
472 unsigned control
= buf_get_u32(armv7m
->core_cache
473 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
475 /* is this thread privileged? */
476 armv7m
->core_mode
= control
& 1;
477 arm
->core_mode
= armv7m
->core_mode
478 ? ARM_MODE_USER_THREAD
481 /* which stack is it using? */
483 arm
->map
= armv7m_psp_reg_map
;
485 arm
->map
= armv7m_msp_reg_map
;
487 armv7m
->exception_number
= 0;
490 if (armv7m
->exception_number
)
492 cortex_m3_examine_exception_reason(target
);
495 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
496 armv7m_mode_strings
[armv7m
->core_mode
],
497 *(uint32_t*)(arm
->pc
->value
),
498 target_state_name(target
));
500 if (armv7m
->post_debug_entry
)
502 retval
= armv7m
->post_debug_entry(target
);
503 if (retval
!= ERROR_OK
)
510 static int cortex_m3_poll(struct target
*target
)
512 int detected_failure
= ERROR_OK
;
513 int retval
= ERROR_OK
;
514 enum target_state prev_target_state
= target
->state
;
515 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
516 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
518 /* Read from Debug Halting Control and Status Register */
519 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
520 if (retval
!= ERROR_OK
)
522 target
->state
= TARGET_UNKNOWN
;
526 /* Recover from lockup. See ARMv7-M architecture spec,
527 * section B1.5.15 "Unrecoverable exception cases".
529 if (cortex_m3
->dcb_dhcsr
& S_LOCKUP
) {
530 LOG_ERROR("%s -- clearing lockup after double fault",
531 target_name(target
));
532 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
533 target
->debug_reason
= DBG_REASON_DBGRQ
;
535 /* We have to execute the rest (the "finally" equivalent, but
536 * still throw this exception again).
538 detected_failure
= ERROR_FAIL
;
540 /* refresh status bits */
541 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
542 if (retval
!= ERROR_OK
)
546 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
548 /* check if still in reset */
549 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
550 if (retval
!= ERROR_OK
)
553 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
555 target
->state
= TARGET_RESET
;
560 if (target
->state
== TARGET_RESET
)
562 /* Cannot switch context while running so endreset is
563 * called with target->state == TARGET_RESET
565 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
566 cortex_m3
->dcb_dhcsr
);
567 cortex_m3_endreset_event(target
);
568 target
->state
= TARGET_RUNNING
;
569 prev_target_state
= TARGET_RUNNING
;
572 if (cortex_m3
->dcb_dhcsr
& S_HALT
)
574 target
->state
= TARGET_HALTED
;
576 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
))
578 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
581 if (arm_semihosting(target
, &retval
) != 0)
584 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
586 if (prev_target_state
== TARGET_DEBUG_RUNNING
)
589 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
592 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
596 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
597 * How best to model low power modes?
600 if (target
->state
== TARGET_UNKNOWN
)
602 /* check if processor is retiring instructions */
603 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
)
605 target
->state
= TARGET_RUNNING
;
610 /* Did we detect a failure condition that we cleared? */
611 if (detected_failure
!= ERROR_OK
)
612 retval
= detected_failure
;
616 static int cortex_m3_halt(struct target
*target
)
618 LOG_DEBUG("target->state: %s",
619 target_state_name(target
));
621 if (target
->state
== TARGET_HALTED
)
623 LOG_DEBUG("target was already halted");
627 if (target
->state
== TARGET_UNKNOWN
)
629 LOG_WARNING("target was in unknown state when halt was requested");
632 if (target
->state
== TARGET_RESET
)
634 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
636 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
637 return ERROR_TARGET_FAILURE
;
641 /* we came here in a reset_halt or reset_init sequence
642 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
644 target
->debug_reason
= DBG_REASON_DBGRQ
;
650 /* Write to Debug Halting Control and Status Register */
651 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
653 target
->debug_reason
= DBG_REASON_DBGRQ
;
658 static int cortex_m3_soft_reset_halt(struct target
*target
)
660 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
661 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
662 uint32_t dcb_dhcsr
= 0;
663 int retval
, timeout
= 0;
665 /* Enter debug state on reset; restore DEMCR in endreset_event() */
666 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
,
667 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
668 if (retval
!= ERROR_OK
)
671 /* Request a core-only reset */
672 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
673 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
674 if (retval
!= ERROR_OK
)
676 target
->state
= TARGET_RESET
;
678 /* registers are now invalid */
679 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
681 while (timeout
< 100)
683 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
684 if (retval
== ERROR_OK
)
686 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
687 &cortex_m3
->nvic_dfsr
);
688 if (retval
!= ERROR_OK
)
690 if ((dcb_dhcsr
& S_HALT
)
691 && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
))
693 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
695 (unsigned) dcb_dhcsr
,
696 (unsigned) cortex_m3
->nvic_dfsr
);
697 cortex_m3_poll(target
);
698 /* FIXME restore user's vector catch config */
702 LOG_DEBUG("waiting for system reset-halt, "
703 "DHCSR 0x%08x, %d ms",
704 (unsigned) dcb_dhcsr
, timeout
);
713 static void cortex_m3_enable_breakpoints(struct target
*target
)
715 struct breakpoint
*breakpoint
= target
->breakpoints
;
717 /* set any pending breakpoints */
720 if (!breakpoint
->set
)
721 cortex_m3_set_breakpoint(target
, breakpoint
);
722 breakpoint
= breakpoint
->next
;
726 static int cortex_m3_resume(struct target
*target
, int current
,
727 uint32_t address
, int handle_breakpoints
, int debug_execution
)
729 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
730 struct breakpoint
*breakpoint
= NULL
;
734 if (target
->state
!= TARGET_HALTED
)
736 LOG_WARNING("target not halted");
737 return ERROR_TARGET_NOT_HALTED
;
740 if (!debug_execution
)
742 target_free_all_working_areas(target
);
743 cortex_m3_enable_breakpoints(target
);
744 cortex_m3_enable_watchpoints(target
);
749 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_PRIMASK
;
751 /* Disable interrupts */
752 /* We disable interrupts in the PRIMASK register instead of
753 * masking with C_MASKINTS. This is probably the same issue
754 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
755 * in parallel with disabled interrupts can cause local faults
758 * REVISIT this clearly breaks non-debug execution, since the
759 * PRIMASK register state isn't saved/restored... workaround
760 * by never resuming app code after debug execution.
762 buf_set_u32(r
->value
, 0, 1, 1);
766 /* Make sure we are in Thumb mode */
767 r
= armv7m
->core_cache
->reg_list
+ ARMV7M_xPSR
;
768 buf_set_u32(r
->value
, 24, 1, 1);
773 /* current = 1: continue on current pc, otherwise continue at <address> */
777 buf_set_u32(r
->value
, 0, 32, address
);
782 /* if we halted last time due to a bkpt instruction
783 * then we have to manually step over it, otherwise
784 * the core will break again */
786 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
789 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
792 resume_pc
= buf_get_u32(r
->value
, 0, 32);
794 armv7m_restore_context(target
);
796 /* the front-end may request us not to handle breakpoints */
797 if (handle_breakpoints
)
799 /* Single step past breakpoint at current address */
800 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
802 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
804 breakpoint
->unique_id
);
805 cortex_m3_unset_breakpoint(target
, breakpoint
);
806 cortex_m3_single_step_core(target
);
807 cortex_m3_set_breakpoint(target
, breakpoint
);
812 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
814 target
->debug_reason
= DBG_REASON_NOTHALTED
;
816 /* registers are now invalid */
817 register_cache_invalidate(armv7m
->core_cache
);
819 if (!debug_execution
)
821 target
->state
= TARGET_RUNNING
;
822 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
823 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
827 target
->state
= TARGET_DEBUG_RUNNING
;
828 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
829 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
835 /* int irqstepcount = 0; */
836 static int cortex_m3_step(struct target
*target
, int current
,
837 uint32_t address
, int handle_breakpoints
)
839 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
840 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
841 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
842 struct breakpoint
*breakpoint
= NULL
;
843 struct reg
*pc
= armv7m
->arm
.pc
;
844 bool bkpt_inst_found
= false;
846 bool isr_timed_out
= false;
848 if (target
->state
!= TARGET_HALTED
)
850 LOG_WARNING("target not halted");
851 return ERROR_TARGET_NOT_HALTED
;
854 /* current = 1: continue on current pc, otherwise continue at <address> */
856 buf_set_u32(pc
->value
, 0, 32, address
);
858 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
860 /* the front-end may request us not to handle breakpoints */
861 if (handle_breakpoints
) {
862 breakpoint
= breakpoint_find(target
, pc_value
);
864 cortex_m3_unset_breakpoint(target
, breakpoint
);
867 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
869 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
871 armv7m_restore_context(target
);
873 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
875 /* if no bkpt instruction is found at pc then we can perform
876 * a normal step, otherwise we have to manually step over the bkpt
877 * instruction - as such simulate a step */
878 if (bkpt_inst_found
== false)
880 /* Automatic ISR masking mode off: Just step over the next instruction */
881 if ((cortex_m3
->isrmasking_mode
!= CORTEX_M3_ISRMASK_AUTO
))
883 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
887 /* Process interrupts during stepping in a way they don't interfere
892 * Set a temporary break point at the current pc and let the core run
893 * with interrupts enabled. Pending interrupts get served and we run
894 * into the breakpoint again afterwards. Then we step over the next
895 * instruction with interrupts disabled.
897 * If the pending interrupts don't complete within time, we leave the
898 * core running. This may happen if the interrupts trigger faster
899 * than the core can process them or the handler doesn't return.
901 * If no more breakpoints are available we simply do a step with
902 * interrupts enabled.
906 /* Set a temporary break point */
907 retval
= breakpoint_add(target
, pc_value
, 2, BKPT_TYPE_BY_ADDR(pc_value
));
908 bool tmp_bp_set
= (retval
== ERROR_OK
);
910 /* No more breakpoints left, just do a step */
913 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
918 LOG_DEBUG("Starting core to serve pending interrupts");
919 int64_t t_start
= timeval_ms();
920 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
922 /* Wait for pending handlers to complete or timeout */
924 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
925 if (retval
!= ERROR_OK
)
927 target
->state
= TARGET_UNKNOWN
;
930 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
931 } while (!((cortex_m3
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
933 /* Remove the temporary breakpoint */
934 breakpoint_remove(target
, pc_value
);
938 LOG_DEBUG("Interrupt handlers didn't complete within time, "
939 "leaving target running");
943 /* Step over next instruction with interrupts disabled */
944 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
945 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
946 /* Re-enable interrupts */
947 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
953 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
954 if (retval
!= ERROR_OK
)
957 /* registers are now invalid */
958 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
961 cortex_m3_set_breakpoint(target
, breakpoint
);
964 /* Leave the core running. The user has to stop execution manually. */
965 target
->debug_reason
= DBG_REASON_NOTHALTED
;
966 target
->state
= TARGET_RUNNING
;
970 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
971 " nvic_icsr = 0x%" PRIx32
,
972 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
974 retval
= cortex_m3_debug_entry(target
);
975 if (retval
!= ERROR_OK
)
977 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
979 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
980 " nvic_icsr = 0x%" PRIx32
,
981 cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
986 static int cortex_m3_assert_reset(struct target
*target
)
988 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
989 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
990 enum cortex_m3_soft_reset_config reset_config
= cortex_m3
->soft_reset_config
;
992 LOG_DEBUG("target->state: %s",
993 target_state_name(target
));
995 enum reset_types jtag_reset_config
= jtag_get_reset_config();
997 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
998 /* allow scripts to override the reset event */
1000 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1001 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
1002 target
->state
= TARGET_RESET
;
1007 /* Enable debug requests */
1009 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
1010 if (retval
!= ERROR_OK
)
1012 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
1014 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
1015 if (retval
!= ERROR_OK
)
1019 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
1020 if (retval
!= ERROR_OK
)
1023 if (!target
->reset_halt
)
1025 /* Set/Clear C_MASKINTS in a separate operation */
1026 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
)
1028 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
1029 DBGKEY
| C_DEBUGEN
| C_HALT
);
1030 if (retval
!= ERROR_OK
)
1034 /* clear any debug flags before resuming */
1035 cortex_m3_clear_halt(target
);
1037 /* clear C_HALT in dhcsr reg */
1038 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
1042 /* Halt in debug on reset; endreset_event() restores DEMCR.
1044 * REVISIT catching BUSERR presumably helps to defend against
1045 * bad vector table entries. Should this include MMERR or
1048 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
1049 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1050 if (retval
!= ERROR_OK
)
1054 if (jtag_reset_config
& RESET_HAS_SRST
)
1056 /* default to asserting srst */
1057 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1059 jtag_add_reset(1, 1);
1063 jtag_add_reset(0, 1);
1068 /* Use a standard Cortex-M3 software reset mechanism.
1069 * We default to using VECRESET as it is supported on all current cores.
1070 * This has the disadvantage of not resetting the peripherals, so a
1071 * reset-init event handler is needed to perform any peripheral resets.
1073 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
1074 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1075 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1076 if (retval
!= ERROR_OK
)
1079 LOG_DEBUG("Using Cortex-M3 %s", (reset_config
== CORTEX_M3_RESET_SYSRESETREQ
)
1080 ? "SYSRESETREQ" : "VECTRESET");
1082 if (reset_config
== CORTEX_M3_RESET_VECTRESET
) {
1083 LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
1084 "handler to reset any peripherals");
1088 /* I do not know why this is necessary, but it
1089 * fixes strange effects (step/resume cause NMI
1090 * after reset) on LM3S6918 -- Michael Schwingen
1093 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
1094 if (retval
!= ERROR_OK
)
1099 target
->state
= TARGET_RESET
;
1100 jtag_add_sleep(50000);
1102 register_cache_invalidate(cortex_m3
->armv7m
.core_cache
);
1104 if (target
->reset_halt
)
1106 if ((retval
= target_halt(target
)) != ERROR_OK
)
1113 static int cortex_m3_deassert_reset(struct target
*target
)
1115 LOG_DEBUG("target->state: %s",
1116 target_state_name(target
));
1118 /* deassert reset lines */
1119 jtag_add_reset(0, 0);
1125 cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1130 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1131 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
1133 if (breakpoint
->set
)
1135 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
1139 if (cortex_m3
->auto_bp_type
)
1141 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1144 if (breakpoint
->type
== BKPT_HARD
)
1146 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
1148 if (fp_num
>= cortex_m3
->fp_num_code
)
1150 LOG_ERROR("Can not find free FPB Comparator!");
1153 breakpoint
->set
= fp_num
+ 1;
1154 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1155 comparator_list
[fp_num
].used
= 1;
1156 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
1157 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
1158 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"", fp_num
, comparator_list
[fp_num
].fpcr_value
);
1159 if (!cortex_m3
->fpb_enabled
)
1161 LOG_DEBUG("FPB wasn't enabled, do it now");
1162 target_write_u32(target
, FP_CTRL
, 3);
1165 else if (breakpoint
->type
== BKPT_SOFT
)
1169 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1170 * semihosting; don't use that. Otherwise the BKPT
1171 * parameter is arbitrary.
1173 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1174 retval
= target_read_memory(target
,
1175 breakpoint
->address
& 0xFFFFFFFE,
1176 breakpoint
->length
, 1,
1177 breakpoint
->orig_instr
);
1178 if (retval
!= ERROR_OK
)
1180 retval
= target_write_memory(target
,
1181 breakpoint
->address
& 0xFFFFFFFE,
1182 breakpoint
->length
, 1,
1184 if (retval
!= ERROR_OK
)
1186 breakpoint
->set
= true;
1189 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1190 breakpoint
->unique_id
,
1191 (int)(breakpoint
->type
),
1192 breakpoint
->address
,
1200 cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1203 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1204 struct cortex_m3_fp_comparator
* comparator_list
= cortex_m3
->fp_comparator_list
;
1206 if (!breakpoint
->set
)
1208 LOG_WARNING("breakpoint not set");
1212 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1213 breakpoint
->unique_id
,
1214 (int)(breakpoint
->type
),
1215 breakpoint
->address
,
1219 if (breakpoint
->type
== BKPT_HARD
)
1221 int fp_num
= breakpoint
->set
- 1;
1222 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
))
1224 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1227 comparator_list
[fp_num
].used
= 0;
1228 comparator_list
[fp_num
].fpcr_value
= 0;
1229 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
1233 /* restore original instruction (kept in target endianness) */
1234 if (breakpoint
->length
== 4)
1236 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1243 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
1249 breakpoint
->set
= false;
1255 cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1257 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1259 if (cortex_m3
->auto_bp_type
)
1261 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1262 #ifdef ARMV7_GDB_HACKS
1263 if (breakpoint
->length
!= 2) {
1264 /* XXX Hack: Replace all breakpoints with length != 2 with
1265 * a hardware breakpoint. */
1266 breakpoint
->type
= BKPT_HARD
;
1267 breakpoint
->length
= 2;
1272 if(breakpoint
->type
!= BKPT_TYPE_BY_ADDR(breakpoint
->address
)) {
1273 if (breakpoint
->type
== BKPT_HARD
)
1275 LOG_INFO("flash patch comparator requested outside code memory region");
1276 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1279 if (breakpoint
->type
== BKPT_SOFT
)
1281 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1282 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1286 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1))
1288 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1289 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1292 if ((breakpoint
->length
!= 2))
1294 LOG_INFO("only breakpoints of two bytes length supported");
1295 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1298 if (breakpoint
->type
== BKPT_HARD
)
1299 cortex_m3
->fp_code_available
--;
1301 return cortex_m3_set_breakpoint(target
, breakpoint
);
1305 cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1307 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1309 /* REVISIT why check? FBP can be updated with core running ... */
1310 if (target
->state
!= TARGET_HALTED
)
1312 LOG_WARNING("target not halted");
1313 return ERROR_TARGET_NOT_HALTED
;
1316 if (cortex_m3
->auto_bp_type
)
1318 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1321 if (breakpoint
->set
)
1323 cortex_m3_unset_breakpoint(target
, breakpoint
);
1326 if (breakpoint
->type
== BKPT_HARD
)
1327 cortex_m3
->fp_code_available
++;
1333 cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1336 uint32_t mask
, temp
;
1337 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1339 /* watchpoint params were validated earlier */
1341 temp
= watchpoint
->length
;
1348 /* REVISIT Don't fully trust these "not used" records ... users
1349 * may set up breakpoints by hand, e.g. dual-address data value
1350 * watchpoint using comparator #1; comparator #0 matching cycle
1351 * count; send data trace info through ITM and TPIU; etc
1353 struct cortex_m3_dwt_comparator
*comparator
;
1355 for (comparator
= cortex_m3
->dwt_comparator_list
;
1356 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1357 comparator
++, dwt_num
++)
1359 if (dwt_num
>= cortex_m3
->dwt_num_comp
)
1361 LOG_ERROR("Can not find free DWT Comparator");
1364 comparator
->used
= 1;
1365 watchpoint
->set
= dwt_num
+ 1;
1367 comparator
->comp
= watchpoint
->address
;
1368 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1371 comparator
->mask
= mask
;
1372 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1375 switch (watchpoint
->rw
) {
1377 comparator
->function
= 5;
1380 comparator
->function
= 6;
1383 comparator
->function
= 7;
1386 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1387 comparator
->function
);
1389 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1390 watchpoint
->unique_id
, dwt_num
,
1391 (unsigned) comparator
->comp
,
1392 (unsigned) comparator
->mask
,
1393 (unsigned) comparator
->function
);
1398 cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1400 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1401 struct cortex_m3_dwt_comparator
*comparator
;
1404 if (!watchpoint
->set
)
1406 LOG_WARNING("watchpoint (wpid: %d) not set",
1407 watchpoint
->unique_id
);
1411 dwt_num
= watchpoint
->set
- 1;
1413 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1414 watchpoint
->unique_id
, dwt_num
,
1415 (unsigned) watchpoint
->address
);
1417 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
))
1419 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1423 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1424 comparator
->used
= 0;
1425 comparator
->function
= 0;
1426 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1427 comparator
->function
);
1429 watchpoint
->set
= false;
1435 cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1437 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1439 if (cortex_m3
->dwt_comp_available
< 1)
1441 LOG_DEBUG("no comparators?");
1442 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1445 /* hardware doesn't support data value masking */
1446 if (watchpoint
->mask
!= ~(uint32_t)0) {
1447 LOG_DEBUG("watchpoint value masks not supported");
1448 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1451 /* hardware allows address masks of up to 32K */
1454 for (mask
= 0; mask
< 16; mask
++) {
1455 if ((1u << mask
) == watchpoint
->length
)
1459 LOG_DEBUG("unsupported watchpoint length");
1460 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1462 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1463 LOG_DEBUG("watchpoint address is unaligned");
1464 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1467 /* Caller doesn't seem to be able to describe watching for data
1468 * values of zero; that flags "no value".
1470 * REVISIT This DWT may well be able to watch for specific data
1471 * values. Requires comparator #1 to set DATAVMATCH and match
1472 * the data, and another comparator (DATAVADDR0) matching addr.
1474 if (watchpoint
->value
) {
1475 LOG_DEBUG("data value watchpoint not YET supported");
1476 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1479 cortex_m3
->dwt_comp_available
--;
1480 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1486 cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1488 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1490 /* REVISIT why check? DWT can be updated with core running ... */
1491 if (target
->state
!= TARGET_HALTED
)
1493 LOG_WARNING("target not halted");
1494 return ERROR_TARGET_NOT_HALTED
;
1497 if (watchpoint
->set
)
1499 cortex_m3_unset_watchpoint(target
, watchpoint
);
1502 cortex_m3
->dwt_comp_available
++;
1503 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1508 void cortex_m3_enable_watchpoints(struct target
*target
)
1510 struct watchpoint
*watchpoint
= target
->watchpoints
;
1512 /* set any pending watchpoints */
1515 if (!watchpoint
->set
)
1516 cortex_m3_set_watchpoint(target
, watchpoint
);
1517 watchpoint
= watchpoint
->next
;
1521 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1522 enum armv7m_regtype type
, uint32_t num
, uint32_t * value
)
1525 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1526 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1528 /* NOTE: we "know" here that the register identifiers used
1529 * in the v7m header match the Cortex-M3 Debug Core Register
1530 * Selector values for R0..R15, xPSR, MSP, and PSP.
1534 /* read a normal core register */
1535 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1537 if (retval
!= ERROR_OK
)
1539 LOG_ERROR("JTAG failure %i",retval
);
1540 return ERROR_JTAG_DEVICE_ERROR
;
1542 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"",(int)num
,*value
);
1545 case ARMV7M_PRIMASK
:
1546 case ARMV7M_BASEPRI
:
1547 case ARMV7M_FAULTMASK
:
1548 case ARMV7M_CONTROL
:
1549 /* Cortex-M3 packages these four registers as bitfields
1550 * in one Debug Core register. So say r0 and r2 docs;
1551 * it was removed from r1 docs, but still works.
1553 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1557 case ARMV7M_PRIMASK
:
1558 *value
= buf_get_u32((uint8_t*)value
, 0, 1);
1561 case ARMV7M_BASEPRI
:
1562 *value
= buf_get_u32((uint8_t*)value
, 8, 8);
1565 case ARMV7M_FAULTMASK
:
1566 *value
= buf_get_u32((uint8_t*)value
, 16, 1);
1569 case ARMV7M_CONTROL
:
1570 *value
= buf_get_u32((uint8_t*)value
, 24, 2);
1574 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1578 return ERROR_COMMAND_SYNTAX_ERROR
;
1584 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1585 enum armv7m_regtype type
, uint32_t num
, uint32_t value
)
1589 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1590 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1592 #ifdef ARMV7_GDB_HACKS
1593 /* If the LR register is being modified, make sure it will put us
1594 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1595 * hack to deal with the fact that gdb will sometimes "forge"
1596 * return addresses, and doesn't set the LSB correctly (i.e., when
1597 * printing expressions containing function calls, it sets LR = 0.)
1598 * Valid exception return codes have bit 0 set too.
1600 if (num
== ARMV7M_R14
)
1604 /* NOTE: we "know" here that the register identifiers used
1605 * in the v7m header match the Cortex-M3 Debug Core Register
1606 * Selector values for R0..R15, xPSR, MSP, and PSP.
1610 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1611 if (retval
!= ERROR_OK
)
1615 LOG_ERROR("JTAG failure");
1616 r
= armv7m
->core_cache
->reg_list
+ num
;
1617 r
->dirty
= r
->valid
;
1618 return ERROR_JTAG_DEVICE_ERROR
;
1620 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1623 case ARMV7M_PRIMASK
:
1624 case ARMV7M_BASEPRI
:
1625 case ARMV7M_FAULTMASK
:
1626 case ARMV7M_CONTROL
:
1627 /* Cortex-M3 packages these four registers as bitfields
1628 * in one Debug Core register. So say r0 and r2 docs;
1629 * it was removed from r1 docs, but still works.
1631 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1635 case ARMV7M_PRIMASK
:
1636 buf_set_u32((uint8_t*)®
, 0, 1, value
);
1639 case ARMV7M_BASEPRI
:
1640 buf_set_u32((uint8_t*)®
, 8, 8, value
);
1643 case ARMV7M_FAULTMASK
:
1644 buf_set_u32((uint8_t*)®
, 16, 1, value
);
1647 case ARMV7M_CONTROL
:
1648 buf_set_u32((uint8_t*)®
, 24, 2, value
);
1652 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1654 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1658 return ERROR_COMMAND_SYNTAX_ERROR
;
1664 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1665 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1667 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1668 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1669 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1671 /* cortex_m3 handles unaligned memory access */
1672 if (count
&& buffer
) {
1675 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1678 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1681 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1689 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1690 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1692 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1693 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1694 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1696 if (count
&& buffer
) {
1699 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1702 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1705 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1713 static int cortex_m3_bulk_write_memory(struct target
*target
, uint32_t address
,
1714 uint32_t count
, const uint8_t *buffer
)
1716 return cortex_m3_write_memory(target
, address
, 4, count
, buffer
);
1719 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1720 struct target
*target
)
1722 armv7m_build_reg_cache(target
);
1726 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1727 * on r/w if the core is not running, and clear on resume or reset ... or
1728 * at least, in a post_restore_context() method.
1731 struct dwt_reg_state
{
1732 struct target
*target
;
1734 uint32_t value
; /* scratch/cache */
1737 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1739 struct dwt_reg_state
*state
= reg
->arch_info
;
1741 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1744 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1746 struct dwt_reg_state
*state
= reg
->arch_info
;
1748 return target_write_u32(state
->target
, state
->addr
,
1749 buf_get_u32(buf
, 0, reg
->size
));
1758 static struct dwt_reg dwt_base_regs
[] = {
1759 { DWT_CTRL
, "dwt_ctrl", 32, },
1760 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1761 * increments while the core is asleep.
1763 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1764 /* plus some 8 bit counters, useful for profiling with TPIU */
1767 static struct dwt_reg dwt_comp
[] = {
1768 #define DWT_COMPARATOR(i) \
1769 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1770 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1771 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1776 #undef DWT_COMPARATOR
1779 static const struct reg_arch_type dwt_reg_type
= {
1780 .get
= cortex_m3_dwt_get_reg
,
1781 .set
= cortex_m3_dwt_set_reg
,
1785 cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1787 struct dwt_reg_state
*state
;
1789 state
= calloc(1, sizeof *state
);
1792 state
->addr
= d
->addr
;
1797 r
->value
= &state
->value
;
1798 r
->arch_info
= state
;
1799 r
->type
= &dwt_reg_type
;
1803 cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1806 struct reg_cache
*cache
;
1807 struct cortex_m3_dwt_comparator
*comparator
;
1810 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1812 LOG_DEBUG("no DWT");
1816 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1817 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1818 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1819 sizeof(struct cortex_m3_dwt_comparator
));
1820 if (!cm3
->dwt_comparator_list
) {
1822 cm3
->dwt_num_comp
= 0;
1823 LOG_ERROR("out of mem");
1827 cache
= calloc(1, sizeof *cache
);
1830 free(cm3
->dwt_comparator_list
);
1833 cache
->name
= "cortex-m3 dwt registers";
1834 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1835 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1836 if (!cache
->reg_list
) {
1841 for (reg
= 0; reg
< 2; reg
++)
1842 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1843 dwt_base_regs
+ reg
);
1845 comparator
= cm3
->dwt_comparator_list
;
1846 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1849 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1850 for (j
= 0; j
< 3; j
++, reg
++)
1851 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1852 dwt_comp
+ 3 * i
+ j
);
1855 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1856 cm3
->dwt_cache
= cache
;
1858 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1859 dwtcr
, cm3
->dwt_num_comp
,
1860 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1862 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1863 * implement single-address data value watchpoints ... so we
1864 * won't need to check it later, when asked to set one up.
1868 static int cortex_m3_examine(struct target
*target
)
1871 uint32_t cpuid
, fpcr
;
1873 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1874 struct adiv5_dap
*swjdp
= &cortex_m3
->armv7m
.dap
;
1876 if ((retval
= ahbap_debugport_init(swjdp
)) != ERROR_OK
)
1879 if (!target_was_examined(target
))
1881 target_set_examined(target
);
1883 /* Read from Device Identification Registers */
1884 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1885 if (retval
!= ERROR_OK
)
1888 if (((cpuid
>> 4) & 0xc3f) == 0xc23)
1889 LOG_DEBUG("Cortex-M3 r%" PRId8
"p%" PRId8
" processor detected",
1890 (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1891 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1893 /* NOTE: FPB and DWT are both optional. */
1896 target_read_u32(target
, FP_CTRL
, &fpcr
);
1897 cortex_m3
->auto_bp_type
= 1;
1898 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits [14:12] and [7:4] */
1899 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1900 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1901 cortex_m3
->fp_comparator_list
= calloc(cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
, sizeof(struct cortex_m3_fp_comparator
));
1902 cortex_m3
->fpb_enabled
= fpcr
& 1;
1903 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
1905 cortex_m3
->fp_comparator_list
[i
].type
= (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1906 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1908 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i", fpcr
, cortex_m3
->fp_num_code
, cortex_m3
->fp_num_lit
);
1911 cortex_m3_dwt_setup(cortex_m3
, target
);
1913 /* These hardware breakpoints only work for code in flash! */
1914 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1915 target_name(target
),
1916 cortex_m3
->fp_num_code
,
1917 cortex_m3
->dwt_num_comp
);
1923 static int cortex_m3_dcc_read(struct adiv5_dap
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1928 mem_ap_read_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1929 *ctrl
= (uint8_t)dcrdr
;
1930 *value
= (uint8_t)(dcrdr
>> 8);
1932 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1934 /* write ack back to software dcc register
1935 * signify we have read data */
1936 if (dcrdr
& (1 << 0))
1939 retval
= mem_ap_write_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1940 if (retval
!= ERROR_OK
)
1947 static int cortex_m3_target_request_data(struct target
*target
,
1948 uint32_t size
, uint8_t *buffer
)
1950 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1951 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1956 for (i
= 0; i
< (size
* 4); i
++)
1958 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1965 static int cortex_m3_handle_target_request(void *priv
)
1967 struct target
*target
= priv
;
1968 if (!target_was_examined(target
))
1970 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1971 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
1973 if (!target
->dbg_msg_enabled
)
1976 if (target
->state
== TARGET_RUNNING
)
1981 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1983 /* check if we have data */
1984 if (ctrl
& (1 << 0))
1988 /* we assume target is quick enough */
1990 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1991 request
|= (data
<< 8);
1992 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1993 request
|= (data
<< 16);
1994 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1995 request
|= (data
<< 24);
1996 target_request(target
, request
);
2003 static int cortex_m3_init_arch_info(struct target
*target
,
2004 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
2007 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
2009 armv7m_init_arch_info(target
, armv7m
);
2011 /* prepare JTAG information for the new target */
2012 cortex_m3
->jtag_info
.tap
= tap
;
2013 cortex_m3
->jtag_info
.scann_size
= 4;
2015 /* default reset mode is to use srst if fitted
2016 * if not it will use CORTEX_M3_RESET_VECTRESET */
2017 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
2019 armv7m
->arm
.dap
= &armv7m
->dap
;
2021 /* Leave (only) generic DAP stuff for debugport_init(); */
2022 armv7m
->dap
.jtag_info
= &cortex_m3
->jtag_info
;
2023 armv7m
->dap
.memaccess_tck
= 8;
2024 /* Cortex-M3 has 4096 bytes autoincrement range */
2025 armv7m
->dap
.tar_autoincr_block
= (1 << 12);
2027 /* register arch-specific functions */
2028 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
2030 armv7m
->post_debug_entry
= NULL
;
2032 armv7m
->pre_restore_context
= NULL
;
2034 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
2035 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
2037 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
2039 if ((retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
)) != ERROR_OK
)
2047 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
2049 struct cortex_m3_common
*cortex_m3
= calloc(1,sizeof(struct cortex_m3_common
));
2051 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
2052 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
2057 /*--------------------------------------------------------------------------*/
2059 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
2060 struct cortex_m3_common
*cm3
)
2062 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
2063 command_print(cmd_ctx
, "target is not a Cortex-M3");
2064 return ERROR_TARGET_INVALID
;
2070 * Only stuff below this line should need to verify that its target
2071 * is a Cortex-M3. Everything else should have indirected through the
2072 * cortexm3_target structure, which is only used with CM3 targets.
2075 static const struct {
2079 { "hard_err", VC_HARDERR
, },
2080 { "int_err", VC_INTERR
, },
2081 { "bus_err", VC_BUSERR
, },
2082 { "state_err", VC_STATERR
, },
2083 { "chk_err", VC_CHKERR
, },
2084 { "nocp_err", VC_NOCPERR
, },
2085 { "mm_err", VC_MMERR
, },
2086 { "reset", VC_CORERESET
, },
2089 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
2091 struct target
*target
= get_current_target(CMD_CTX
);
2092 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2093 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
2094 struct adiv5_dap
*swjdp
= &armv7m
->dap
;
2098 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2099 if (retval
!= ERROR_OK
)
2102 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2103 if (retval
!= ERROR_OK
)
2109 if (CMD_ARGC
== 1) {
2110 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2111 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2112 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2113 | VC_MMERR
| VC_CORERESET
;
2115 } else if (strcmp(CMD_ARGV
[0], "none") == 0) {
2119 while (CMD_ARGC
-- > 0) {
2121 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2122 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2124 catch |= vec_ids
[i
].mask
;
2127 if (i
== ARRAY_SIZE(vec_ids
)) {
2128 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2129 return ERROR_COMMAND_SYNTAX_ERROR
;
2133 /* For now, armv7m->demcr only stores vector catch flags. */
2134 armv7m
->demcr
= catch;
2139 /* write, but don't assume it stuck (why not??) */
2140 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
2141 if (retval
!= ERROR_OK
)
2143 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2144 if (retval
!= ERROR_OK
)
2147 /* FIXME be sure to clear DEMCR on clean server shutdown.
2148 * Otherwise the vector catch hardware could fire when there's
2149 * no debugger hooked up, causing much confusion...
2153 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++)
2155 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2156 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2162 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
2164 struct target
*target
= get_current_target(CMD_CTX
);
2165 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2168 static const Jim_Nvp nvp_maskisr_modes
[] = {
2169 { .name
= "auto", .value
= CORTEX_M3_ISRMASK_AUTO
},
2170 { .name
= "off" , .value
= CORTEX_M3_ISRMASK_OFF
},
2171 { .name
= "on" , .value
= CORTEX_M3_ISRMASK_ON
},
2172 { .name
= NULL
, .value
= -1 },
2177 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2178 if (retval
!= ERROR_OK
)
2181 if (target
->state
!= TARGET_HALTED
)
2183 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2189 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2190 if (n
->name
== NULL
)
2192 return ERROR_COMMAND_SYNTAX_ERROR
;
2194 cortex_m3
->isrmasking_mode
= n
->value
;
2197 if(cortex_m3
->isrmasking_mode
== CORTEX_M3_ISRMASK_ON
)
2199 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
2203 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
2207 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m3
->isrmasking_mode
);
2208 command_print(CMD_CTX
, "cortex_m3 interrupt mask %s", n
->name
);
2213 COMMAND_HANDLER(handle_cortex_m3_reset_config_command
)
2215 struct target
*target
= get_current_target(CMD_CTX
);
2216 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
2220 retval
= cortex_m3_verify_pointer(CMD_CTX
, cortex_m3
);
2221 if (retval
!= ERROR_OK
)
2226 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2227 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_SYSRESETREQ
;
2228 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2229 cortex_m3
->soft_reset_config
= CORTEX_M3_RESET_VECTRESET
;
2232 switch (cortex_m3
->soft_reset_config
)
2234 case CORTEX_M3_RESET_SYSRESETREQ
:
2235 reset_config
= "sysresetreq";
2238 case CORTEX_M3_RESET_VECTRESET
:
2239 reset_config
= "vectreset";
2243 reset_config
= "unknown";
2247 command_print(CMD_CTX
, "cortex_m3 reset_config %s", reset_config
);
2252 static const struct command_registration cortex_m3_exec_command_handlers
[] = {
2255 .handler
= handle_cortex_m3_mask_interrupts_command
,
2256 .mode
= COMMAND_EXEC
,
2257 .help
= "mask cortex_m3 interrupts",
2258 .usage
= "['auto'|'on'|'off']",
2261 .name
= "vector_catch",
2262 .handler
= handle_cortex_m3_vector_catch_command
,
2263 .mode
= COMMAND_EXEC
,
2264 .help
= "configure hardware vectors to trigger debug entry",
2265 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2268 .name
= "reset_config",
2269 .handler
= handle_cortex_m3_reset_config_command
,
2270 .mode
= COMMAND_ANY
,
2271 .help
= "configure software reset handling",
2272 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2274 COMMAND_REGISTRATION_DONE
2276 static const struct command_registration cortex_m3_command_handlers
[] = {
2278 .chain
= armv7m_command_handlers
,
2281 .name
= "cortex_m3",
2282 .mode
= COMMAND_EXEC
,
2283 .help
= "Cortex-M3 command group",
2285 .chain
= cortex_m3_exec_command_handlers
,
2287 COMMAND_REGISTRATION_DONE
2290 struct target_type cortexm3_target
=
2292 .name
= "cortex_m3",
2294 .poll
= cortex_m3_poll
,
2295 .arch_state
= armv7m_arch_state
,
2297 .target_request_data
= cortex_m3_target_request_data
,
2299 .halt
= cortex_m3_halt
,
2300 .resume
= cortex_m3_resume
,
2301 .step
= cortex_m3_step
,
2303 .assert_reset
= cortex_m3_assert_reset
,
2304 .deassert_reset
= cortex_m3_deassert_reset
,
2305 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
2307 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2309 .read_memory
= cortex_m3_read_memory
,
2310 .write_memory
= cortex_m3_write_memory
,
2311 .bulk_write_memory
= cortex_m3_bulk_write_memory
,
2312 .checksum_memory
= armv7m_checksum_memory
,
2313 .blank_check_memory
= armv7m_blank_check_memory
,
2315 .run_algorithm
= armv7m_run_algorithm
,
2316 .start_algorithm
= armv7m_start_algorithm
,
2317 .wait_algorithm
= armv7m_wait_algorithm
,
2319 .add_breakpoint
= cortex_m3_add_breakpoint
,
2320 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
2321 .add_watchpoint
= cortex_m3_add_watchpoint
,
2322 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
2324 .commands
= cortex_m3_command_handlers
,
2325 .target_create
= cortex_m3_target_create
,
2326 .init_target
= cortex_m3_init_target
,
2327 .examine
= cortex_m3_examine
,
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